2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_format_s3tc.h>
31 #include <util/u_math.h>
32 #include <util/u_inlines.h>
33 #include <util/u_memory.h>
34 #include "state_tracker/drm_driver.h"
35 #include "pipebuffer/pb_buffer.h"
36 #include "r600_pipe.h"
37 #include "r600_resource.h"
38 #include "r600_state_inlines.h"
40 #include "r600_formats.h"
42 /* Copy from a full GPU texture to a transfer's staging one. */
43 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
45 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
46 struct pipe_resource
*texture
= transfer
->resource
;
48 ctx
->resource_copy_region(ctx
, rtransfer
->staging_texture
,
49 0, 0, 0, 0, texture
, transfer
->level
,
54 /* Copy from a transfer's staging texture to a full GPU one. */
55 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
57 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
58 struct pipe_resource
*texture
= transfer
->resource
;
61 sbox
.x
= sbox
.y
= sbox
.z
= 0;
62 sbox
.width
= transfer
->box
.width
;
63 sbox
.height
= transfer
->box
.height
;
64 /* XXX that might be wrong */
66 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
67 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
68 rtransfer
->staging_texture
,
71 ctx
->flush(ctx
, 0, NULL
);
74 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
75 unsigned level
, unsigned layer
)
77 unsigned offset
= rtex
->offset
[level
];
79 switch (rtex
->resource
.b
.b
.b
.target
) {
81 case PIPE_TEXTURE_CUBE
:
82 return offset
+ layer
* rtex
->layer_size
[level
];
89 static unsigned r600_get_block_alignment(struct pipe_screen
*screen
,
90 enum pipe_format format
,
93 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
94 unsigned pixsize
= util_format_get_blocksize(format
);
98 case V_038000_ARRAY_1D_TILED_THIN1
:
100 ((rscreen
->tiling_info
->group_bytes
/ 8 / pixsize
)));
102 case V_038000_ARRAY_2D_TILED_THIN1
:
103 p_align
= MAX2(rscreen
->tiling_info
->num_banks
,
104 (((rscreen
->tiling_info
->group_bytes
/ 8 / pixsize
)) *
105 rscreen
->tiling_info
->num_banks
)) * 8;
107 case V_038000_ARRAY_LINEAR_ALIGNED
:
108 p_align
= MAX2(64, rscreen
->tiling_info
->group_bytes
/ pixsize
);
110 case V_038000_ARRAY_LINEAR_GENERAL
:
112 p_align
= rscreen
->tiling_info
->group_bytes
/ pixsize
;
118 static unsigned r600_get_height_alignment(struct pipe_screen
*screen
,
121 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
124 switch (array_mode
) {
125 case V_038000_ARRAY_2D_TILED_THIN1
:
126 h_align
= rscreen
->tiling_info
->num_channels
* 8;
128 case V_038000_ARRAY_1D_TILED_THIN1
:
129 case V_038000_ARRAY_LINEAR_ALIGNED
:
132 case V_038000_ARRAY_LINEAR_GENERAL
:
140 static unsigned r600_get_base_alignment(struct pipe_screen
*screen
,
141 enum pipe_format format
,
144 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
145 unsigned pixsize
= util_format_get_blocksize(format
);
146 int p_align
= r600_get_block_alignment(screen
, format
, array_mode
);
147 int h_align
= r600_get_height_alignment(screen
, array_mode
);
150 switch (array_mode
) {
151 case V_038000_ARRAY_2D_TILED_THIN1
:
152 b_align
= MAX2(rscreen
->tiling_info
->num_banks
* rscreen
->tiling_info
->num_channels
* 8 * 8 * pixsize
,
153 p_align
* pixsize
* h_align
);
155 case V_038000_ARRAY_1D_TILED_THIN1
:
156 case V_038000_ARRAY_LINEAR_ALIGNED
:
157 case V_038000_ARRAY_LINEAR_GENERAL
:
159 b_align
= rscreen
->tiling_info
->group_bytes
;
165 static unsigned mip_minify(unsigned size
, unsigned level
)
168 val
= u_minify(size
, level
);
170 val
= util_next_power_of_two(val
);
174 static unsigned r600_texture_get_nblocksx(struct pipe_screen
*screen
,
175 struct r600_resource_texture
*rtex
,
178 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
179 unsigned nblocksx
, block_align
, width
;
180 unsigned blocksize
= util_format_get_blocksize(ptex
->format
);
182 if (rtex
->pitch_override
)
183 return rtex
->pitch_override
/ blocksize
;
185 width
= mip_minify(ptex
->width0
, level
);
186 nblocksx
= util_format_get_nblocksx(ptex
->format
, width
);
188 block_align
= r600_get_block_alignment(screen
, ptex
->format
,
189 rtex
->array_mode
[level
]);
190 nblocksx
= align(nblocksx
, block_align
);
194 static unsigned r600_texture_get_nblocksy(struct pipe_screen
*screen
,
195 struct r600_resource_texture
*rtex
,
198 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
199 unsigned height
, tile_height
;
201 height
= mip_minify(ptex
->height0
, level
);
202 height
= util_format_get_nblocksy(ptex
->format
, height
);
203 tile_height
= r600_get_height_alignment(screen
,
204 rtex
->array_mode
[level
]);
205 height
= align(height
, tile_height
);
209 static void r600_texture_set_array_mode(struct pipe_screen
*screen
,
210 struct r600_resource_texture
*rtex
,
211 unsigned level
, unsigned array_mode
)
213 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
215 switch (array_mode
) {
216 case V_0280A0_ARRAY_LINEAR_GENERAL
:
217 case V_0280A0_ARRAY_LINEAR_ALIGNED
:
218 case V_0280A0_ARRAY_1D_TILED_THIN1
:
220 rtex
->array_mode
[level
] = array_mode
;
222 case V_0280A0_ARRAY_2D_TILED_THIN1
:
224 unsigned w
, h
, tile_height
, tile_width
;
226 tile_height
= r600_get_height_alignment(screen
, array_mode
);
227 tile_width
= r600_get_block_alignment(screen
, ptex
->format
, array_mode
);
229 w
= mip_minify(ptex
->width0
, level
);
230 h
= mip_minify(ptex
->height0
, level
);
231 if (w
< tile_width
|| h
< tile_height
)
232 rtex
->array_mode
[level
] = V_0280A0_ARRAY_1D_TILED_THIN1
;
234 rtex
->array_mode
[level
] = array_mode
;
240 static void r600_setup_miptree(struct pipe_screen
*screen
,
241 struct r600_resource_texture
*rtex
,
244 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
245 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
246 enum chip_class chipc
= r600_get_family_class(radeon
);
247 unsigned size
, layer_size
, i
, offset
;
248 unsigned nblocksx
, nblocksy
;
250 for (i
= 0, offset
= 0; i
<= ptex
->last_level
; i
++) {
251 unsigned blocksize
= util_format_get_blocksize(ptex
->format
);
253 r600_texture_set_array_mode(screen
, rtex
, i
, array_mode
);
255 nblocksx
= r600_texture_get_nblocksx(screen
, rtex
, i
);
256 nblocksy
= r600_texture_get_nblocksy(screen
, rtex
, i
);
258 layer_size
= nblocksx
* nblocksy
* blocksize
;
259 if (ptex
->target
== PIPE_TEXTURE_CUBE
) {
261 size
= layer_size
* 8;
263 size
= layer_size
* 6;
266 size
= layer_size
* u_minify(ptex
->depth0
, i
);
267 /* align base image and start of miptree */
268 if ((i
== 0) || (i
== 1))
269 offset
= align(offset
, r600_get_base_alignment(screen
, ptex
->format
, array_mode
));
270 rtex
->offset
[i
] = offset
;
271 rtex
->layer_size
[i
] = layer_size
;
272 rtex
->pitch_in_blocks
[i
] = nblocksx
; /* CB talks in elements */
273 rtex
->pitch_in_bytes
[i
] = nblocksx
* blocksize
;
280 /* Figure out whether u_blitter will fallback to a transfer operation.
281 * If so, don't use a staging resource.
283 static boolean
permit_hardware_blit(struct pipe_screen
*screen
,
284 const struct pipe_resource
*res
)
288 if (util_format_is_depth_or_stencil(res
->format
))
289 bind
= PIPE_BIND_DEPTH_STENCIL
;
291 bind
= PIPE_BIND_RENDER_TARGET
;
293 /* hackaround for S3TC */
294 if (util_format_is_s3tc(res
->format
))
297 if (!screen
->is_format_supported(screen
,
304 if (!screen
->is_format_supported(screen
,
308 PIPE_BIND_SAMPLER_VIEW
, 0))
314 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
315 struct pipe_resource
*ptex
,
316 struct winsys_handle
*whandle
)
318 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
319 struct r600_resource
*resource
= &rtex
->resource
;
320 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
322 return r600_bo_get_winsys_handle(radeon
, resource
->bo
,
323 rtex
->pitch_in_bytes
[0], whandle
);
326 static void r600_texture_destroy(struct pipe_screen
*screen
,
327 struct pipe_resource
*ptex
)
329 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
330 struct r600_resource
*resource
= &rtex
->resource
;
331 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
333 if (rtex
->flushed_depth_texture
)
334 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
337 r600_bo_reference(radeon
, &resource
->bo
, NULL
);
342 static unsigned int r600_texture_is_referenced(struct pipe_context
*context
,
343 struct pipe_resource
*texture
,
344 unsigned level
, int layer
)
347 return PIPE_REFERENCED_FOR_READ
| PIPE_REFERENCED_FOR_WRITE
;
350 static const struct u_resource_vtbl r600_texture_vtbl
=
352 r600_texture_get_handle
, /* get_handle */
353 r600_texture_destroy
, /* resource_destroy */
354 r600_texture_is_referenced
, /* is_resource_referenced */
355 r600_texture_get_transfer
, /* get_transfer */
356 r600_texture_transfer_destroy
, /* transfer_destroy */
357 r600_texture_transfer_map
, /* transfer_map */
358 u_default_transfer_flush_region
,/* transfer_flush_region */
359 r600_texture_transfer_unmap
, /* transfer_unmap */
360 u_default_transfer_inline_write
/* transfer_inline_write */
363 static struct r600_resource_texture
*
364 r600_texture_create_object(struct pipe_screen
*screen
,
365 const struct pipe_resource
*base
,
367 unsigned pitch_in_bytes_override
,
368 unsigned max_buffer_size
,
371 struct r600_resource_texture
*rtex
;
372 struct r600_resource
*resource
;
373 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
375 rtex
= CALLOC_STRUCT(r600_resource_texture
);
379 resource
= &rtex
->resource
;
380 resource
->b
.b
.b
= *base
;
381 resource
->b
.b
.vtbl
= &r600_texture_vtbl
;
382 pipe_reference_init(&resource
->b
.b
.b
.reference
, 1);
383 resource
->b
.b
.b
.screen
= screen
;
385 rtex
->pitch_override
= pitch_in_bytes_override
;
386 /* only mark depth textures the HW can hit as depth textures */
387 if (util_format_is_depth_or_stencil(base
->format
) && permit_hardware_blit(screen
, base
))
390 r600_setup_miptree(screen
, rtex
, array_mode
);
392 resource
->size
= rtex
->size
;
395 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
396 int base_align
= r600_get_base_alignment(screen
, ptex
->format
, array_mode
);
398 resource
->bo
= r600_bo(radeon
, rtex
->size
, base_align
, base
->bind
, base
->usage
);
407 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
408 const struct pipe_resource
*templ
)
410 unsigned array_mode
= 0;
411 static int force_tiling
= -1;
413 /* Would like some magic "get_bool_option_once" routine.
415 if (force_tiling
== -1)
416 force_tiling
= debug_get_bool_option("R600_FORCE_TILING", FALSE
);
418 if (force_tiling
&& permit_hardware_blit(screen
, templ
)) {
419 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
420 !(templ
->bind
& PIPE_BIND_SCANOUT
)) {
421 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
425 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
426 util_format_is_s3tc(templ
->format
))
427 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
429 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
434 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
435 struct pipe_resource
*texture
,
436 const struct pipe_surface
*surf_tmpl
)
438 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
439 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
440 unsigned level
= surf_tmpl
->u
.tex
.level
;
442 assert(surf_tmpl
->u
.tex
.first_layer
== surf_tmpl
->u
.tex
.last_layer
);
446 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
447 pipe_reference_init(&surface
->base
.reference
, 1);
448 pipe_resource_reference(&surface
->base
.texture
, texture
);
449 surface
->base
.context
= pipe
;
450 surface
->base
.format
= surf_tmpl
->format
;
451 surface
->base
.width
= mip_minify(texture
->width0
, level
);
452 surface
->base
.height
= mip_minify(texture
->height0
, level
);
453 surface
->base
.usage
= surf_tmpl
->usage
;
454 surface
->base
.texture
= texture
;
455 surface
->base
.u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
456 surface
->base
.u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
457 surface
->base
.u
.tex
.level
= level
;
459 surface
->aligned_height
= r600_texture_get_nblocksy(pipe
->screen
,
461 return &surface
->base
;
464 static void r600_surface_destroy(struct pipe_context
*pipe
,
465 struct pipe_surface
*surface
)
467 pipe_resource_reference(&surface
->texture
, NULL
);
472 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
473 const struct pipe_resource
*templ
,
474 struct winsys_handle
*whandle
)
476 struct radeon
*rw
= (struct radeon
*)screen
->winsys
;
477 struct r600_bo
*bo
= NULL
;
478 unsigned array_mode
= 0;
480 /* Support only 2D textures without mipmaps */
481 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
482 templ
->depth0
!= 1 || templ
->last_level
!= 0)
485 bo
= r600_bo_handle(rw
, whandle
->handle
, &array_mode
);
490 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
496 int r600_texture_depth_flush(struct pipe_context
*ctx
,
497 struct pipe_resource
*texture
, boolean just_create
)
499 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
500 struct pipe_resource resource
;
502 if (rtex
->flushed_depth_texture
)
505 resource
.target
= PIPE_TEXTURE_2D
;
506 resource
.format
= texture
->format
;
507 resource
.width0
= texture
->width0
;
508 resource
.height0
= texture
->height0
;
510 resource
.last_level
= texture
->last_level
;
511 resource
.nr_samples
= 0;
512 resource
.usage
= PIPE_USAGE_DYNAMIC
;
514 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
516 resource
.bind
|= PIPE_BIND_DEPTH_STENCIL
;
518 rtex
->flushed_depth_texture
= (struct r600_resource_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
519 if (rtex
->flushed_depth_texture
== NULL
) {
520 R600_ERR("failed to create temporary texture to hold untiled copy\n");
524 ((struct r600_resource_texture
*)rtex
->flushed_depth_texture
)->is_flushing_texture
= TRUE
;
529 /* XXX: only do this if the depth texture has actually changed:
531 r600_blit_uncompress_depth(ctx
, rtex
);
535 /* Needs adjustment for pixelformat:
537 static INLINE
unsigned u_box_volume( const struct pipe_box
*box
)
539 return box
->width
* box
->depth
* box
->height
;
542 struct pipe_transfer
* r600_texture_get_transfer(struct pipe_context
*ctx
,
543 struct pipe_resource
*texture
,
546 const struct pipe_box
*box
)
548 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
549 struct pipe_resource resource
;
550 struct r600_transfer
*trans
;
552 boolean use_staging_texture
= FALSE
;
554 /* We cannot map a tiled texture directly because the data is
555 * in a different order, therefore we do detiling using a blit.
557 * Also, use a temporary in GTT memory for read transfers, as
558 * the CPU is much happier reading out of cached system memory
559 * than uncached VRAM.
561 if (R600_TEX_IS_TILED(rtex
, level
))
562 use_staging_texture
= TRUE
;
564 if ((usage
& PIPE_TRANSFER_READ
) && u_box_volume(box
) > 1024)
565 use_staging_texture
= TRUE
;
567 /* XXX: Use a staging texture for uploads if the underlying BO
568 * is busy. No interface for checking that currently? so do
569 * it eagerly whenever the transfer doesn't require a readback
572 if ((usage
& PIPE_TRANSFER_WRITE
) &&
573 !(usage
& (PIPE_TRANSFER_READ
|
574 PIPE_TRANSFER_DONTBLOCK
|
575 PIPE_TRANSFER_UNSYNCHRONIZED
)))
576 use_staging_texture
= TRUE
;
578 if (!permit_hardware_blit(ctx
->screen
, texture
) ||
579 (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
))
580 use_staging_texture
= FALSE
;
582 trans
= CALLOC_STRUCT(r600_transfer
);
585 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
586 trans
->transfer
.level
= level
;
587 trans
->transfer
.usage
= usage
;
588 trans
->transfer
.box
= *box
;
590 /* XXX: only readback the rectangle which is being mapped?
592 /* XXX: when discard is true, no need to read back from depth texture
594 r
= r600_texture_depth_flush(ctx
, texture
, FALSE
);
596 R600_ERR("failed to create temporary texture to hold untiled copy\n");
597 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
601 trans
->transfer
.stride
= rtex
->flushed_depth_texture
->pitch_in_bytes
[level
];
602 trans
->offset
= r600_texture_get_offset(rtex
->flushed_depth_texture
, level
, box
->z
);
603 return &trans
->transfer
;
604 } else if (use_staging_texture
) {
605 resource
.target
= PIPE_TEXTURE_2D
;
606 resource
.format
= texture
->format
;
607 resource
.width0
= box
->width
;
608 resource
.height0
= box
->height
;
610 resource
.array_size
= 1;
611 resource
.last_level
= 0;
612 resource
.nr_samples
= 0;
613 resource
.usage
= PIPE_USAGE_STAGING
;
615 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
616 /* For texture reading, the temporary (detiled) texture is used as
617 * a render target when blitting from a tiled texture. */
618 if (usage
& PIPE_TRANSFER_READ
) {
619 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
621 /* For texture writing, the temporary texture is used as a sampler
622 * when blitting into a tiled texture. */
623 if (usage
& PIPE_TRANSFER_WRITE
) {
624 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
626 /* Create the temporary texture. */
627 trans
->staging_texture
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
628 if (trans
->staging_texture
== NULL
) {
629 R600_ERR("failed to create temporary texture to hold untiled copy\n");
630 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
635 trans
->transfer
.stride
=
636 ((struct r600_resource_texture
*)trans
->staging_texture
)->pitch_in_bytes
[0];
637 if (usage
& PIPE_TRANSFER_READ
) {
638 r600_copy_to_staging_texture(ctx
, trans
);
639 /* Always referenced in the blit. */
640 ctx
->flush(ctx
, 0, NULL
);
642 return &trans
->transfer
;
644 trans
->transfer
.stride
= rtex
->pitch_in_bytes
[level
];
645 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
646 return &trans
->transfer
;
649 void r600_texture_transfer_destroy(struct pipe_context
*ctx
,
650 struct pipe_transfer
*transfer
)
652 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
653 struct pipe_resource
*texture
= transfer
->resource
;
654 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
656 if (rtransfer
->staging_texture
) {
657 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
658 r600_copy_from_staging_texture(ctx
, rtransfer
);
660 pipe_resource_reference(&rtransfer
->staging_texture
, NULL
);
663 if (rtex
->depth
&& !rtex
->is_flushing_texture
) {
664 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtex
->flushed_depth_texture
)
665 r600_blit_push_depth(ctx
, rtex
);
668 pipe_resource_reference(&transfer
->resource
, NULL
);
672 void* r600_texture_transfer_map(struct pipe_context
*ctx
,
673 struct pipe_transfer
* transfer
)
675 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
677 enum pipe_format format
= transfer
->resource
->format
;
678 struct radeon
*radeon
= (struct radeon
*)ctx
->screen
->winsys
;
683 if (rtransfer
->staging_texture
) {
684 bo
= ((struct r600_resource
*)rtransfer
->staging_texture
)->bo
;
686 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
688 if (rtex
->flushed_depth_texture
)
689 bo
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->bo
;
691 bo
= ((struct r600_resource
*)transfer
->resource
)->bo
;
693 offset
= rtransfer
->offset
+
694 transfer
->box
.y
/ util_format_get_blockheight(format
) * transfer
->stride
+
695 transfer
->box
.x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
698 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
699 usage
|= PB_USAGE_CPU_WRITE
;
701 if (transfer
->usage
& PIPE_TRANSFER_DISCARD
) {
704 if (transfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
) {
708 if (transfer
->usage
& PIPE_TRANSFER_READ
) {
709 usage
|= PB_USAGE_CPU_READ
;
712 if (transfer
->usage
& PIPE_TRANSFER_DONTBLOCK
) {
713 usage
|= PB_USAGE_DONTBLOCK
;
716 if (transfer
->usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
717 usage
|= PB_USAGE_UNSYNCHRONIZED
;
720 map
= r600_bo_map(radeon
, bo
, usage
, ctx
);
728 void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
729 struct pipe_transfer
* transfer
)
731 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
732 struct radeon
*radeon
= (struct radeon
*)ctx
->screen
->winsys
;
735 if (rtransfer
->staging_texture
) {
736 bo
= ((struct r600_resource
*)rtransfer
->staging_texture
)->bo
;
738 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
740 if (rtex
->flushed_depth_texture
) {
741 bo
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->bo
;
743 bo
= ((struct r600_resource
*)transfer
->resource
)->bo
;
746 r600_bo_unmap(radeon
, bo
);
749 void r600_init_surface_functions(struct r600_pipe_context
*r600
)
751 r600
->context
.create_surface
= r600_create_surface
;
752 r600
->context
.surface_destroy
= r600_surface_destroy
;
755 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
756 const unsigned char *swizzle_view
)
759 unsigned char swizzle
[4];
761 const uint32_t swizzle_shift
[4] = {
764 const uint32_t swizzle_bit
[4] = {
769 /* Combine two sets of swizzles. */
770 for (i
= 0; i
< 4; i
++) {
771 swizzle
[i
] = swizzle_view
[i
] <= UTIL_FORMAT_SWIZZLE_W
?
772 swizzle_format
[swizzle_view
[i
]] : swizzle_view
[i
];
775 memcpy(swizzle
, swizzle_format
, 4);
779 for (i
= 0; i
< 4; i
++) {
780 switch (swizzle
[i
]) {
781 case UTIL_FORMAT_SWIZZLE_Y
:
782 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
784 case UTIL_FORMAT_SWIZZLE_Z
:
785 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
787 case UTIL_FORMAT_SWIZZLE_W
:
788 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
790 case UTIL_FORMAT_SWIZZLE_0
:
791 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
793 case UTIL_FORMAT_SWIZZLE_1
:
794 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
796 default: /* UTIL_FORMAT_SWIZZLE_X */
797 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
803 /* texture format translate */
804 uint32_t r600_translate_texformat(enum pipe_format format
,
805 const unsigned char *swizzle_view
,
806 uint32_t *word4_p
, uint32_t *yuv_format_p
)
808 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
809 const struct util_format_description
*desc
;
810 boolean uniform
= TRUE
;
812 const uint32_t sign_bit
[4] = {
813 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
814 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
815 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
816 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
818 desc
= util_format_description(format
);
820 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
822 /* Colorspace (return non-RGB formats directly). */
823 switch (desc
->colorspace
) {
824 /* Depth stencil formats */
825 case UTIL_FORMAT_COLORSPACE_ZS
:
827 case PIPE_FORMAT_Z16_UNORM
:
830 case PIPE_FORMAT_X24S8_USCALED
:
831 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
832 case PIPE_FORMAT_Z24X8_UNORM
:
833 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
836 case PIPE_FORMAT_S8X24_USCALED
:
837 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
838 case PIPE_FORMAT_X8Z24_UNORM
:
839 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
842 case PIPE_FORMAT_S8_USCALED
:
844 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
850 case UTIL_FORMAT_COLORSPACE_YUV
:
851 yuv_format
|= (1 << 30);
853 case PIPE_FORMAT_UYVY
:
854 case PIPE_FORMAT_YUYV
:
858 goto out_unknown
; /* TODO */
860 case UTIL_FORMAT_COLORSPACE_SRGB
:
861 word4
|= S_038010_FORCE_DEGAMMA(1);
862 if (format
== PIPE_FORMAT_L8A8_SRGB
|| format
== PIPE_FORMAT_L8_SRGB
)
863 goto out_unknown
; /* fails for some reason - TODO */
870 /* S3TC formats. TODO */
871 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
872 static int r600_enable_s3tc
= -1;
874 if (r600_enable_s3tc
== -1)
876 debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
878 if (!r600_enable_s3tc
)
881 if (!util_format_s3tc_enabled
) {
886 case PIPE_FORMAT_DXT1_RGB
:
887 case PIPE_FORMAT_DXT1_RGBA
:
888 case PIPE_FORMAT_DXT1_SRGB
:
889 case PIPE_FORMAT_DXT1_SRGBA
:
892 case PIPE_FORMAT_DXT3_RGBA
:
893 case PIPE_FORMAT_DXT3_SRGBA
:
896 case PIPE_FORMAT_DXT5_RGBA
:
897 case PIPE_FORMAT_DXT5_SRGBA
:
906 for (i
= 0; i
< desc
->nr_channels
; i
++) {
907 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
908 word4
|= sign_bit
[i
];
912 /* R8G8Bx_SNORM - TODO CxV8U8 */
916 /* See whether the components are of the same size. */
917 for (i
= 1; i
< desc
->nr_channels
; i
++) {
918 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
921 /* Non-uniform formats. */
923 switch(desc
->nr_channels
) {
925 if (desc
->channel
[0].size
== 5 &&
926 desc
->channel
[1].size
== 6 &&
927 desc
->channel
[2].size
== 5) {
933 if (desc
->channel
[0].size
== 5 &&
934 desc
->channel
[1].size
== 5 &&
935 desc
->channel
[2].size
== 5 &&
936 desc
->channel
[3].size
== 1) {
937 result
= FMT_1_5_5_5
;
940 if (desc
->channel
[0].size
== 10 &&
941 desc
->channel
[1].size
== 10 &&
942 desc
->channel
[2].size
== 10 &&
943 desc
->channel
[3].size
== 2) {
944 result
= FMT_2_10_10_10
;
952 /* Find the first non-VOID channel. */
953 for (i
= 0; i
< 4; i
++) {
954 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
962 /* uniform formats */
963 switch (desc
->channel
[i
].type
) {
964 case UTIL_FORMAT_TYPE_UNSIGNED
:
965 case UTIL_FORMAT_TYPE_SIGNED
:
966 if (!desc
->channel
[i
].normalized
&&
967 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
971 switch (desc
->channel
[i
].size
) {
973 switch (desc
->nr_channels
) {
978 result
= FMT_4_4_4_4
;
983 switch (desc
->nr_channels
) {
991 result
= FMT_8_8_8_8
;
996 switch (desc
->nr_channels
) {
1004 result
= FMT_16_16_16_16
;
1009 switch (desc
->nr_channels
) {
1017 result
= FMT_32_32_32_32
;
1023 case UTIL_FORMAT_TYPE_FLOAT
:
1024 switch (desc
->channel
[i
].size
) {
1026 switch (desc
->nr_channels
) {
1028 result
= FMT_16_FLOAT
;
1031 result
= FMT_16_16_FLOAT
;
1034 result
= FMT_16_16_16_16_FLOAT
;
1039 switch (desc
->nr_channels
) {
1041 result
= FMT_32_FLOAT
;
1044 result
= FMT_32_32_FLOAT
;
1047 result
= FMT_32_32_32_32_FLOAT
;
1057 *yuv_format_p
= yuv_format
;
1060 // R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));