2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_formats.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
35 /* Copy from a full GPU texture to a transfer's staging one. */
36 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
38 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
39 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
40 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
41 struct pipe_resource
*src
= transfer
->resource
;
43 if (src
->nr_samples
<= 1) {
44 if (!rctx
->screen
->dma_blit(ctx
, dst
, 0, 0, 0, 0,
47 /* async dma could not be use */
48 ctx
->resource_copy_region(ctx
, dst
, 0, 0, 0, 0,
49 src
, transfer
->level
, &transfer
->box
);
52 /* Resolve the resource. */
53 struct pipe_blit_info blit
;
55 memset(&blit
, 0, sizeof(blit
));
56 blit
.src
.resource
= src
;
57 blit
.src
.format
= src
->format
;
58 blit
.src
.level
= transfer
->level
;
59 blit
.src
.box
= transfer
->box
;
60 blit
.dst
.resource
= dst
;
61 blit
.dst
.format
= dst
->format
;
62 blit
.dst
.box
.width
= transfer
->box
.width
;
63 blit
.dst
.box
.height
= transfer
->box
.height
;
64 blit
.dst
.box
.depth
= transfer
->box
.depth
;
65 blit
.mask
= PIPE_MASK_RGBA
;
66 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
68 ctx
->blit(ctx
, &blit
);
72 /* Copy from a transfer's staging texture to a full GPU one. */
73 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
75 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
76 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
77 struct pipe_resource
*texture
= transfer
->resource
;
80 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
82 if (!rctx
->screen
->dma_blit(ctx
, texture
, transfer
->level
,
83 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
84 &rtransfer
->staging
->b
.b
, 0, &sbox
)) {
85 /* async dma could not be use */
86 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
87 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
88 &rtransfer
->staging
->b
.b
,
93 unsigned r600_texture_get_offset(struct r600_texture
*rtex
,
94 unsigned level
, unsigned layer
)
96 return rtex
->surface
.level
[level
].offset
+
97 layer
* rtex
->surface
.level
[level
].slice_size
;
100 static int r600_init_surface(struct r600_screen
*rscreen
,
101 struct radeon_surface
*surface
,
102 const struct pipe_resource
*ptex
,
104 bool is_flushed_depth
)
106 const struct util_format_description
*desc
=
107 util_format_description(ptex
->format
);
108 bool is_depth
, is_stencil
;
110 is_depth
= util_format_has_depth(desc
);
111 is_stencil
= util_format_has_stencil(desc
);
113 surface
->npix_x
= ptex
->width0
;
114 surface
->npix_y
= ptex
->height0
;
115 surface
->npix_z
= ptex
->depth0
;
116 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
117 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
119 surface
->array_size
= 1;
120 surface
->last_level
= ptex
->last_level
;
122 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
123 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
124 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
126 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
127 /* align byte per element on dword */
128 if (surface
->bpe
== 3) {
133 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
136 switch (array_mode
) {
137 case V_038000_ARRAY_1D_TILED_THIN1
:
138 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
140 case V_038000_ARRAY_2D_TILED_THIN1
:
141 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
143 case V_038000_ARRAY_LINEAR_ALIGNED
:
144 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
146 case V_038000_ARRAY_LINEAR_GENERAL
:
148 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR
, MODE
);
151 switch (ptex
->target
) {
152 case PIPE_TEXTURE_1D
:
153 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
155 case PIPE_TEXTURE_RECT
:
156 case PIPE_TEXTURE_2D
:
157 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
159 case PIPE_TEXTURE_3D
:
160 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
162 case PIPE_TEXTURE_1D_ARRAY
:
163 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
164 surface
->array_size
= ptex
->array_size
;
166 case PIPE_TEXTURE_2D_ARRAY
:
167 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d layout for now */
168 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
169 surface
->array_size
= ptex
->array_size
;
171 case PIPE_TEXTURE_CUBE
:
172 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
178 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
179 surface
->flags
|= RADEON_SURF_SCANOUT
;
182 if (!is_flushed_depth
&& is_depth
) {
183 surface
->flags
|= RADEON_SURF_ZBUFFER
;
186 surface
->flags
|= RADEON_SURF_SBUFFER
|
187 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
193 static int r600_setup_surface(struct pipe_screen
*screen
,
194 struct r600_texture
*rtex
,
195 unsigned pitch_in_bytes_override
)
197 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
198 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
202 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
206 rtex
->size
= rtex
->surface
.bo_size
;
207 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
208 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
211 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
212 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
213 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
214 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
215 rtex
->surface
.stencil_offset
=
216 rtex
->surface
.stencil_level
[0].offset
= rtex
->surface
.level
[0].slice_size
;
219 for (i
= 0; i
<= ptex
->last_level
; i
++) {
220 switch (rtex
->surface
.level
[i
].mode
) {
221 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
222 rtex
->array_mode
[i
] = V_038000_ARRAY_LINEAR_ALIGNED
;
224 case RADEON_SURF_MODE_1D
:
225 rtex
->array_mode
[i
] = V_038000_ARRAY_1D_TILED_THIN1
;
227 case RADEON_SURF_MODE_2D
:
228 rtex
->array_mode
[i
] = V_038000_ARRAY_2D_TILED_THIN1
;
231 case RADEON_SURF_MODE_LINEAR
:
232 rtex
->array_mode
[i
] = 0;
239 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
240 struct pipe_resource
*ptex
,
241 struct winsys_handle
*whandle
)
243 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
244 struct r600_resource
*resource
= &rtex
->resource
;
245 struct radeon_surface
*surface
= &rtex
->surface
;
246 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
248 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
250 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
251 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
252 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
253 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
254 surface
->bankw
, surface
->bankh
,
256 surface
->stencil_tile_split
,
258 rtex
->surface
.level
[0].pitch_bytes
);
260 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
261 rtex
->surface
.level
[0].pitch_bytes
, whandle
);
264 static void r600_texture_destroy(struct pipe_screen
*screen
,
265 struct pipe_resource
*ptex
)
267 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
268 struct r600_resource
*resource
= &rtex
->resource
;
270 if (rtex
->flushed_depth_texture
)
271 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
273 pb_reference(&resource
->buf
, NULL
);
277 static const struct u_resource_vtbl r600_texture_vtbl
;
279 /* The number of samples can be specified independently of the texture. */
280 void r600_texture_get_fmask_info(struct r600_screen
*rscreen
,
281 struct r600_texture
*rtex
,
283 struct r600_fmask_info
*out
)
285 /* FMASK is allocated pretty much like an ordinary texture.
286 * Here we use bpe in the units of bits, not bytes. */
287 struct radeon_surface fmask
= rtex
->surface
;
289 switch (nr_samples
) {
291 /* This should be 8,1, but we should set nsamples > 1
292 * for the allocator to treat it as a multisample surface.
293 * Let's set 4,2 then. */
307 R600_ERR("Invalid sample count for FMASK allocation.\n");
311 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
312 if (rscreen
->chip_class
<= R700
) {
316 if (rscreen
->chip_class
>= EVERGREEN
) {
317 fmask
.bankh
= nr_samples
<= 4 ? 4 : 1;
320 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
321 R600_ERR("Got error in surface_init while allocating FMASK.\n");
324 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
326 out
->bank_height
= fmask
.bankh
;
327 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
328 out
->size
= (fmask
.bo_size
+ 7) / 8;
331 static void r600_texture_allocate_fmask(struct r600_screen
*rscreen
,
332 struct r600_texture
*rtex
)
334 struct r600_fmask_info fmask
;
336 r600_texture_get_fmask_info(rscreen
, rtex
,
337 rtex
->resource
.b
.b
.nr_samples
, &fmask
);
339 rtex
->fmask_bank_height
= fmask
.bank_height
;
340 rtex
->fmask_offset
= align(rtex
->size
, fmask
.alignment
);
341 rtex
->fmask_size
= fmask
.size
;
342 rtex
->size
= rtex
->fmask_offset
+ rtex
->fmask_size
;
344 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
345 fmask
.npix_x
, fmask
.npix_y
, fmask
.bpe
* fmask
.nsamples
, rtex
->fmask_size
);
349 void r600_texture_get_cmask_info(struct r600_screen
*rscreen
,
350 struct r600_texture
*rtex
,
351 struct r600_cmask_info
*out
)
353 unsigned cmask_tile_width
= 8;
354 unsigned cmask_tile_height
= 8;
355 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
356 unsigned element_bits
= 4;
357 unsigned cmask_cache_bits
= 1024;
358 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
359 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
361 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
362 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
363 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
364 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
365 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
367 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
368 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
370 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
371 unsigned slice_bytes
=
372 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
374 assert(macro_tile_width
% 128 == 0);
375 assert(macro_tile_height
% 128 == 0);
377 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
378 out
->alignment
= MAX2(256, base_align
);
379 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
382 static void r600_texture_allocate_cmask(struct r600_screen
*rscreen
,
383 struct r600_texture
*rtex
)
385 struct r600_cmask_info cmask
;
387 r600_texture_get_cmask_info(rscreen
, rtex
, &cmask
);
389 rtex
->cmask_slice_tile_max
= cmask
.slice_tile_max
;
390 rtex
->cmask_offset
= align(rtex
->size
, cmask
.alignment
);
391 rtex
->cmask_size
= cmask
.size
;
392 rtex
->size
= rtex
->cmask_offset
+ rtex
->cmask_size
;
394 printf("CMASK: macro tile width = %u, macro tile height = %u, "
395 "pitch elements = %u, height = %u, slice tile max = %u\n",
396 macro_tile_width
, macro_tile_height
, pitch_elements
, height
,
397 rtex
->cmask_slice_tile_max
);
401 DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth
, "R600_PRINT_TEXDEPTH", FALSE
);
403 static struct r600_texture
*
404 r600_texture_create_object(struct pipe_screen
*screen
,
405 const struct pipe_resource
*base
,
406 unsigned pitch_in_bytes_override
,
407 struct pb_buffer
*buf
,
408 struct radeon_surface
*surface
)
410 struct r600_texture
*rtex
;
411 struct r600_resource
*resource
;
412 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
415 rtex
= CALLOC_STRUCT(r600_texture
);
419 resource
= &rtex
->resource
;
420 resource
->b
.b
= *base
;
421 resource
->b
.vtbl
= &r600_texture_vtbl
;
422 pipe_reference_init(&resource
->b
.b
.reference
, 1);
423 resource
->b
.b
.screen
= screen
;
424 rtex
->pitch_override
= pitch_in_bytes_override
;
426 /* don't include stencil-only formats which we don't support for rendering */
427 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
429 rtex
->surface
= *surface
;
430 r
= r600_setup_surface(screen
, rtex
,
431 pitch_in_bytes_override
);
437 if (base
->nr_samples
> 1 && !rtex
->is_depth
&& !buf
) {
438 r600_texture_allocate_cmask(rscreen
, rtex
);
439 r600_texture_allocate_fmask(rscreen
, rtex
);
442 if (!rtex
->is_depth
&& base
->nr_samples
> 1 &&
443 (!rtex
->fmask_size
|| !rtex
->cmask_size
)) {
448 /* Tiled depth textures utilize the non-displayable tile order. */
449 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
451 /* only enable hyperz for PIPE_TEXTURE_2D not for PIPE_TEXTURE_2D_ARRAY
452 * Thought it might still be interessting to use hyperz for texture
453 * array without using fast clear features
456 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) &&
457 util_format_is_depth_or_stencil(base
->format
) &&
458 rscreen
->use_hyperz
&&
459 base
->target
== PIPE_TEXTURE_2D
&&
460 rtex
->surface
.level
[0].nblk_x
>= 32 &&
461 rtex
->surface
.level
[0].nblk_y
>= 32) {
462 unsigned sw
= rtex
->surface
.level
[0].nblk_x
* rtex
->surface
.blk_w
;
463 unsigned sh
= rtex
->surface
.level
[0].nblk_y
* rtex
->surface
.blk_h
;
465 unsigned npipes
= rscreen
->info
.r600_num_tile_pipes
;
467 /* this alignment and htile size only apply to linear htile buffer */
468 sw
= align(sw
, 16 << 3);
469 sh
= align(sh
, npipes
<< 3);
470 htile_size
= (sw
>> 3) * (sh
>> 3) * 4;
471 /* must be aligned with 2K * npipes */
472 htile_size
= align(htile_size
, (2 << 10) * npipes
);
474 rtex
->htile
= (struct r600_resource
*)pipe_buffer_create(&rscreen
->screen
, PIPE_BIND_CUSTOM
,
475 PIPE_USAGE_STATIC
, htile_size
);
476 if (rtex
->htile
== NULL
) {
477 /* this is not a fatal error as we can still keep rendering
478 * without htile buffer
480 R600_ERR("r600: failed to create bo for htile buffers\n");
483 ptr
= rscreen
->ws
->buffer_map(rtex
->htile
->cs_buf
, NULL
, PIPE_TRANSFER_WRITE
);
484 memset(ptr
, 0x0, htile_size
);
485 rscreen
->ws
->buffer_unmap(rtex
->htile
->cs_buf
);
489 /* Now create the backing buffer. */
491 unsigned base_align
= rtex
->surface
.bo_alignment
;
492 unsigned usage
= R600_TEX_IS_TILED(rtex
, 0) ? PIPE_USAGE_STATIC
: base
->usage
;
494 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, FALSE
, usage
)) {
499 /* This is usually the window framebuffer. We want it in VRAM, always. */
501 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
502 resource
->domains
= RADEON_DOMAIN_VRAM
;
505 if (rtex
->cmask_size
) {
506 /* Initialize the cmask to 0xCC (= compressed state). */
507 char *ptr
= rscreen
->ws
->buffer_map(resource
->cs_buf
, NULL
, PIPE_TRANSFER_WRITE
);
508 memset(ptr
+ rtex
->cmask_offset
, 0xCC, rtex
->cmask_size
);
509 rscreen
->ws
->buffer_unmap(resource
->cs_buf
);
512 if (debug_get_option_print_texdepth() && rtex
->is_depth
&& rtex
->non_disp_tiling
) {
513 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
514 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
515 "bpe=%u, nsamples=%u, flags=%u\n",
516 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
517 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
518 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
519 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
520 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
521 rtex
->surface
.flags
);
522 if (rtex
->surface
.flags
& RADEON_SURF_ZBUFFER
) {
523 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
524 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
525 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
526 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
527 i
, (unsigned long long)rtex
->surface
.level
[i
].offset
,
528 (unsigned long long)rtex
->surface
.level
[i
].slice_size
,
529 u_minify(rtex
->resource
.b
.b
.width0
, i
),
530 u_minify(rtex
->resource
.b
.b
.height0
, i
),
531 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
532 rtex
->surface
.level
[i
].nblk_x
,
533 rtex
->surface
.level
[i
].nblk_y
,
534 rtex
->surface
.level
[i
].nblk_z
,
535 rtex
->surface
.level
[i
].pitch_bytes
,
536 rtex
->surface
.level
[i
].mode
);
539 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
540 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
541 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
542 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
543 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
544 i
, (unsigned long long)rtex
->surface
.stencil_level
[i
].offset
,
545 (unsigned long long)rtex
->surface
.stencil_level
[i
].slice_size
,
546 u_minify(rtex
->resource
.b
.b
.width0
, i
),
547 u_minify(rtex
->resource
.b
.b
.height0
, i
),
548 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
549 rtex
->surface
.stencil_level
[i
].nblk_x
,
550 rtex
->surface
.stencil_level
[i
].nblk_y
,
551 rtex
->surface
.stencil_level
[i
].nblk_z
,
552 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
553 rtex
->surface
.stencil_level
[i
].mode
);
560 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
561 const struct pipe_resource
*templ
)
563 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
564 struct radeon_surface surface
;
565 const struct util_format_description
*desc
= util_format_description(templ
->format
);
569 /* Default tiling mode for staging textures. */
570 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
572 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
573 * because 422 formats are used for videos, which prefer linear buffers
574 * for fast uploads anyway. */
575 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
576 desc
->layout
!= UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
577 if (templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
) {
578 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
579 } else if (!(templ
->bind
& PIPE_BIND_SCANOUT
) &&
580 templ
->usage
!= PIPE_USAGE_STAGING
&&
581 templ
->usage
!= PIPE_USAGE_STREAM
&&
582 templ
->target
!= PIPE_TEXTURE_1D
&&
583 templ
->target
!= PIPE_TEXTURE_1D_ARRAY
&&
584 templ
->height0
> 3) {
585 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
586 } else if (util_format_is_compressed(templ
->format
)) {
587 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
591 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
,
592 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
596 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
600 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
604 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
605 struct pipe_resource
*texture
,
606 const struct pipe_surface
*templ
,
607 unsigned width
, unsigned height
)
609 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
611 assert(templ
->u
.tex
.first_layer
<= u_max_layer(texture
, templ
->u
.tex
.level
));
612 assert(templ
->u
.tex
.last_layer
<= u_max_layer(texture
, templ
->u
.tex
.level
));
613 assert(templ
->u
.tex
.first_layer
== templ
->u
.tex
.last_layer
);
616 pipe_reference_init(&surface
->base
.reference
, 1);
617 pipe_resource_reference(&surface
->base
.texture
, texture
);
618 surface
->base
.context
= pipe
;
619 surface
->base
.format
= templ
->format
;
620 surface
->base
.width
= width
;
621 surface
->base
.height
= height
;
622 surface
->base
.u
= templ
->u
;
623 return &surface
->base
;
626 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
627 struct pipe_resource
*tex
,
628 const struct pipe_surface
*templ
)
630 unsigned level
= templ
->u
.tex
.level
;
632 return r600_create_surface_custom(pipe
, tex
, templ
,
633 u_minify(tex
->width0
, level
),
634 u_minify(tex
->height0
, level
));
637 static void r600_surface_destroy(struct pipe_context
*pipe
,
638 struct pipe_surface
*surface
)
640 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
641 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
, NULL
);
642 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
, NULL
);
643 pipe_resource_reference(&surface
->texture
, NULL
);
647 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
648 const struct pipe_resource
*templ
,
649 struct winsys_handle
*whandle
)
651 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
652 struct pb_buffer
*buf
= NULL
;
654 unsigned array_mode
= 0;
655 enum radeon_bo_layout micro
, macro
;
656 struct radeon_surface surface
;
659 /* Support only 2D textures without mipmaps */
660 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
661 templ
->depth0
!= 1 || templ
->last_level
!= 0)
664 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
668 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
669 &surface
.bankw
, &surface
.bankh
,
671 &surface
.stencil_tile_split
,
674 if (macro
== RADEON_LAYOUT_TILED
)
675 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
676 else if (micro
== RADEON_LAYOUT_TILED
)
677 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
679 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
681 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
685 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
686 stride
, buf
, &surface
);
689 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
690 struct pipe_resource
*texture
,
691 struct r600_texture
**staging
)
693 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
694 struct pipe_resource resource
;
695 struct r600_texture
**flushed_depth_texture
= staging
?
696 staging
: &rtex
->flushed_depth_texture
;
698 if (!staging
&& rtex
->flushed_depth_texture
)
699 return true; /* it's ready */
701 resource
.target
= texture
->target
;
702 resource
.format
= texture
->format
;
703 resource
.width0
= texture
->width0
;
704 resource
.height0
= texture
->height0
;
705 resource
.depth0
= texture
->depth0
;
706 resource
.array_size
= texture
->array_size
;
707 resource
.last_level
= texture
->last_level
;
708 resource
.nr_samples
= texture
->nr_samples
;
709 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_STATIC
;
710 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
711 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
714 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
716 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
717 if (*flushed_depth_texture
== NULL
) {
718 R600_ERR("failed to create temporary texture to hold flushed depth\n");
722 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
723 (*flushed_depth_texture
)->non_disp_tiling
= false;
727 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
728 struct pipe_resource
*texture
,
731 const struct pipe_box
*box
,
732 struct pipe_transfer
**ptransfer
)
734 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
735 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
736 struct r600_transfer
*trans
;
737 boolean use_staging_texture
= FALSE
;
738 enum pipe_format format
= texture
->format
;
739 struct r600_resource
*buf
;
743 if ((texture
->bind
& PIPE_BIND_GLOBAL
) && texture
->target
== PIPE_BUFFER
) {
744 return r600_compute_global_transfer_map(ctx
, texture
, level
, usage
, box
, ptransfer
);
747 /* We cannot map a tiled texture directly because the data is
748 * in a different order, therefore we do detiling using a blit.
750 * Also, use a temporary in GTT memory for read transfers, as
751 * the CPU is much happier reading out of cached system memory
752 * than uncached VRAM.
754 if (R600_TEX_IS_TILED(rtex
, level
)) {
755 use_staging_texture
= TRUE
;
758 /* Use a staging texture for uploads if the underlying BO is busy. */
759 if (!(usage
& PIPE_TRANSFER_READ
) &&
760 (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
761 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
))) {
762 use_staging_texture
= TRUE
;
765 if (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
) {
766 use_staging_texture
= FALSE
;
769 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
773 trans
= CALLOC_STRUCT(r600_transfer
);
776 trans
->transfer
.resource
= texture
;
777 trans
->transfer
.level
= level
;
778 trans
->transfer
.usage
= usage
;
779 trans
->transfer
.box
= *box
;
780 if (rtex
->is_depth
) {
781 /* XXX: only readback the rectangle which is being mapped?
783 /* XXX: when discard is true, no need to read back from depth texture
785 struct r600_texture
*staging_depth
;
787 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
788 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
789 R600_ERR("mapping MSAA zbuffer unimplemented\n");
794 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
795 R600_ERR("failed to create temporary texture to hold untiled copy\n");
800 r600_blit_decompress_depth(ctx
, rtex
, staging_depth
,
802 box
->z
, box
->z
+ box
->depth
- 1,
805 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
806 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
807 trans
->offset
= r600_texture_get_offset(staging_depth
, level
, box
->z
);
808 trans
->staging
= (struct r600_resource
*)staging_depth
;
809 } else if (use_staging_texture
) {
810 struct pipe_resource resource
;
811 struct r600_texture
*staging
;
813 memset(&resource
, 0, sizeof(resource
));
814 resource
.format
= texture
->format
;
815 resource
.width0
= box
->width
;
816 resource
.height0
= box
->height
;
818 resource
.array_size
= 1;
819 resource
.usage
= PIPE_USAGE_STAGING
;
820 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
822 /* We must set the correct texture target and dimensions if needed for a 3D transfer. */
823 if (box
->depth
> 1 && u_max_layer(texture
, level
) > 0)
824 resource
.target
= texture
->target
;
826 resource
.target
= PIPE_TEXTURE_2D
;
828 switch (resource
.target
) {
829 case PIPE_TEXTURE_1D_ARRAY
:
830 case PIPE_TEXTURE_2D_ARRAY
:
831 case PIPE_TEXTURE_CUBE_ARRAY
:
832 resource
.array_size
= box
->depth
;
834 case PIPE_TEXTURE_3D
:
835 resource
.depth0
= box
->depth
;
841 /* Create the temporary texture. */
842 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
843 if (staging
== NULL
) {
844 R600_ERR("failed to create temporary texture to hold untiled copy\n");
848 trans
->staging
= &staging
->resource
;
849 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
850 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
851 if (usage
& PIPE_TRANSFER_READ
) {
852 r600_copy_to_staging_texture(ctx
, trans
);
853 /* flush gfx & dma ring, order does not matter as only one can be live */
854 rctx
->rings
.dma
.flush(rctx
, 0);
855 rctx
->rings
.gfx
.flush(rctx
, 0);
858 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
859 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
860 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
863 if (trans
->staging
) {
864 buf
= trans
->staging
;
866 buf
= &rtex
->resource
;
869 if (rtex
->is_depth
|| !trans
->staging
)
870 offset
= trans
->offset
+
871 box
->y
/ util_format_get_blockheight(format
) * trans
->transfer
.stride
+
872 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
874 if (!(map
= r600_buffer_mmap_sync_with_rings(rctx
, buf
, usage
))) {
875 pipe_resource_reference((struct pipe_resource
**)&trans
->staging
, NULL
);
880 *ptransfer
= &trans
->transfer
;
884 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
885 struct pipe_transfer
* transfer
)
887 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
888 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
889 struct radeon_winsys_cs_handle
*buf
;
890 struct pipe_resource
*texture
= transfer
->resource
;
891 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
893 if ((transfer
->resource
->bind
& PIPE_BIND_GLOBAL
) && transfer
->resource
->target
== PIPE_BUFFER
) {
894 return r600_compute_global_transfer_unmap(ctx
, transfer
);
897 if (rtransfer
->staging
) {
898 buf
= ((struct r600_resource
*)rtransfer
->staging
)->cs_buf
;
900 buf
= ((struct r600_resource
*)transfer
->resource
)->cs_buf
;
902 rctx
->ws
->buffer_unmap(buf
);
904 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
905 if (rtex
->is_depth
) {
906 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
907 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
908 &rtransfer
->staging
->b
.b
, transfer
->level
,
911 r600_copy_from_staging_texture(ctx
, rtransfer
);
915 if (rtransfer
->staging
)
916 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
921 void r600_init_surface_functions(struct r600_context
*r600
)
923 r600
->context
.create_surface
= r600_create_surface
;
924 r600
->context
.surface_destroy
= r600_surface_destroy
;
927 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
928 const unsigned char *swizzle_view
,
932 unsigned char swizzle
[4];
934 const uint32_t tex_swizzle_shift
[4] = {
937 const uint32_t vtx_swizzle_shift
[4] = {
940 const uint32_t swizzle_bit
[4] = {
943 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
946 swizzle_shift
= vtx_swizzle_shift
;
949 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
951 memcpy(swizzle
, swizzle_format
, 4);
955 for (i
= 0; i
< 4; i
++) {
956 switch (swizzle
[i
]) {
957 case UTIL_FORMAT_SWIZZLE_Y
:
958 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
960 case UTIL_FORMAT_SWIZZLE_Z
:
961 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
963 case UTIL_FORMAT_SWIZZLE_W
:
964 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
966 case UTIL_FORMAT_SWIZZLE_0
:
967 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
969 case UTIL_FORMAT_SWIZZLE_1
:
970 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
972 default: /* UTIL_FORMAT_SWIZZLE_X */
973 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
979 /* texture format translate */
980 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
981 enum pipe_format format
,
982 const unsigned char *swizzle_view
,
983 uint32_t *word4_p
, uint32_t *yuv_format_p
)
985 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
986 const struct util_format_description
*desc
;
987 boolean uniform
= TRUE
;
988 static int r600_enable_s3tc
= -1;
989 bool is_srgb_valid
= FALSE
;
992 const uint32_t sign_bit
[4] = {
993 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
994 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
995 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
996 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
998 desc
= util_format_description(format
);
1000 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
1002 /* Colorspace (return non-RGB formats directly). */
1003 switch (desc
->colorspace
) {
1004 /* Depth stencil formats */
1005 case UTIL_FORMAT_COLORSPACE_ZS
:
1007 case PIPE_FORMAT_Z16_UNORM
:
1010 case PIPE_FORMAT_X24S8_UINT
:
1011 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1012 case PIPE_FORMAT_Z24X8_UNORM
:
1013 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1016 case PIPE_FORMAT_S8X24_UINT
:
1017 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1018 case PIPE_FORMAT_X8Z24_UNORM
:
1019 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1022 case PIPE_FORMAT_S8_UINT
:
1024 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1026 case PIPE_FORMAT_Z32_FLOAT
:
1027 result
= FMT_32_FLOAT
;
1029 case PIPE_FORMAT_X32_S8X24_UINT
:
1030 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1031 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1032 result
= FMT_X24_8_32_FLOAT
;
1038 case UTIL_FORMAT_COLORSPACE_YUV
:
1039 yuv_format
|= (1 << 30);
1041 case PIPE_FORMAT_UYVY
:
1042 case PIPE_FORMAT_YUYV
:
1046 goto out_unknown
; /* XXX */
1048 case UTIL_FORMAT_COLORSPACE_SRGB
:
1049 word4
|= S_038010_FORCE_DEGAMMA(1);
1056 if (r600_enable_s3tc
== -1) {
1057 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1058 if (rscreen
->info
.drm_minor
>= 9)
1059 r600_enable_s3tc
= 1;
1061 r600_enable_s3tc
= debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
1064 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1065 if (!r600_enable_s3tc
)
1069 case PIPE_FORMAT_RGTC1_SNORM
:
1070 case PIPE_FORMAT_LATC1_SNORM
:
1071 word4
|= sign_bit
[0];
1072 case PIPE_FORMAT_RGTC1_UNORM
:
1073 case PIPE_FORMAT_LATC1_UNORM
:
1076 case PIPE_FORMAT_RGTC2_SNORM
:
1077 case PIPE_FORMAT_LATC2_SNORM
:
1078 word4
|= sign_bit
[0] | sign_bit
[1];
1079 case PIPE_FORMAT_RGTC2_UNORM
:
1080 case PIPE_FORMAT_LATC2_UNORM
:
1088 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1090 if (!r600_enable_s3tc
)
1093 if (!util_format_s3tc_enabled
) {
1098 case PIPE_FORMAT_DXT1_RGB
:
1099 case PIPE_FORMAT_DXT1_RGBA
:
1100 case PIPE_FORMAT_DXT1_SRGB
:
1101 case PIPE_FORMAT_DXT1_SRGBA
:
1103 is_srgb_valid
= TRUE
;
1105 case PIPE_FORMAT_DXT3_RGBA
:
1106 case PIPE_FORMAT_DXT3_SRGBA
:
1108 is_srgb_valid
= TRUE
;
1110 case PIPE_FORMAT_DXT5_RGBA
:
1111 case PIPE_FORMAT_DXT5_SRGBA
:
1113 is_srgb_valid
= TRUE
;
1120 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1122 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1123 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1126 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1127 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1135 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1136 result
= FMT_5_9_9_9_SHAREDEXP
;
1138 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1139 result
= FMT_10_11_11_FLOAT
;
1144 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1145 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1146 word4
|= sign_bit
[i
];
1150 /* R8G8Bx_SNORM - XXX CxV8U8 */
1152 /* See whether the components are of the same size. */
1153 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1154 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1157 /* Non-uniform formats. */
1159 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1160 desc
->channel
[0].pure_integer
)
1161 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1162 switch(desc
->nr_channels
) {
1164 if (desc
->channel
[0].size
== 5 &&
1165 desc
->channel
[1].size
== 6 &&
1166 desc
->channel
[2].size
== 5) {
1172 if (desc
->channel
[0].size
== 5 &&
1173 desc
->channel
[1].size
== 5 &&
1174 desc
->channel
[2].size
== 5 &&
1175 desc
->channel
[3].size
== 1) {
1176 result
= FMT_1_5_5_5
;
1179 if (desc
->channel
[0].size
== 10 &&
1180 desc
->channel
[1].size
== 10 &&
1181 desc
->channel
[2].size
== 10 &&
1182 desc
->channel
[3].size
== 2) {
1183 result
= FMT_2_10_10_10
;
1191 /* Find the first non-VOID channel. */
1192 for (i
= 0; i
< 4; i
++) {
1193 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1201 /* uniform formats */
1202 switch (desc
->channel
[i
].type
) {
1203 case UTIL_FORMAT_TYPE_UNSIGNED
:
1204 case UTIL_FORMAT_TYPE_SIGNED
:
1206 if (!desc
->channel
[i
].normalized
&&
1207 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
1211 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1212 desc
->channel
[i
].pure_integer
)
1213 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1215 switch (desc
->channel
[i
].size
) {
1217 switch (desc
->nr_channels
) {
1222 result
= FMT_4_4_4_4
;
1227 switch (desc
->nr_channels
) {
1235 result
= FMT_8_8_8_8
;
1236 is_srgb_valid
= TRUE
;
1241 switch (desc
->nr_channels
) {
1249 result
= FMT_16_16_16_16
;
1254 switch (desc
->nr_channels
) {
1262 result
= FMT_32_32_32_32
;
1268 case UTIL_FORMAT_TYPE_FLOAT
:
1269 switch (desc
->channel
[i
].size
) {
1271 switch (desc
->nr_channels
) {
1273 result
= FMT_16_FLOAT
;
1276 result
= FMT_16_16_FLOAT
;
1279 result
= FMT_16_16_16_16_FLOAT
;
1284 switch (desc
->nr_channels
) {
1286 result
= FMT_32_FLOAT
;
1289 result
= FMT_32_32_FLOAT
;
1292 result
= FMT_32_32_32_32_FLOAT
;
1301 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
1306 *yuv_format_p
= yuv_format
;
1309 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1313 static const struct u_resource_vtbl r600_texture_vtbl
=
1315 r600_texture_get_handle
, /* get_handle */
1316 r600_texture_destroy
, /* resource_destroy */
1317 r600_texture_transfer_map
, /* transfer_map */
1318 NULL
, /* transfer_flush_region */
1319 r600_texture_transfer_unmap
, /* transfer_unmap */
1320 NULL
/* transfer_inline_write */