2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "pipe/p_screen.h"
29 #include "util/u_format.h"
30 #include "util/u_format_s3tc.h"
31 #include "util/u_math.h"
32 #include "util/u_inlines.h"
33 #include "util/u_memory.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
38 #include "r600_formats.h"
40 /* Copy from a full GPU texture to a transfer's staging one. */
41 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
43 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
44 struct pipe_resource
*texture
= transfer
->resource
;
46 ctx
->resource_copy_region(ctx
, &rtransfer
->staging
->b
.b
.b
,
47 0, 0, 0, 0, texture
, transfer
->level
,
52 /* Copy from a transfer's staging texture to a full GPU one. */
53 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
55 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
56 struct pipe_resource
*texture
= transfer
->resource
;
59 sbox
.x
= sbox
.y
= sbox
.z
= 0;
60 sbox
.width
= transfer
->box
.width
;
61 sbox
.height
= transfer
->box
.height
;
62 /* XXX that might be wrong */
64 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
65 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
66 &rtransfer
->staging
->b
.b
.b
,
70 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
71 unsigned level
, unsigned layer
)
73 unsigned offset
= rtex
->offset
[level
];
75 switch (rtex
->resource
.b
.b
.b
.target
) {
77 case PIPE_TEXTURE_CUBE
:
79 return offset
+ layer
* rtex
->layer_size
[level
];
83 static unsigned r600_get_block_alignment(struct pipe_screen
*screen
,
84 enum pipe_format format
,
87 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
88 unsigned pixsize
= util_format_get_blocksize(format
);
92 case V_038000_ARRAY_1D_TILED_THIN1
:
94 ((rscreen
->tiling_info
.group_bytes
/ 8 / pixsize
)));
96 case V_038000_ARRAY_2D_TILED_THIN1
:
97 p_align
= MAX2(rscreen
->tiling_info
.num_banks
,
98 (((rscreen
->tiling_info
.group_bytes
/ 8 / pixsize
)) *
99 rscreen
->tiling_info
.num_banks
)) * 8;
101 case V_038000_ARRAY_LINEAR_ALIGNED
:
102 p_align
= MAX2(64, rscreen
->tiling_info
.group_bytes
/ pixsize
);
104 case V_038000_ARRAY_LINEAR_GENERAL
:
106 p_align
= rscreen
->tiling_info
.group_bytes
/ pixsize
;
112 static unsigned r600_get_height_alignment(struct pipe_screen
*screen
,
115 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
118 switch (array_mode
) {
119 case V_038000_ARRAY_2D_TILED_THIN1
:
120 h_align
= rscreen
->tiling_info
.num_channels
* 8;
122 case V_038000_ARRAY_1D_TILED_THIN1
:
123 case V_038000_ARRAY_LINEAR_ALIGNED
:
126 case V_038000_ARRAY_LINEAR_GENERAL
:
134 static unsigned r600_get_base_alignment(struct pipe_screen
*screen
,
135 enum pipe_format format
,
138 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
139 unsigned pixsize
= util_format_get_blocksize(format
);
140 int p_align
= r600_get_block_alignment(screen
, format
, array_mode
);
141 int h_align
= r600_get_height_alignment(screen
, array_mode
);
144 switch (array_mode
) {
145 case V_038000_ARRAY_2D_TILED_THIN1
:
146 b_align
= MAX2(rscreen
->tiling_info
.num_banks
* rscreen
->tiling_info
.num_channels
* 8 * 8 * pixsize
,
147 p_align
* pixsize
* h_align
);
149 case V_038000_ARRAY_1D_TILED_THIN1
:
150 case V_038000_ARRAY_LINEAR_ALIGNED
:
151 case V_038000_ARRAY_LINEAR_GENERAL
:
153 b_align
= rscreen
->tiling_info
.group_bytes
;
159 static unsigned mip_minify(unsigned size
, unsigned level
)
162 val
= u_minify(size
, level
);
164 val
= util_next_power_of_two(val
);
168 static unsigned r600_texture_get_nblocksx(struct pipe_screen
*screen
,
169 struct r600_resource_texture
*rtex
,
172 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
173 unsigned nblocksx
, block_align
, width
;
174 unsigned blocksize
= util_format_get_blocksize(rtex
->real_format
);
176 if (rtex
->pitch_override
)
177 return rtex
->pitch_override
/ blocksize
;
179 width
= mip_minify(ptex
->width0
, level
);
180 nblocksx
= util_format_get_nblocksx(rtex
->real_format
, width
);
182 block_align
= r600_get_block_alignment(screen
, rtex
->real_format
,
183 rtex
->array_mode
[level
]);
184 nblocksx
= align(nblocksx
, block_align
);
188 static unsigned r600_texture_get_nblocksy(struct pipe_screen
*screen
,
189 struct r600_resource_texture
*rtex
,
192 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
193 unsigned height
, tile_height
;
195 height
= mip_minify(ptex
->height0
, level
);
196 height
= util_format_get_nblocksy(rtex
->real_format
, height
);
197 tile_height
= r600_get_height_alignment(screen
,
198 rtex
->array_mode
[level
]);
200 /* XXX Hack around an alignment issue. Less tests fail with this.
202 * The thing is depth-stencil buffers should be tiled, i.e.
203 * the alignment should be >=8. If I make them tiled, stencil starts
204 * working because it no longer overlaps with the depth buffer
205 * in memory, but texturing like drawpix-stencil breaks. */
206 if (util_format_is_depth_or_stencil(rtex
->real_format
) && tile_height
< 8)
209 height
= align(height
, tile_height
);
213 static void r600_texture_set_array_mode(struct pipe_screen
*screen
,
214 struct r600_resource_texture
*rtex
,
215 unsigned level
, unsigned array_mode
)
217 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
219 switch (array_mode
) {
220 case V_0280A0_ARRAY_LINEAR_GENERAL
:
221 case V_0280A0_ARRAY_LINEAR_ALIGNED
:
222 case V_0280A0_ARRAY_1D_TILED_THIN1
:
224 rtex
->array_mode
[level
] = array_mode
;
226 case V_0280A0_ARRAY_2D_TILED_THIN1
:
228 unsigned w
, h
, tile_height
, tile_width
;
230 tile_height
= r600_get_height_alignment(screen
, array_mode
);
231 tile_width
= r600_get_block_alignment(screen
, rtex
->real_format
, array_mode
);
233 w
= mip_minify(ptex
->width0
, level
);
234 h
= mip_minify(ptex
->height0
, level
);
235 if (w
<= tile_width
|| h
<= tile_height
)
236 rtex
->array_mode
[level
] = V_0280A0_ARRAY_1D_TILED_THIN1
;
238 rtex
->array_mode
[level
] = array_mode
;
244 static int r600_init_surface(struct radeon_surface
*surface
,
245 const struct pipe_resource
*ptex
,
248 surface
->npix_x
= ptex
->width0
;
249 surface
->npix_y
= ptex
->height0
;
250 surface
->npix_z
= ptex
->depth0
;
251 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
252 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
254 surface
->array_size
= 1;
255 surface
->last_level
= ptex
->last_level
;
256 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
257 /* align byte per element on dword */
258 if (surface
->bpe
== 3) {
261 surface
->nsamples
= 1;
263 switch (array_mode
) {
264 case V_038000_ARRAY_1D_TILED_THIN1
:
265 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
267 case V_038000_ARRAY_2D_TILED_THIN1
:
268 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
270 case V_038000_ARRAY_LINEAR_ALIGNED
:
271 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
273 case V_038000_ARRAY_LINEAR_GENERAL
:
275 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR
, MODE
);
278 switch (ptex
->target
) {
279 case PIPE_TEXTURE_1D
:
280 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
282 case PIPE_TEXTURE_RECT
:
283 case PIPE_TEXTURE_2D
:
284 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
286 case PIPE_TEXTURE_3D
:
287 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
289 case PIPE_TEXTURE_1D_ARRAY
:
290 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
291 surface
->array_size
= ptex
->array_size
;
293 case PIPE_TEXTURE_2D_ARRAY
:
294 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
295 surface
->array_size
= ptex
->array_size
;
297 case PIPE_TEXTURE_CUBE
:
298 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
304 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
305 surface
->flags
|= RADEON_SURF_SCANOUT
;
307 if (util_format_is_depth_and_stencil(ptex
->format
)) {
308 surface
->flags
|= RADEON_SURF_ZBUFFER
;
309 surface
->flags
|= RADEON_SURF_SBUFFER
;
315 static int r600_setup_surface(struct pipe_screen
*screen
,
316 struct r600_resource_texture
*rtex
,
318 unsigned pitch_in_bytes_override
)
320 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
321 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
325 if (util_format_is_depth_or_stencil(rtex
->real_format
)) {
326 rtex
->surface
.flags
|= RADEON_SURF_ZBUFFER
;
327 rtex
->surface
.flags
|= RADEON_SURF_SBUFFER
;
330 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
334 rtex
->size
= rtex
->surface
.bo_size
;
335 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
336 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
339 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
340 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
341 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
342 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
343 rtex
->surface
.stencil_offset
= rtex
->surface
.level
[0].slice_size
;
346 for (i
= 0; i
<= ptex
->last_level
; i
++) {
347 rtex
->offset
[i
] = rtex
->surface
.level
[i
].offset
;
348 rtex
->layer_size
[i
] = rtex
->surface
.level
[i
].slice_size
;
349 rtex
->pitch_in_bytes
[i
] = rtex
->surface
.level
[i
].pitch_bytes
;
350 switch (rtex
->surface
.level
[i
].mode
) {
351 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
352 rtex
->array_mode
[i
] = V_038000_ARRAY_LINEAR_ALIGNED
;
354 case RADEON_SURF_MODE_1D
:
355 rtex
->array_mode
[i
] = V_038000_ARRAY_1D_TILED_THIN1
;
357 case RADEON_SURF_MODE_2D
:
358 rtex
->array_mode
[i
] = V_038000_ARRAY_2D_TILED_THIN1
;
361 case RADEON_SURF_MODE_LINEAR
:
362 rtex
->array_mode
[i
] = 0;
369 static void r600_setup_miptree(struct pipe_screen
*screen
,
370 struct r600_resource_texture
*rtex
,
373 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
374 enum chip_class chipc
= ((struct r600_screen
*)screen
)->chip_class
;
375 unsigned size
, layer_size
, i
, offset
;
376 unsigned nblocksx
, nblocksy
;
378 for (i
= 0, offset
= 0; i
<= ptex
->last_level
; i
++) {
379 unsigned blocksize
= util_format_get_blocksize(rtex
->real_format
);
380 unsigned base_align
= r600_get_base_alignment(screen
, rtex
->real_format
, array_mode
);
382 r600_texture_set_array_mode(screen
, rtex
, i
, array_mode
);
384 nblocksx
= r600_texture_get_nblocksx(screen
, rtex
, i
);
385 nblocksy
= r600_texture_get_nblocksy(screen
, rtex
, i
);
387 if (chipc
>= EVERGREEN
&& array_mode
== V_038000_ARRAY_LINEAR_GENERAL
)
388 layer_size
= align(nblocksx
, 64) * nblocksy
* blocksize
;
390 layer_size
= nblocksx
* nblocksy
* blocksize
;
392 if (ptex
->target
== PIPE_TEXTURE_CUBE
) {
394 size
= layer_size
* 8;
396 size
= layer_size
* 6;
398 else if (ptex
->target
== PIPE_TEXTURE_3D
)
399 size
= layer_size
* u_minify(ptex
->depth0
, i
);
401 size
= layer_size
* ptex
->array_size
;
403 /* align base image and start of miptree */
404 if ((i
== 0) || (i
== 1))
405 offset
= align(offset
, base_align
);
406 rtex
->offset
[i
] = offset
;
407 rtex
->layer_size
[i
] = layer_size
;
408 rtex
->pitch_in_blocks
[i
] = nblocksx
; /* CB talks in elements */
409 rtex
->pitch_in_bytes
[i
] = nblocksx
* blocksize
;
416 /* Figure out whether u_blitter will fallback to a transfer operation.
417 * If so, don't use a staging resource.
419 static boolean
permit_hardware_blit(struct pipe_screen
*screen
,
420 const struct pipe_resource
*res
)
424 if (util_format_is_depth_or_stencil(res
->format
))
425 bind
= PIPE_BIND_DEPTH_STENCIL
;
427 bind
= PIPE_BIND_RENDER_TARGET
;
429 /* hackaround for S3TC */
430 if (util_format_is_compressed(res
->format
))
433 if (!screen
->is_format_supported(screen
,
440 if (!screen
->is_format_supported(screen
,
444 PIPE_BIND_SAMPLER_VIEW
))
447 switch (res
->usage
) {
448 case PIPE_USAGE_STREAM
:
449 case PIPE_USAGE_STAGING
:
457 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
458 struct pipe_resource
*ptex
,
459 struct winsys_handle
*whandle
)
461 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
462 struct r600_resource
*resource
= &rtex
->resource
;
463 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
465 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
466 rtex
->pitch_in_bytes
[0], whandle
);
469 static void r600_texture_destroy(struct pipe_screen
*screen
,
470 struct pipe_resource
*ptex
)
472 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
473 struct r600_resource
*resource
= &rtex
->resource
;
475 if (rtex
->flushed_depth_texture
)
476 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
479 pipe_resource_reference((struct pipe_resource
**)&rtex
->stencil
, NULL
);
481 pb_reference(&resource
->buf
, NULL
);
485 static const struct u_resource_vtbl r600_texture_vtbl
=
487 r600_texture_get_handle
, /* get_handle */
488 r600_texture_destroy
, /* resource_destroy */
489 r600_texture_get_transfer
, /* get_transfer */
490 r600_texture_transfer_destroy
, /* transfer_destroy */
491 r600_texture_transfer_map
, /* transfer_map */
492 NULL
, /* transfer_flush_region */
493 r600_texture_transfer_unmap
, /* transfer_unmap */
494 NULL
/* transfer_inline_write */
497 static struct r600_resource_texture
*
498 r600_texture_create_object(struct pipe_screen
*screen
,
499 const struct pipe_resource
*base
,
501 unsigned pitch_in_bytes_override
,
502 unsigned max_buffer_size
,
503 struct pb_buffer
*buf
,
505 struct radeon_surface
*surface
)
507 struct r600_resource_texture
*rtex
;
508 struct r600_resource
*resource
;
509 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
512 rtex
= CALLOC_STRUCT(r600_resource_texture
);
516 resource
= &rtex
->resource
;
517 resource
->b
.b
.b
= *base
;
518 resource
->b
.b
.vtbl
= &r600_texture_vtbl
;
519 pipe_reference_init(&resource
->b
.b
.b
.reference
, 1);
520 resource
->b
.b
.b
.screen
= screen
;
521 rtex
->pitch_override
= pitch_in_bytes_override
;
522 rtex
->real_format
= base
->format
;
524 /* We must split depth and stencil into two separate buffers on Evergreen. */
525 if (!(base
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
526 ((struct r600_screen
*)screen
)->chip_class
>= EVERGREEN
&&
527 util_format_is_depth_and_stencil(base
->format
) &&
528 !rscreen
->use_surface_alloc
) {
529 struct pipe_resource stencil
;
530 unsigned stencil_pitch_override
= 0;
532 switch (base
->format
) {
533 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
534 rtex
->real_format
= PIPE_FORMAT_Z24X8_UNORM
;
536 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
537 rtex
->real_format
= PIPE_FORMAT_X8Z24_UNORM
;
539 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
540 rtex
->real_format
= PIPE_FORMAT_Z32_FLOAT
;
548 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
549 if (pitch_in_bytes_override
) {
550 assert(base
->format
== PIPE_FORMAT_Z24_UNORM_S8_UINT
||
551 base
->format
== PIPE_FORMAT_S8_UINT_Z24_UNORM
);
552 stencil_pitch_override
= pitch_in_bytes_override
/ 4;
555 /* Allocate the stencil buffer. */
557 stencil
.format
= PIPE_FORMAT_S8_UINT
;
558 rtex
->stencil
= r600_texture_create_object(screen
, &stencil
, array_mode
,
559 stencil_pitch_override
,
560 max_buffer_size
, NULL
, FALSE
, surface
);
561 if (!rtex
->stencil
) {
565 /* Proceed in creating the depth buffer. */
568 /* only mark depth textures the HW can hit as depth textures */
569 if (util_format_is_depth_or_stencil(rtex
->real_format
) && permit_hardware_blit(screen
, base
))
570 rtex
->is_depth
= true;
572 r600_setup_miptree(screen
, rtex
, array_mode
);
573 if (rscreen
->use_surface_alloc
) {
574 rtex
->surface
= *surface
;
575 r
= r600_setup_surface(screen
, rtex
, array_mode
, pitch_in_bytes_override
);
582 /* If we initialized separate stencil for Evergreen. place it after depth. */
584 unsigned stencil_align
, stencil_offset
;
586 stencil_align
= r600_get_base_alignment(screen
, rtex
->stencil
->real_format
, array_mode
);
587 stencil_offset
= align(rtex
->size
, stencil_align
);
589 for (unsigned i
= 0; i
<= rtex
->stencil
->resource
.b
.b
.b
.last_level
; i
++)
590 rtex
->stencil
->offset
[i
] += stencil_offset
;
592 rtex
->size
= stencil_offset
+ rtex
->stencil
->size
;
595 /* Now create the backing buffer. */
596 if (!buf
&& alloc_bo
) {
597 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
598 unsigned base_align
= r600_get_base_alignment(screen
, ptex
->format
, array_mode
);
600 if (rscreen
->use_surface_alloc
) {
601 base_align
= rtex
->surface
.bo_alignment
;
602 } else if (util_format_is_depth_or_stencil(rtex
->real_format
)) {
603 /* ugly work around depth buffer need stencil room at end of bo */
604 rtex
->size
+= ptex
->width0
* ptex
->height0
;
606 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, base
->bind
, base
->usage
)) {
607 pipe_resource_reference((struct pipe_resource
**)&rtex
->stencil
, NULL
);
613 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
614 resource
->domains
= RADEON_DOMAIN_GTT
| RADEON_DOMAIN_VRAM
;
618 pb_reference(&rtex
->stencil
->resource
.buf
, rtex
->resource
.buf
);
619 rtex
->stencil
->resource
.cs_buf
= rtex
->resource
.cs_buf
;
620 rtex
->stencil
->resource
.domains
= rtex
->resource
.domains
;
625 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
626 const struct pipe_resource
*templ
)
628 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
629 struct radeon_surface surface
;
630 unsigned array_mode
= 0;
633 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
634 !(templ
->bind
& PIPE_BIND_SCANOUT
)) {
635 if (rscreen
->use_surface_alloc
) {
636 if (permit_hardware_blit(screen
, templ
)) {
637 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
639 } else if (util_format_is_compressed(templ
->format
)) {
640 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
644 r
= r600_init_surface(&surface
, templ
, array_mode
);
648 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
652 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
653 0, 0, NULL
, TRUE
, &surface
);
656 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
657 struct pipe_resource
*texture
,
658 const struct pipe_surface
*surf_tmpl
)
660 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
661 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
662 unsigned level
= surf_tmpl
->u
.tex
.level
;
664 assert(surf_tmpl
->u
.tex
.first_layer
== surf_tmpl
->u
.tex
.last_layer
);
668 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
669 pipe_reference_init(&surface
->base
.reference
, 1);
670 pipe_resource_reference(&surface
->base
.texture
, texture
);
671 surface
->base
.context
= pipe
;
672 surface
->base
.format
= surf_tmpl
->format
;
673 surface
->base
.width
= mip_minify(texture
->width0
, level
);
674 surface
->base
.height
= mip_minify(texture
->height0
, level
);
675 surface
->base
.usage
= surf_tmpl
->usage
;
676 surface
->base
.texture
= texture
;
677 surface
->base
.u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
678 surface
->base
.u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
679 surface
->base
.u
.tex
.level
= level
;
681 surface
->aligned_height
= r600_texture_get_nblocksy(pipe
->screen
,
683 return &surface
->base
;
686 static void r600_surface_destroy(struct pipe_context
*pipe
,
687 struct pipe_surface
*surface
)
689 pipe_resource_reference(&surface
->texture
, NULL
);
693 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
694 const struct pipe_resource
*templ
,
695 struct winsys_handle
*whandle
)
697 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
698 struct pb_buffer
*buf
= NULL
;
700 unsigned array_mode
= 0;
701 enum radeon_bo_layout micro
, macro
;
702 struct radeon_surface surface
;
705 /* Support only 2D textures without mipmaps */
706 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
707 templ
->depth0
!= 1 || templ
->last_level
!= 0)
710 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
714 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
715 &surface
.bankw
, &surface
.bankh
,
717 &surface
.stencil_tile_split
,
720 if (macro
== RADEON_LAYOUT_TILED
)
721 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
722 else if (micro
== RADEON_LAYOUT_TILED
)
723 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
727 r
= r600_init_surface(&surface
, templ
, array_mode
);
731 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
732 stride
, 0, buf
, FALSE
, &surface
);
735 int r600_texture_depth_flush(struct pipe_context
*ctx
,
736 struct pipe_resource
*texture
, boolean just_create
)
738 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
739 struct pipe_resource resource
;
741 if (rtex
->flushed_depth_texture
)
744 resource
.target
= texture
->target
;
745 resource
.format
= texture
->format
;
746 resource
.width0
= texture
->width0
;
747 resource
.height0
= texture
->height0
;
748 resource
.depth0
= texture
->depth0
;
749 resource
.array_size
= texture
->array_size
;
750 resource
.last_level
= texture
->last_level
;
751 resource
.nr_samples
= texture
->nr_samples
;
752 resource
.usage
= PIPE_USAGE_DYNAMIC
;
753 resource
.bind
= texture
->bind
| PIPE_BIND_DEPTH_STENCIL
;
754 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
| texture
->flags
;
756 rtex
->flushed_depth_texture
= (struct r600_resource_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
757 if (rtex
->flushed_depth_texture
== NULL
) {
758 R600_ERR("failed to create temporary texture to hold untiled copy\n");
762 ((struct r600_resource_texture
*)rtex
->flushed_depth_texture
)->is_flushing_texture
= TRUE
;
767 /* XXX: only do this if the depth texture has actually changed:
769 r600_blit_uncompress_depth(ctx
, rtex
);
773 /* Needs adjustment for pixelformat:
775 static INLINE
unsigned u_box_volume( const struct pipe_box
*box
)
777 return box
->width
* box
->depth
* box
->height
;
780 struct pipe_transfer
* r600_texture_get_transfer(struct pipe_context
*ctx
,
781 struct pipe_resource
*texture
,
784 const struct pipe_box
*box
)
786 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
787 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
788 struct pipe_resource resource
;
789 struct r600_transfer
*trans
;
791 boolean use_staging_texture
= FALSE
;
793 /* We cannot map a tiled texture directly because the data is
794 * in a different order, therefore we do detiling using a blit.
796 * Also, use a temporary in GTT memory for read transfers, as
797 * the CPU is much happier reading out of cached system memory
798 * than uncached VRAM.
800 if (R600_TEX_IS_TILED(rtex
, level
))
801 use_staging_texture
= TRUE
;
803 if ((usage
& PIPE_TRANSFER_READ
) && u_box_volume(box
) > 1024)
804 use_staging_texture
= TRUE
;
806 /* Use a staging texture for uploads if the underlying BO is busy. */
807 if (!(usage
& PIPE_TRANSFER_READ
) &&
808 (rctx
->ws
->cs_is_buffer_referenced(rctx
->cs
, rtex
->resource
.cs_buf
) ||
809 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
)))
810 use_staging_texture
= TRUE
;
812 if (!permit_hardware_blit(ctx
->screen
, texture
) ||
813 (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
))
814 use_staging_texture
= FALSE
;
816 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
819 trans
= CALLOC_STRUCT(r600_transfer
);
822 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
823 trans
->transfer
.level
= level
;
824 trans
->transfer
.usage
= usage
;
825 trans
->transfer
.box
= *box
;
826 if (rtex
->is_depth
) {
827 /* XXX: only readback the rectangle which is being mapped?
829 /* XXX: when discard is true, no need to read back from depth texture
831 r
= r600_texture_depth_flush(ctx
, texture
, FALSE
);
833 R600_ERR("failed to create temporary texture to hold untiled copy\n");
834 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
838 trans
->transfer
.stride
= rtex
->flushed_depth_texture
->pitch_in_bytes
[level
];
839 trans
->offset
= r600_texture_get_offset(rtex
->flushed_depth_texture
, level
, box
->z
);
840 return &trans
->transfer
;
841 } else if (use_staging_texture
) {
842 resource
.target
= PIPE_TEXTURE_2D
;
843 resource
.format
= texture
->format
;
844 resource
.width0
= box
->width
;
845 resource
.height0
= box
->height
;
847 resource
.array_size
= 1;
848 resource
.last_level
= 0;
849 resource
.nr_samples
= 0;
850 resource
.usage
= PIPE_USAGE_STAGING
;
852 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
853 /* For texture reading, the temporary (detiled) texture is used as
854 * a render target when blitting from a tiled texture. */
855 if (usage
& PIPE_TRANSFER_READ
) {
856 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
858 /* For texture writing, the temporary texture is used as a sampler
859 * when blitting into a tiled texture. */
860 if (usage
& PIPE_TRANSFER_WRITE
) {
861 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
863 /* Create the temporary texture. */
864 trans
->staging
= (struct r600_resource
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
865 if (trans
->staging
== NULL
) {
866 R600_ERR("failed to create temporary texture to hold untiled copy\n");
867 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
872 trans
->transfer
.stride
=
873 ((struct r600_resource_texture
*)trans
->staging
)->pitch_in_bytes
[0];
874 if (usage
& PIPE_TRANSFER_READ
) {
875 r600_copy_to_staging_texture(ctx
, trans
);
876 /* Always referenced in the blit. */
877 r600_flush(ctx
, NULL
, 0);
879 return &trans
->transfer
;
881 trans
->transfer
.stride
= rtex
->pitch_in_bytes
[level
];
882 trans
->transfer
.layer_stride
= rtex
->layer_size
[level
];
883 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
884 return &trans
->transfer
;
887 void r600_texture_transfer_destroy(struct pipe_context
*ctx
,
888 struct pipe_transfer
*transfer
)
890 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
891 struct pipe_resource
*texture
= transfer
->resource
;
892 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
894 if (rtransfer
->staging
) {
895 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
896 r600_copy_from_staging_texture(ctx
, rtransfer
);
898 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
901 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
902 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtex
->flushed_depth_texture
)
903 r600_blit_push_depth(ctx
, rtex
);
906 pipe_resource_reference(&transfer
->resource
, NULL
);
910 void* r600_texture_transfer_map(struct pipe_context
*ctx
,
911 struct pipe_transfer
* transfer
)
913 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
914 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
915 struct pb_buffer
*buf
;
916 enum pipe_format format
= transfer
->resource
->format
;
920 if (rtransfer
->staging
) {
921 buf
= ((struct r600_resource
*)rtransfer
->staging
)->buf
;
923 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
925 if (rtex
->flushed_depth_texture
)
926 buf
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->buf
;
928 buf
= ((struct r600_resource
*)transfer
->resource
)->buf
;
930 offset
= rtransfer
->offset
+
931 transfer
->box
.y
/ util_format_get_blockheight(format
) * transfer
->stride
+
932 transfer
->box
.x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
935 if (!(map
= rctx
->ws
->buffer_map(buf
, rctx
->cs
, transfer
->usage
))) {
942 void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
943 struct pipe_transfer
* transfer
)
945 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
946 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
947 struct pb_buffer
*buf
;
949 if (rtransfer
->staging
) {
950 buf
= ((struct r600_resource
*)rtransfer
->staging
)->buf
;
952 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
954 if (rtex
->flushed_depth_texture
) {
955 buf
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->buf
;
957 buf
= ((struct r600_resource
*)transfer
->resource
)->buf
;
960 rctx
->ws
->buffer_unmap(buf
);
963 void r600_init_surface_functions(struct r600_context
*r600
)
965 r600
->context
.create_surface
= r600_create_surface
;
966 r600
->context
.surface_destroy
= r600_surface_destroy
;
969 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
970 const unsigned char *swizzle_view
)
973 unsigned char swizzle
[4];
975 const uint32_t swizzle_shift
[4] = {
978 const uint32_t swizzle_bit
[4] = {
983 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
985 memcpy(swizzle
, swizzle_format
, 4);
989 for (i
= 0; i
< 4; i
++) {
990 switch (swizzle
[i
]) {
991 case UTIL_FORMAT_SWIZZLE_Y
:
992 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
994 case UTIL_FORMAT_SWIZZLE_Z
:
995 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
997 case UTIL_FORMAT_SWIZZLE_W
:
998 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
1000 case UTIL_FORMAT_SWIZZLE_0
:
1001 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
1003 case UTIL_FORMAT_SWIZZLE_1
:
1004 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
1006 default: /* UTIL_FORMAT_SWIZZLE_X */
1007 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
1013 /* texture format translate */
1014 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
1015 enum pipe_format format
,
1016 const unsigned char *swizzle_view
,
1017 uint32_t *word4_p
, uint32_t *yuv_format_p
)
1019 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
1020 const struct util_format_description
*desc
;
1021 boolean uniform
= TRUE
;
1022 static int r600_enable_s3tc
= -1;
1023 bool is_srgb_valid
= FALSE
;
1026 const uint32_t sign_bit
[4] = {
1027 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
1028 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
1029 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
1030 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
1032 desc
= util_format_description(format
);
1034 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
1036 /* Colorspace (return non-RGB formats directly). */
1037 switch (desc
->colorspace
) {
1038 /* Depth stencil formats */
1039 case UTIL_FORMAT_COLORSPACE_ZS
:
1041 case PIPE_FORMAT_Z16_UNORM
:
1044 case PIPE_FORMAT_X24S8_UINT
:
1045 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1046 case PIPE_FORMAT_Z24X8_UNORM
:
1047 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1050 case PIPE_FORMAT_S8X24_UINT
:
1051 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1052 case PIPE_FORMAT_X8Z24_UNORM
:
1053 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1056 case PIPE_FORMAT_S8_UINT
:
1058 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1060 case PIPE_FORMAT_Z32_FLOAT
:
1061 result
= FMT_32_FLOAT
;
1063 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1064 result
= FMT_X24_8_32_FLOAT
;
1070 case UTIL_FORMAT_COLORSPACE_YUV
:
1071 yuv_format
|= (1 << 30);
1073 case PIPE_FORMAT_UYVY
:
1074 case PIPE_FORMAT_YUYV
:
1078 goto out_unknown
; /* TODO */
1080 case UTIL_FORMAT_COLORSPACE_SRGB
:
1081 word4
|= S_038010_FORCE_DEGAMMA(1);
1088 if (r600_enable_s3tc
== -1) {
1089 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1090 if (rscreen
->info
.drm_minor
>= 9)
1091 r600_enable_s3tc
= 1;
1093 r600_enable_s3tc
= debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
1096 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1097 if (!r600_enable_s3tc
)
1101 case PIPE_FORMAT_RGTC1_SNORM
:
1102 case PIPE_FORMAT_LATC1_SNORM
:
1103 word4
|= sign_bit
[0];
1104 case PIPE_FORMAT_RGTC1_UNORM
:
1105 case PIPE_FORMAT_LATC1_UNORM
:
1108 case PIPE_FORMAT_RGTC2_SNORM
:
1109 case PIPE_FORMAT_LATC2_SNORM
:
1110 word4
|= sign_bit
[0] | sign_bit
[1];
1111 case PIPE_FORMAT_RGTC2_UNORM
:
1112 case PIPE_FORMAT_LATC2_UNORM
:
1120 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1122 if (!r600_enable_s3tc
)
1125 if (!util_format_s3tc_enabled
) {
1130 case PIPE_FORMAT_DXT1_RGB
:
1131 case PIPE_FORMAT_DXT1_RGBA
:
1132 case PIPE_FORMAT_DXT1_SRGB
:
1133 case PIPE_FORMAT_DXT1_SRGBA
:
1135 is_srgb_valid
= TRUE
;
1137 case PIPE_FORMAT_DXT3_RGBA
:
1138 case PIPE_FORMAT_DXT3_SRGBA
:
1140 is_srgb_valid
= TRUE
;
1142 case PIPE_FORMAT_DXT5_RGBA
:
1143 case PIPE_FORMAT_DXT5_SRGBA
:
1145 is_srgb_valid
= TRUE
;
1152 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1153 result
= FMT_5_9_9_9_SHAREDEXP
;
1155 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1156 result
= FMT_10_11_11_FLOAT
;
1161 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1162 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1163 word4
|= sign_bit
[i
];
1167 /* R8G8Bx_SNORM - TODO CxV8U8 */
1169 /* See whether the components are of the same size. */
1170 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1171 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1174 /* Non-uniform formats. */
1176 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1177 desc
->channel
[0].pure_integer
)
1178 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1179 switch(desc
->nr_channels
) {
1181 if (desc
->channel
[0].size
== 5 &&
1182 desc
->channel
[1].size
== 6 &&
1183 desc
->channel
[2].size
== 5) {
1189 if (desc
->channel
[0].size
== 5 &&
1190 desc
->channel
[1].size
== 5 &&
1191 desc
->channel
[2].size
== 5 &&
1192 desc
->channel
[3].size
== 1) {
1193 result
= FMT_1_5_5_5
;
1196 if (desc
->channel
[0].size
== 10 &&
1197 desc
->channel
[1].size
== 10 &&
1198 desc
->channel
[2].size
== 10 &&
1199 desc
->channel
[3].size
== 2) {
1200 result
= FMT_2_10_10_10
;
1208 /* Find the first non-VOID channel. */
1209 for (i
= 0; i
< 4; i
++) {
1210 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1218 /* uniform formats */
1219 switch (desc
->channel
[i
].type
) {
1220 case UTIL_FORMAT_TYPE_UNSIGNED
:
1221 case UTIL_FORMAT_TYPE_SIGNED
:
1223 if (!desc
->channel
[i
].normalized
&&
1224 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
1228 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1229 desc
->channel
[i
].pure_integer
)
1230 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1232 switch (desc
->channel
[i
].size
) {
1234 switch (desc
->nr_channels
) {
1239 result
= FMT_4_4_4_4
;
1244 switch (desc
->nr_channels
) {
1252 result
= FMT_8_8_8_8
;
1253 is_srgb_valid
= TRUE
;
1258 switch (desc
->nr_channels
) {
1266 result
= FMT_16_16_16_16
;
1271 switch (desc
->nr_channels
) {
1279 result
= FMT_32_32_32_32
;
1285 case UTIL_FORMAT_TYPE_FLOAT
:
1286 switch (desc
->channel
[i
].size
) {
1288 switch (desc
->nr_channels
) {
1290 result
= FMT_16_FLOAT
;
1293 result
= FMT_16_16_FLOAT
;
1296 result
= FMT_16_16_16_16_FLOAT
;
1301 switch (desc
->nr_channels
) {
1303 result
= FMT_32_FLOAT
;
1306 result
= FMT_32_32_FLOAT
;
1309 result
= FMT_32_32_32_32_FLOAT
;
1318 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
1323 *yuv_format_p
= yuv_format
;
1326 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */