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[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
36 {
37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
38 struct pipe_resource *texture = transfer->resource;
39
40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b,
41 0, 0, 0, 0, texture, transfer->level,
42 &transfer->box);
43 }
44
45
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
48 {
49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
50 struct pipe_resource *texture = transfer->resource;
51 struct pipe_box sbox;
52
53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
54
55 ctx->resource_copy_region(ctx, texture, transfer->level,
56 transfer->box.x, transfer->box.y, transfer->box.z,
57 &rtransfer->staging->b.b,
58 0, &sbox);
59 }
60
61 unsigned r600_texture_get_offset(struct r600_texture *rtex,
62 unsigned level, unsigned layer)
63 {
64 return rtex->surface.level[level].offset +
65 layer * rtex->surface.level[level].slice_size;
66 }
67
68 static int r600_init_surface(struct r600_screen *rscreen,
69 struct radeon_surface *surface,
70 const struct pipe_resource *ptex,
71 unsigned array_mode,
72 bool is_transfer, bool is_flushed_depth)
73 {
74 const struct util_format_description *desc =
75 util_format_description(ptex->format);
76 bool is_depth, is_stencil;
77
78 is_depth = util_format_has_depth(desc);
79 is_stencil = util_format_has_stencil(desc);
80
81 surface->npix_x = ptex->width0;
82 surface->npix_y = ptex->height0;
83 surface->npix_z = ptex->depth0;
84 surface->blk_w = util_format_get_blockwidth(ptex->format);
85 surface->blk_h = util_format_get_blockheight(ptex->format);
86 surface->blk_d = 1;
87 surface->array_size = 1;
88 surface->last_level = ptex->last_level;
89
90 if (rscreen->chip_class >= EVERGREEN &&
91 !is_transfer && !is_flushed_depth &&
92 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
93 surface->bpe = 4; /* stencil is allocated separately on evergreen */
94 } else {
95 surface->bpe = util_format_get_blocksize(ptex->format);
96 /* align byte per element on dword */
97 if (surface->bpe == 3) {
98 surface->bpe = 4;
99 }
100 }
101
102 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
103 surface->flags = 0;
104
105 switch (array_mode) {
106 case V_038000_ARRAY_1D_TILED_THIN1:
107 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
108 break;
109 case V_038000_ARRAY_2D_TILED_THIN1:
110 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
111 break;
112 case V_038000_ARRAY_LINEAR_ALIGNED:
113 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
114 break;
115 case V_038000_ARRAY_LINEAR_GENERAL:
116 default:
117 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
118 break;
119 }
120 switch (ptex->target) {
121 case PIPE_TEXTURE_1D:
122 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
123 break;
124 case PIPE_TEXTURE_RECT:
125 case PIPE_TEXTURE_2D:
126 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
127 break;
128 case PIPE_TEXTURE_3D:
129 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
130 break;
131 case PIPE_TEXTURE_1D_ARRAY:
132 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
133 surface->array_size = ptex->array_size;
134 break;
135 case PIPE_TEXTURE_2D_ARRAY:
136 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
137 surface->array_size = ptex->array_size;
138 break;
139 case PIPE_TEXTURE_CUBE:
140 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
141 break;
142 case PIPE_BUFFER:
143 default:
144 return -EINVAL;
145 }
146 if (ptex->bind & PIPE_BIND_SCANOUT) {
147 surface->flags |= RADEON_SURF_SCANOUT;
148 }
149
150 if (!is_transfer && !is_flushed_depth && is_depth) {
151 surface->flags |= RADEON_SURF_ZBUFFER;
152
153 if (is_stencil) {
154 surface->flags |= RADEON_SURF_SBUFFER;
155 }
156 }
157 return 0;
158 }
159
160 static int r600_setup_surface(struct pipe_screen *screen,
161 struct r600_texture *rtex,
162 unsigned pitch_in_bytes_override)
163 {
164 struct pipe_resource *ptex = &rtex->resource.b.b;
165 struct r600_screen *rscreen = (struct r600_screen*)screen;
166 unsigned i;
167 int r;
168
169 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
170 if (r) {
171 return r;
172 }
173 rtex->size = rtex->surface.bo_size;
174 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
175 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
176 * for those
177 */
178 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
179 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
180 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
181 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
182 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
183 }
184 }
185 for (i = 0; i <= ptex->last_level; i++) {
186 switch (rtex->surface.level[i].mode) {
187 case RADEON_SURF_MODE_LINEAR_ALIGNED:
188 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
189 break;
190 case RADEON_SURF_MODE_1D:
191 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
192 break;
193 case RADEON_SURF_MODE_2D:
194 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
195 break;
196 default:
197 case RADEON_SURF_MODE_LINEAR:
198 rtex->array_mode[i] = 0;
199 break;
200 }
201 }
202 return 0;
203 }
204
205 static boolean r600_texture_get_handle(struct pipe_screen* screen,
206 struct pipe_resource *ptex,
207 struct winsys_handle *whandle)
208 {
209 struct r600_texture *rtex = (struct r600_texture*)ptex;
210 struct r600_resource *resource = &rtex->resource;
211 struct radeon_surface *surface = &rtex->surface;
212 struct r600_screen *rscreen = (struct r600_screen*)screen;
213
214 rscreen->ws->buffer_set_tiling(resource->buf,
215 NULL,
216 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
217 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
218 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
219 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
220 surface->bankw, surface->bankh,
221 surface->tile_split,
222 surface->stencil_tile_split,
223 surface->mtilea,
224 rtex->surface.level[0].pitch_bytes);
225
226 return rscreen->ws->buffer_get_handle(resource->buf,
227 rtex->surface.level[0].pitch_bytes, whandle);
228 }
229
230 static void r600_texture_destroy(struct pipe_screen *screen,
231 struct pipe_resource *ptex)
232 {
233 struct r600_texture *rtex = (struct r600_texture*)ptex;
234 struct r600_resource *resource = &rtex->resource;
235
236 if (rtex->flushed_depth_texture)
237 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
238
239 pb_reference(&resource->buf, NULL);
240 FREE(rtex);
241 }
242
243 static const struct u_resource_vtbl r600_texture_vtbl =
244 {
245 r600_texture_get_handle, /* get_handle */
246 r600_texture_destroy, /* resource_destroy */
247 r600_texture_get_transfer, /* get_transfer */
248 r600_texture_transfer_destroy, /* transfer_destroy */
249 r600_texture_transfer_map, /* transfer_map */
250 NULL, /* transfer_flush_region */
251 r600_texture_transfer_unmap, /* transfer_unmap */
252 NULL /* transfer_inline_write */
253 };
254
255 static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
256 struct r600_texture *rtex)
257 {
258 /* FMASK is allocated pretty much like an ordinary texture.
259 * Here we use bpe in the units of bits, not bytes. */
260 struct radeon_surface fmask = rtex->surface;
261 unsigned nr_samples = rtex->resource.b.b.nr_samples;
262
263 switch (nr_samples) {
264 case 2:
265 /* This should be 8,1, but we should set nsamples > 1
266 * for the allocator to treat it as a multisample surface.
267 * Let's set 4,2 then. */
268 case 4:
269 fmask.bpe = 4;
270 fmask.nsamples = 2;
271 break;
272 case 8:
273 fmask.bpe = 8;
274 fmask.nsamples = 4;
275 break;
276 case 16:
277 fmask.bpe = 16;
278 fmask.nsamples = 4;
279 break;
280 default:
281 R600_ERR("Invalid sample count for FMASK allocation.\n");
282 return;
283 }
284
285 if (rscreen->chip_class >= EVERGREEN) {
286 fmask.bankh = nr_samples <= 4 ? 4 : 1;
287 }
288
289 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
290 R600_ERR("Got error in surface_init while allocating FMASK.\n");
291 return;
292 }
293 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
294
295 /* Reserve space for FMASK while converting bits back to bytes. */
296 rtex->fmask_bank_height = fmask.bankh;
297 rtex->fmask_offset = align(rtex->size, MAX2(256, fmask.bo_alignment));
298 rtex->fmask_size = (fmask.bo_size + 7) / 8;
299 rtex->size = rtex->fmask_offset + rtex->fmask_size;
300 #if 0
301 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
302 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
303 #endif
304 }
305
306 static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
307 struct r600_texture *rtex)
308 {
309 unsigned cmask_tile_width = 8;
310 unsigned cmask_tile_height = 8;
311 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
312 unsigned element_bits = 4;
313 unsigned cmask_cache_bits = 1024;
314 unsigned num_pipes = rscreen->tiling_info.num_channels;
315 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
316
317 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
318 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
319 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
320 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
321 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
322
323 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
324 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
325
326 unsigned base_align = num_pipes * pipe_interleave_bytes;
327 unsigned slice_bytes =
328 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
329 unsigned size = rtex->surface.array_size * align(slice_bytes, base_align);
330
331 assert(macro_tile_width % 128 == 0);
332 assert(macro_tile_height % 128 == 0);
333
334 rtex->cmask_slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
335 rtex->cmask_offset = align(rtex->size, MAX2(256, base_align));
336 rtex->cmask_size = size;
337 rtex->size = rtex->cmask_offset + rtex->cmask_size;
338 #if 0
339 printf("CMASK: macro tile width = %u, macro tile height = %u, "
340 "pitch elements = %u, height = %u, slice tile max = %u\n",
341 macro_tile_width, macro_tile_height, pitch_elements, height,
342 rtex->cmask_slice_tile_max);
343 #endif
344 }
345
346 static struct r600_texture *
347 r600_texture_create_object(struct pipe_screen *screen,
348 const struct pipe_resource *base,
349 unsigned pitch_in_bytes_override,
350 struct pb_buffer *buf,
351 boolean alloc_bo,
352 struct radeon_surface *surface)
353 {
354 struct r600_texture *rtex;
355 struct r600_resource *resource;
356 struct r600_screen *rscreen = (struct r600_screen*)screen;
357 int r;
358
359 rtex = CALLOC_STRUCT(r600_texture);
360 if (rtex == NULL)
361 return NULL;
362
363 resource = &rtex->resource;
364 resource->b.b = *base;
365 resource->b.vtbl = &r600_texture_vtbl;
366 pipe_reference_init(&resource->b.b.reference, 1);
367 resource->b.b.screen = screen;
368 rtex->pitch_override = pitch_in_bytes_override;
369
370 /* don't include stencil-only formats which we don't support for rendering */
371 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
372
373 rtex->surface = *surface;
374 r = r600_setup_surface(screen, rtex,
375 pitch_in_bytes_override);
376 if (r) {
377 FREE(rtex);
378 return NULL;
379 }
380
381 if (base->nr_samples > 1 && !rtex->is_depth && alloc_bo) {
382 r600_texture_allocate_fmask(rscreen, rtex);
383 r600_texture_allocate_cmask(rscreen, rtex);
384 }
385
386 if (!rtex->is_depth && base->nr_samples > 1 &&
387 (!rtex->fmask_size || !rtex->cmask_size)) {
388 FREE(rtex);
389 return NULL;
390 }
391
392 /* Now create the backing buffer. */
393 if (!buf && alloc_bo) {
394 unsigned base_align = rtex->surface.bo_alignment;
395 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
396
397 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, usage)) {
398 FREE(rtex);
399 return NULL;
400 }
401 } else if (buf) {
402 resource->buf = buf;
403 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
404 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
405 }
406
407 if (rtex->cmask_size) {
408 /* Initialize the cmask to 0xCC (= compressed state). */
409 char *ptr = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE);
410 memset(ptr + rtex->cmask_offset, 0xCC, rtex->cmask_size);
411 rscreen->ws->buffer_unmap(resource->cs_buf);
412 }
413 return rtex;
414 }
415
416 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
417 const struct pipe_resource *templ)
418 {
419 struct r600_screen *rscreen = (struct r600_screen*)screen;
420 struct radeon_surface surface;
421 unsigned array_mode = 0;
422 int r;
423
424 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) {
425 if (!(templ->bind & PIPE_BIND_SCANOUT) &&
426 templ->usage != PIPE_USAGE_STAGING &&
427 templ->usage != PIPE_USAGE_STREAM) {
428 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
429 } else if (util_format_is_compressed(templ->format)) {
430 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
431 }
432 }
433
434 /* XXX tiling is broken for the 422 formats */
435 if (util_format_description(templ->format)->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
436 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
437
438 r = r600_init_surface(rscreen, &surface, templ, array_mode,
439 templ->flags & R600_RESOURCE_FLAG_TRANSFER,
440 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
441 if (r) {
442 return NULL;
443 }
444 r = rscreen->ws->surface_best(rscreen->ws, &surface);
445 if (r) {
446 return NULL;
447 }
448 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
449 0, NULL, TRUE, &surface);
450 }
451
452 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
453 struct pipe_resource *texture,
454 const struct pipe_surface *templ)
455 {
456 struct r600_texture *rtex = (struct r600_texture*)texture;
457 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
458 unsigned level = templ->u.tex.level;
459
460 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
461 if (surface == NULL)
462 return NULL;
463 pipe_reference_init(&surface->base.reference, 1);
464 pipe_resource_reference(&surface->base.texture, texture);
465 surface->base.context = pipe;
466 surface->base.format = templ->format;
467 surface->base.width = rtex->surface.level[level].npix_x;
468 surface->base.height = rtex->surface.level[level].npix_y;
469 surface->base.usage = templ->usage;
470 surface->base.u = templ->u;
471 return &surface->base;
472 }
473
474 static void r600_surface_destroy(struct pipe_context *pipe,
475 struct pipe_surface *surface)
476 {
477 pipe_resource_reference(&surface->texture, NULL);
478 FREE(surface);
479 }
480
481 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
482 const struct pipe_resource *templ,
483 struct winsys_handle *whandle)
484 {
485 struct r600_screen *rscreen = (struct r600_screen*)screen;
486 struct pb_buffer *buf = NULL;
487 unsigned stride = 0;
488 unsigned array_mode = 0;
489 enum radeon_bo_layout micro, macro;
490 struct radeon_surface surface;
491 int r;
492
493 /* Support only 2D textures without mipmaps */
494 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
495 templ->depth0 != 1 || templ->last_level != 0)
496 return NULL;
497
498 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
499 if (!buf)
500 return NULL;
501
502 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
503 &surface.bankw, &surface.bankh,
504 &surface.tile_split,
505 &surface.stencil_tile_split,
506 &surface.mtilea);
507
508 if (macro == RADEON_LAYOUT_TILED)
509 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
510 else if (micro == RADEON_LAYOUT_TILED)
511 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
512 else
513 array_mode = 0;
514
515 r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false);
516 if (r) {
517 return NULL;
518 }
519 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
520 stride, buf, FALSE, &surface);
521 }
522
523 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
524 struct pipe_resource *texture,
525 struct r600_texture **staging)
526 {
527 struct r600_texture *rtex = (struct r600_texture*)texture;
528 struct pipe_resource resource;
529 struct r600_texture **flushed_depth_texture = staging ?
530 staging : &rtex->flushed_depth_texture;
531
532 if (!staging && rtex->flushed_depth_texture)
533 return true; /* it's ready */
534
535 resource.target = texture->target;
536 resource.format = texture->format;
537 resource.width0 = texture->width0;
538 resource.height0 = texture->height0;
539 resource.depth0 = texture->depth0;
540 resource.array_size = texture->array_size;
541 resource.last_level = texture->last_level;
542 resource.nr_samples = texture->nr_samples;
543 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
544 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
545 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
546
547 if (staging)
548 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
549
550 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
551 if (*flushed_depth_texture == NULL) {
552 R600_ERR("failed to create temporary texture to hold flushed depth\n");
553 return false;
554 }
555
556 (*flushed_depth_texture)->is_flushing_texture = TRUE;
557 return true;
558 }
559
560 /* Needs adjustment for pixelformat:
561 */
562 static INLINE unsigned u_box_volume( const struct pipe_box *box )
563 {
564 return box->width * box->depth * box->height;
565 }
566
567 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
568 struct pipe_resource *texture,
569 unsigned level,
570 unsigned usage,
571 const struct pipe_box *box)
572 {
573 struct r600_context *rctx = (struct r600_context*)ctx;
574 struct r600_texture *rtex = (struct r600_texture*)texture;
575 struct pipe_resource resource;
576 struct r600_transfer *trans;
577 boolean use_staging_texture = FALSE;
578
579 /* We cannot map a tiled texture directly because the data is
580 * in a different order, therefore we do detiling using a blit.
581 *
582 * Also, use a temporary in GTT memory for read transfers, as
583 * the CPU is much happier reading out of cached system memory
584 * than uncached VRAM.
585 */
586 if (R600_TEX_IS_TILED(rtex, level)) {
587 use_staging_texture = TRUE;
588 }
589
590 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
591 use_staging_texture = TRUE;
592
593 /* Use a staging texture for uploads if the underlying BO is busy. */
594 if (!(usage & PIPE_TRANSFER_READ) &&
595 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
596 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
597 use_staging_texture = TRUE;
598 }
599
600 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
601 use_staging_texture = FALSE;
602 }
603
604 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
605 return NULL;
606 }
607
608 trans = CALLOC_STRUCT(r600_transfer);
609 if (trans == NULL)
610 return NULL;
611 pipe_resource_reference(&trans->transfer.resource, texture);
612 trans->transfer.level = level;
613 trans->transfer.usage = usage;
614 trans->transfer.box = *box;
615 if (rtex->is_depth) {
616 /* XXX: only readback the rectangle which is being mapped?
617 */
618 /* XXX: when discard is true, no need to read back from depth texture
619 */
620 struct r600_texture *staging_depth;
621
622 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
623 R600_ERR("failed to create temporary texture to hold untiled copy\n");
624 pipe_resource_reference(&trans->transfer.resource, NULL);
625 FREE(trans);
626 return NULL;
627 }
628
629 r600_blit_decompress_depth(ctx, rtex, staging_depth,
630 level, level,
631 box->z, box->z + box->depth - 1,
632 0, 0);
633
634 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
635 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
636 trans->staging = (struct r600_resource*)staging_depth;
637 return &trans->transfer;
638 } else if (use_staging_texture) {
639 resource.target = PIPE_TEXTURE_2D;
640 resource.format = texture->format;
641 resource.width0 = box->width;
642 resource.height0 = box->height;
643 resource.depth0 = 1;
644 resource.array_size = 1;
645 resource.last_level = 0;
646 resource.nr_samples = 0;
647 resource.usage = PIPE_USAGE_STAGING;
648 resource.bind = 0;
649 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
650 /* For texture reading, the temporary (detiled) texture is used as
651 * a render target when blitting from a tiled texture. */
652 if (usage & PIPE_TRANSFER_READ) {
653 resource.bind |= PIPE_BIND_RENDER_TARGET;
654 }
655 /* For texture writing, the temporary texture is used as a sampler
656 * when blitting into a tiled texture. */
657 if (usage & PIPE_TRANSFER_WRITE) {
658 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
659 }
660 /* Create the temporary texture. */
661 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
662 if (trans->staging == NULL) {
663 R600_ERR("failed to create temporary texture to hold untiled copy\n");
664 pipe_resource_reference(&trans->transfer.resource, NULL);
665 FREE(trans);
666 return NULL;
667 }
668
669 trans->transfer.stride =
670 ((struct r600_texture *)trans->staging)->surface.level[0].pitch_bytes;
671 if (usage & PIPE_TRANSFER_READ) {
672 r600_copy_to_staging_texture(ctx, trans);
673 /* Always referenced in the blit. */
674 r600_flush(ctx, NULL, 0);
675 }
676 return &trans->transfer;
677 }
678 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
679 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
680 trans->offset = r600_texture_get_offset(rtex, level, box->z);
681 return &trans->transfer;
682 }
683
684 void r600_texture_transfer_destroy(struct pipe_context *ctx,
685 struct pipe_transfer *transfer)
686 {
687 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
688 struct pipe_resource *texture = transfer->resource;
689 struct r600_texture *rtex = (struct r600_texture*)texture;
690
691 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
692 if (rtex->is_depth) {
693 ctx->resource_copy_region(ctx, texture, transfer->level,
694 transfer->box.x, transfer->box.y, transfer->box.z,
695 &rtransfer->staging->b.b, transfer->level,
696 &transfer->box);
697 } else {
698 r600_copy_from_staging_texture(ctx, rtransfer);
699 }
700 }
701
702 if (rtransfer->staging)
703 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
704
705 pipe_resource_reference(&transfer->resource, NULL);
706 FREE(transfer);
707 }
708
709 void* r600_texture_transfer_map(struct pipe_context *ctx,
710 struct pipe_transfer* transfer)
711 {
712 struct r600_context *rctx = (struct r600_context *)ctx;
713 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
714 struct radeon_winsys_cs_handle *buf;
715 struct r600_texture *rtex =
716 (struct r600_texture*)transfer->resource;
717 enum pipe_format format = transfer->resource->format;
718 unsigned offset = 0;
719 char *map;
720
721 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
722 return r600_compute_global_transfer_map(ctx, transfer);
723 }
724
725 if (rtransfer->staging) {
726 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
727 } else {
728 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
729 }
730
731 if (rtex->is_depth || !rtransfer->staging)
732 offset = rtransfer->offset +
733 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
734 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
735
736 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
737 return NULL;
738 }
739
740 return map + offset;
741 }
742
743 void r600_texture_transfer_unmap(struct pipe_context *ctx,
744 struct pipe_transfer* transfer)
745 {
746 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
747 struct r600_context *rctx = (struct r600_context*)ctx;
748 struct radeon_winsys_cs_handle *buf;
749
750 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
751 return r600_compute_global_transfer_unmap(ctx, transfer);
752 }
753
754 if (rtransfer->staging) {
755 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
756 } else {
757 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
758 }
759 rctx->ws->buffer_unmap(buf);
760 }
761
762 void r600_init_surface_functions(struct r600_context *r600)
763 {
764 r600->context.create_surface = r600_create_surface;
765 r600->context.surface_destroy = r600_surface_destroy;
766 }
767
768 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
769 const unsigned char *swizzle_view)
770 {
771 unsigned i;
772 unsigned char swizzle[4];
773 unsigned result = 0;
774 const uint32_t swizzle_shift[4] = {
775 16, 19, 22, 25,
776 };
777 const uint32_t swizzle_bit[4] = {
778 0, 1, 2, 3,
779 };
780
781 if (swizzle_view) {
782 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
783 } else {
784 memcpy(swizzle, swizzle_format, 4);
785 }
786
787 /* Get swizzle. */
788 for (i = 0; i < 4; i++) {
789 switch (swizzle[i]) {
790 case UTIL_FORMAT_SWIZZLE_Y:
791 result |= swizzle_bit[1] << swizzle_shift[i];
792 break;
793 case UTIL_FORMAT_SWIZZLE_Z:
794 result |= swizzle_bit[2] << swizzle_shift[i];
795 break;
796 case UTIL_FORMAT_SWIZZLE_W:
797 result |= swizzle_bit[3] << swizzle_shift[i];
798 break;
799 case UTIL_FORMAT_SWIZZLE_0:
800 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
801 break;
802 case UTIL_FORMAT_SWIZZLE_1:
803 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
804 break;
805 default: /* UTIL_FORMAT_SWIZZLE_X */
806 result |= swizzle_bit[0] << swizzle_shift[i];
807 }
808 }
809 return result;
810 }
811
812 /* texture format translate */
813 uint32_t r600_translate_texformat(struct pipe_screen *screen,
814 enum pipe_format format,
815 const unsigned char *swizzle_view,
816 uint32_t *word4_p, uint32_t *yuv_format_p)
817 {
818 uint32_t result = 0, word4 = 0, yuv_format = 0;
819 const struct util_format_description *desc;
820 boolean uniform = TRUE;
821 static int r600_enable_s3tc = -1;
822 bool is_srgb_valid = FALSE;
823
824 int i;
825 const uint32_t sign_bit[4] = {
826 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
827 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
828 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
829 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
830 };
831 desc = util_format_description(format);
832
833 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
834
835 /* Colorspace (return non-RGB formats directly). */
836 switch (desc->colorspace) {
837 /* Depth stencil formats */
838 case UTIL_FORMAT_COLORSPACE_ZS:
839 switch (format) {
840 case PIPE_FORMAT_Z16_UNORM:
841 result = FMT_16;
842 goto out_word4;
843 case PIPE_FORMAT_X24S8_UINT:
844 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
845 case PIPE_FORMAT_Z24X8_UNORM:
846 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
847 result = FMT_8_24;
848 goto out_word4;
849 case PIPE_FORMAT_S8X24_UINT:
850 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
851 case PIPE_FORMAT_X8Z24_UNORM:
852 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
853 result = FMT_24_8;
854 goto out_word4;
855 case PIPE_FORMAT_S8_UINT:
856 result = FMT_8;
857 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
858 goto out_word4;
859 case PIPE_FORMAT_Z32_FLOAT:
860 result = FMT_32_FLOAT;
861 goto out_word4;
862 case PIPE_FORMAT_X32_S8X24_UINT:
863 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
864 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
865 result = FMT_X24_8_32_FLOAT;
866 goto out_word4;
867 default:
868 goto out_unknown;
869 }
870
871 case UTIL_FORMAT_COLORSPACE_YUV:
872 yuv_format |= (1 << 30);
873 switch (format) {
874 case PIPE_FORMAT_UYVY:
875 case PIPE_FORMAT_YUYV:
876 default:
877 break;
878 }
879 goto out_unknown; /* XXX */
880
881 case UTIL_FORMAT_COLORSPACE_SRGB:
882 word4 |= S_038010_FORCE_DEGAMMA(1);
883 break;
884
885 default:
886 break;
887 }
888
889 if (r600_enable_s3tc == -1) {
890 struct r600_screen *rscreen = (struct r600_screen *)screen;
891 if (rscreen->info.drm_minor >= 9)
892 r600_enable_s3tc = 1;
893 else
894 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
895 }
896
897 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
898 if (!r600_enable_s3tc)
899 goto out_unknown;
900
901 switch (format) {
902 case PIPE_FORMAT_RGTC1_SNORM:
903 case PIPE_FORMAT_LATC1_SNORM:
904 word4 |= sign_bit[0];
905 case PIPE_FORMAT_RGTC1_UNORM:
906 case PIPE_FORMAT_LATC1_UNORM:
907 result = FMT_BC4;
908 goto out_word4;
909 case PIPE_FORMAT_RGTC2_SNORM:
910 case PIPE_FORMAT_LATC2_SNORM:
911 word4 |= sign_bit[0] | sign_bit[1];
912 case PIPE_FORMAT_RGTC2_UNORM:
913 case PIPE_FORMAT_LATC2_UNORM:
914 result = FMT_BC5;
915 goto out_word4;
916 default:
917 goto out_unknown;
918 }
919 }
920
921 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
922
923 if (!r600_enable_s3tc)
924 goto out_unknown;
925
926 if (!util_format_s3tc_enabled) {
927 goto out_unknown;
928 }
929
930 switch (format) {
931 case PIPE_FORMAT_DXT1_RGB:
932 case PIPE_FORMAT_DXT1_RGBA:
933 case PIPE_FORMAT_DXT1_SRGB:
934 case PIPE_FORMAT_DXT1_SRGBA:
935 result = FMT_BC1;
936 is_srgb_valid = TRUE;
937 goto out_word4;
938 case PIPE_FORMAT_DXT3_RGBA:
939 case PIPE_FORMAT_DXT3_SRGBA:
940 result = FMT_BC2;
941 is_srgb_valid = TRUE;
942 goto out_word4;
943 case PIPE_FORMAT_DXT5_RGBA:
944 case PIPE_FORMAT_DXT5_SRGBA:
945 result = FMT_BC3;
946 is_srgb_valid = TRUE;
947 goto out_word4;
948 default:
949 goto out_unknown;
950 }
951 }
952
953 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
954 switch (format) {
955 case PIPE_FORMAT_R8G8_B8G8_UNORM:
956 case PIPE_FORMAT_G8R8_B8R8_UNORM:
957 result = FMT_GB_GR;
958 goto out_word4;
959 case PIPE_FORMAT_G8R8_G8B8_UNORM:
960 case PIPE_FORMAT_R8G8_R8B8_UNORM:
961 result = FMT_BG_RG;
962 goto out_word4;
963 default:
964 goto out_unknown;
965 }
966 }
967
968 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
969 result = FMT_5_9_9_9_SHAREDEXP;
970 goto out_word4;
971 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
972 result = FMT_10_11_11_FLOAT;
973 goto out_word4;
974 }
975
976
977 for (i = 0; i < desc->nr_channels; i++) {
978 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
979 word4 |= sign_bit[i];
980 }
981 }
982
983 /* R8G8Bx_SNORM - XXX CxV8U8 */
984
985 /* See whether the components are of the same size. */
986 for (i = 1; i < desc->nr_channels; i++) {
987 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
988 }
989
990 /* Non-uniform formats. */
991 if (!uniform) {
992 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
993 desc->channel[0].pure_integer)
994 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
995 switch(desc->nr_channels) {
996 case 3:
997 if (desc->channel[0].size == 5 &&
998 desc->channel[1].size == 6 &&
999 desc->channel[2].size == 5) {
1000 result = FMT_5_6_5;
1001 goto out_word4;
1002 }
1003 goto out_unknown;
1004 case 4:
1005 if (desc->channel[0].size == 5 &&
1006 desc->channel[1].size == 5 &&
1007 desc->channel[2].size == 5 &&
1008 desc->channel[3].size == 1) {
1009 result = FMT_1_5_5_5;
1010 goto out_word4;
1011 }
1012 if (desc->channel[0].size == 10 &&
1013 desc->channel[1].size == 10 &&
1014 desc->channel[2].size == 10 &&
1015 desc->channel[3].size == 2) {
1016 result = FMT_2_10_10_10;
1017 goto out_word4;
1018 }
1019 goto out_unknown;
1020 }
1021 goto out_unknown;
1022 }
1023
1024 /* Find the first non-VOID channel. */
1025 for (i = 0; i < 4; i++) {
1026 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1027 break;
1028 }
1029 }
1030
1031 if (i == 4)
1032 goto out_unknown;
1033
1034 /* uniform formats */
1035 switch (desc->channel[i].type) {
1036 case UTIL_FORMAT_TYPE_UNSIGNED:
1037 case UTIL_FORMAT_TYPE_SIGNED:
1038 #if 0
1039 if (!desc->channel[i].normalized &&
1040 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1041 goto out_unknown;
1042 }
1043 #endif
1044 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1045 desc->channel[i].pure_integer)
1046 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1047
1048 switch (desc->channel[i].size) {
1049 case 4:
1050 switch (desc->nr_channels) {
1051 case 2:
1052 result = FMT_4_4;
1053 goto out_word4;
1054 case 4:
1055 result = FMT_4_4_4_4;
1056 goto out_word4;
1057 }
1058 goto out_unknown;
1059 case 8:
1060 switch (desc->nr_channels) {
1061 case 1:
1062 result = FMT_8;
1063 goto out_word4;
1064 case 2:
1065 result = FMT_8_8;
1066 goto out_word4;
1067 case 4:
1068 result = FMT_8_8_8_8;
1069 is_srgb_valid = TRUE;
1070 goto out_word4;
1071 }
1072 goto out_unknown;
1073 case 16:
1074 switch (desc->nr_channels) {
1075 case 1:
1076 result = FMT_16;
1077 goto out_word4;
1078 case 2:
1079 result = FMT_16_16;
1080 goto out_word4;
1081 case 4:
1082 result = FMT_16_16_16_16;
1083 goto out_word4;
1084 }
1085 goto out_unknown;
1086 case 32:
1087 switch (desc->nr_channels) {
1088 case 1:
1089 result = FMT_32;
1090 goto out_word4;
1091 case 2:
1092 result = FMT_32_32;
1093 goto out_word4;
1094 case 4:
1095 result = FMT_32_32_32_32;
1096 goto out_word4;
1097 }
1098 }
1099 goto out_unknown;
1100
1101 case UTIL_FORMAT_TYPE_FLOAT:
1102 switch (desc->channel[i].size) {
1103 case 16:
1104 switch (desc->nr_channels) {
1105 case 1:
1106 result = FMT_16_FLOAT;
1107 goto out_word4;
1108 case 2:
1109 result = FMT_16_16_FLOAT;
1110 goto out_word4;
1111 case 4:
1112 result = FMT_16_16_16_16_FLOAT;
1113 goto out_word4;
1114 }
1115 goto out_unknown;
1116 case 32:
1117 switch (desc->nr_channels) {
1118 case 1:
1119 result = FMT_32_FLOAT;
1120 goto out_word4;
1121 case 2:
1122 result = FMT_32_32_FLOAT;
1123 goto out_word4;
1124 case 4:
1125 result = FMT_32_32_32_32_FLOAT;
1126 goto out_word4;
1127 }
1128 }
1129 goto out_unknown;
1130 }
1131
1132 out_word4:
1133
1134 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1135 return ~0;
1136 if (word4_p)
1137 *word4_p = word4;
1138 if (yuv_format_p)
1139 *yuv_format_p = yuv_format;
1140 return result;
1141 out_unknown:
1142 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1143 return ~0;
1144 }