src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include "pipe/p_screen.h"
  29 #include "util/u_format.h"
  30 #include "util/u_format_s3tc.h"
  31 #include "util/u_math.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_memory.h"
  34 #include "pipebuffer/pb_buffer.h"
  35 #include "r600_pipe.h"
  36 #include "r600_resource.h"
  37 #include "r600d.h"
  38 #include "r600_formats.h"
  39
  40 /* Copy from a full GPU texture to a transfer's staging one. */
  41 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  42 {
  43         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  44         struct pipe_resource *texture = transfer->resource;
  45
  46         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  47                                 0, 0, 0, 0, texture, transfer->level,
  48                                 &transfer->box);
  49 }
  50
  51
  52 /* Copy from a transfer's staging texture to a full GPU one. */
  53 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  54 {
  55         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  56         struct pipe_resource *texture = transfer->resource;
  57         struct pipe_box sbox;
  58
  59         sbox.x = sbox.y = sbox.z = 0;
  60         sbox.width = transfer->box.width;
  61         sbox.height = transfer->box.height;
  62         /* XXX that might be wrong */
  63         sbox.depth = 1;
  64         ctx->resource_copy_region(ctx, texture, transfer->level,
  65                                   transfer->box.x, transfer->box.y, transfer->box.z,
  66                                   rtransfer->staging_texture,
  67                                   0, &sbox);
  68
  69         ctx->texture_barrier(ctx);
  70 }
  71
  72 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  73                                         unsigned level, unsigned layer)
  74 {
  75         unsigned offset = rtex->offset[level];
  76
  77         switch (rtex->resource.b.b.b.target) {
  78         case PIPE_TEXTURE_3D:
  79         case PIPE_TEXTURE_CUBE:
  80         default:
  81                 return offset + layer * rtex->layer_size[level];
  82         }
  83 }
  84
  85 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
  86                                          enum pipe_format format,
  87                                          unsigned array_mode)
  88 {
  89         struct r600_screen* rscreen = (struct r600_screen *)screen;
  90         unsigned pixsize = util_format_get_blocksize(format);
  91         int p_align;
  92
  93         switch(array_mode) {
  94         case V_038000_ARRAY_1D_TILED_THIN1:
  95                 p_align = MAX2(8,
  96                                ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
  97                 break;
  98         case V_038000_ARRAY_2D_TILED_THIN1:
  99                 p_align = MAX2(rscreen->tiling_info.num_banks,
 100                                (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
 101                                 rscreen->tiling_info.num_banks)) * 8;
 102                 break;
 103         case V_038000_ARRAY_LINEAR_ALIGNED:
 104                 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
 105                 break;
 106         case V_038000_ARRAY_LINEAR_GENERAL:
 107         default:
 108                 p_align = rscreen->tiling_info.group_bytes / pixsize;
 109                 break;
 110         }
 111         return p_align;
 112 }
 113
 114 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 115                                           unsigned array_mode)
 116 {
 117         struct r600_screen* rscreen = (struct r600_screen *)screen;
 118         int h_align;
 119
 120         switch (array_mode) {
 121         case V_038000_ARRAY_2D_TILED_THIN1:
 122                 h_align = rscreen->tiling_info.num_channels * 8;
 123                 break;
 124         case V_038000_ARRAY_1D_TILED_THIN1:
 125         case V_038000_ARRAY_LINEAR_ALIGNED:
 126                 h_align = 8;
 127                 break;
 128         case V_038000_ARRAY_LINEAR_GENERAL:
 129         default:
 130                 h_align = 1;
 131                 break;
 132         }
 133         return h_align;
 134 }
 135
 136 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 137                                         enum pipe_format format,
 138                                         unsigned array_mode)
 139 {
 140         struct r600_screen* rscreen = (struct r600_screen *)screen;
 141         unsigned pixsize = util_format_get_blocksize(format);
 142         int p_align = r600_get_block_alignment(screen, format, array_mode);
 143         int h_align = r600_get_height_alignment(screen, array_mode);
 144         int b_align;
 145
 146         switch (array_mode) {
 147         case V_038000_ARRAY_2D_TILED_THIN1:
 148                 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
 149                                p_align * pixsize * h_align);
 150                 break;
 151         case V_038000_ARRAY_1D_TILED_THIN1:
 152         case V_038000_ARRAY_LINEAR_ALIGNED:
 153         case V_038000_ARRAY_LINEAR_GENERAL:
 154         default:
 155                 b_align = rscreen->tiling_info.group_bytes;
 156                 break;
 157         }
 158         return b_align;
 159 }
 160
 161 static unsigned mip_minify(unsigned size, unsigned level)
 162 {
 163         unsigned val;
 164         val = u_minify(size, level);
 165         if (level > 0)
 166                 val = util_next_power_of_two(val);
 167         return val;
 168 }
 169
 170 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
 171                                           struct r600_resource_texture *rtex,
 172                                           unsigned level)
 173 {
 174         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 175         unsigned nblocksx, block_align, width;
 176         unsigned blocksize = util_format_get_blocksize(rtex->real_format);
 177
 178         if (rtex->pitch_override)
 179                 return rtex->pitch_override / blocksize;
 180
 181         width = mip_minify(ptex->width0, level);
 182         nblocksx = util_format_get_nblocksx(rtex->real_format, width);
 183
 184         block_align = r600_get_block_alignment(screen, rtex->real_format,
 185                                               rtex->array_mode[level]);
 186         nblocksx = align(nblocksx, block_align);
 187         return nblocksx;
 188 }
 189
 190 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 191                                           struct r600_resource_texture *rtex,
 192                                           unsigned level)
 193 {
 194         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 195         unsigned height, tile_height;
 196
 197         height = mip_minify(ptex->height0, level);
 198         height = util_format_get_nblocksy(rtex->real_format, height);
 199         tile_height = r600_get_height_alignment(screen,
 200                                                 rtex->array_mode[level]);
 201
 202         /* XXX Hack around an alignment issue. Less tests fail with this.
 203          *
 204          * The thing is depth-stencil buffers should be tiled, i.e.
 205          * the alignment should be >=8. If I make them tiled, stencil starts
 206          * working because it no longer overlaps with the depth buffer
 207          * in memory, but texturing like drawpix-stencil breaks. */
 208         if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
 209                 tile_height = 8;
 210
 211         height = align(height, tile_height);
 212         return height;
 213 }
 214
 215 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 216                                         struct r600_resource_texture *rtex,
 217                                         unsigned level, unsigned array_mode)
 218 {
 219         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 220
 221         switch (array_mode) {
 222         case V_0280A0_ARRAY_LINEAR_GENERAL:
 223         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 224         case V_0280A0_ARRAY_1D_TILED_THIN1:
 225         default:
 226                 rtex->array_mode[level] = array_mode;
 227                 break;
 228         case V_0280A0_ARRAY_2D_TILED_THIN1:
 229         {
 230                 unsigned w, h, tile_height, tile_width;
 231
 232                 tile_height = r600_get_height_alignment(screen, array_mode);
 233                 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
 234
 235                 w = mip_minify(ptex->width0, level);
 236                 h = mip_minify(ptex->height0, level);
 237                 if (w <= tile_width || h <= tile_height)
 238                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 239                 else
 240                         rtex->array_mode[level] = array_mode;
 241         }
 242         break;
 243         }
 244 }
 245
 246 static void r600_setup_miptree(struct pipe_screen *screen,
 247                                struct r600_resource_texture *rtex,
 248                                unsigned array_mode)
 249 {
 250         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 251         enum chip_class chipc = ((struct r600_screen*)screen)->chip_class;
 252         unsigned size, layer_size, i, offset;
 253         unsigned nblocksx, nblocksy;
 254
 255         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 256                 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
 257                 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
 258
 259                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 260
 261                 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
 262                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 263
 264                 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL)
 265                         layer_size = align(nblocksx, 64) * nblocksy * blocksize;
 266                 else
 267                         layer_size = nblocksx * nblocksy * blocksize;
 268
 269                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 270                         if (chipc >= R700)
 271                                 size = layer_size * 8;
 272                         else
 273                                 size = layer_size * 6;
 274                 }
 275                 else if (ptex->target == PIPE_TEXTURE_3D)
 276                         size = layer_size * u_minify(ptex->depth0, i);
 277                 else
 278                         size = layer_size * ptex->array_size;
 279
 280                 /* align base image and start of miptree */
 281                 if ((i == 0) || (i == 1))
 282                         offset = align(offset, base_align);
 283                 rtex->offset[i] = offset;
 284                 rtex->layer_size[i] = layer_size;
 285                 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
 286                 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
 287
 288                 offset += size;
 289         }
 290         rtex->size = offset;
 291 }
 292
 293 /* Figure out whether u_blitter will fallback to a transfer operation.
 294  * If so, don't use a staging resource.
 295  */
 296 static boolean permit_hardware_blit(struct pipe_screen *screen,
 297                                         const struct pipe_resource *res)
 298 {
 299         unsigned bind;
 300
 301         if (util_format_is_depth_or_stencil(res->format))
 302                 bind = PIPE_BIND_DEPTH_STENCIL;
 303         else
 304                 bind = PIPE_BIND_RENDER_TARGET;
 305
 306         /* hackaround for S3TC */
 307         if (util_format_is_compressed(res->format))
 308                 return TRUE;
 309
 310         if (!screen->is_format_supported(screen,
 311                                 res->format,
 312                                 res->target,
 313                                 res->nr_samples,
 314                                 bind))
 315                 return FALSE;
 316
 317         if (!screen->is_format_supported(screen,
 318                                 res->format,
 319                                 res->target,
 320                                 res->nr_samples,
 321                                 PIPE_BIND_SAMPLER_VIEW))
 322                 return FALSE;
 323
 324         switch (res->usage) {
 325         case PIPE_USAGE_STREAM:
 326         case PIPE_USAGE_STAGING:
 327                 return FALSE;
 328
 329         default:
 330                 return TRUE;
 331         }
 332 }
 333
 334 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 335                                         struct pipe_resource *ptex,
 336                                         struct winsys_handle *whandle)
 337 {
 338         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 339         struct r600_resource *resource = &rtex->resource;
 340         struct r600_screen *rscreen = (struct r600_screen*)screen;
 341
 342         return rscreen->ws->buffer_get_handle(resource->buf,
 343                                               rtex->pitch_in_bytes[0], whandle);
 344 }
 345
 346 static void r600_texture_destroy(struct pipe_screen *screen,
 347                                  struct pipe_resource *ptex)
 348 {
 349         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 350         struct r600_resource *resource = &rtex->resource;
 351
 352         if (rtex->flushed_depth_texture)
 353                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 354
 355         pb_reference(&resource->buf, NULL);
 356         FREE(rtex);
 357 }
 358
 359 static const struct u_resource_vtbl r600_texture_vtbl =
 360 {
 361         r600_texture_get_handle,        /* get_handle */
 362         r600_texture_destroy,           /* resource_destroy */
 363         r600_texture_get_transfer,      /* get_transfer */
 364         r600_texture_transfer_destroy,  /* transfer_destroy */
 365         r600_texture_transfer_map,      /* transfer_map */
 366         u_default_transfer_flush_region,/* transfer_flush_region */
 367         r600_texture_transfer_unmap,    /* transfer_unmap */
 368         u_default_transfer_inline_write /* transfer_inline_write */
 369 };
 370
 371 static struct r600_resource_texture *
 372 r600_texture_create_object(struct pipe_screen *screen,
 373                            const struct pipe_resource *base,
 374                            unsigned array_mode,
 375                            unsigned pitch_in_bytes_override,
 376                            unsigned max_buffer_size,
 377                            struct pb_buffer *buf,
 378                            boolean alloc_bo)
 379 {
 380         struct r600_resource_texture *rtex;
 381         struct r600_resource *resource;
 382         struct r600_screen *rscreen = (struct r600_screen*)screen;
 383
 384         rtex = CALLOC_STRUCT(r600_resource_texture);
 385         if (rtex == NULL)
 386                 return NULL;
 387
 388         resource = &rtex->resource;
 389         resource->b.b.b = *base;
 390         resource->b.b.vtbl = &r600_texture_vtbl;
 391         pipe_reference_init(&resource->b.b.b.reference, 1);
 392         resource->b.b.b.screen = screen;
 393         rtex->pitch_override = pitch_in_bytes_override;
 394         rtex->real_format = base->format;
 395
 396         /* We must split depth and stencil into two separate buffers on Evergreen. */
 397         if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 398             ((struct r600_screen*)screen)->chip_class >= EVERGREEN &&
 399             util_format_is_depth_and_stencil(base->format)) {
 400                 struct pipe_resource stencil;
 401                 unsigned stencil_pitch_override = 0;
 402
 403                 switch (base->format) {
 404                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 405                         rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
 406                         break;
 407                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 408                         rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
 409                         break;
 410                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 411                         rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
 412                         break;
 413                 default:
 414                         assert(0);
 415                         FREE(rtex);
 416                         return NULL;
 417                 }
 418
 419                 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
 420                 if (pitch_in_bytes_override) {
 421                         assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT ||
 422                                base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
 423                         stencil_pitch_override = pitch_in_bytes_override / 4;
 424                 }
 425
 426                 /* Allocate the stencil buffer. */
 427                 stencil = *base;
 428                 stencil.format = PIPE_FORMAT_S8_UINT;
 429                 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
 430                                                            stencil_pitch_override,
 431                                                            max_buffer_size, NULL, FALSE);
 432                 if (!rtex->stencil) {
 433                         FREE(rtex);
 434                         return NULL;
 435                 }
 436                 /* Proceed in creating the depth buffer. */
 437         }
 438
 439         /* only mark depth textures the HW can hit as depth textures */
 440         if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
 441                 rtex->depth = 1;
 442
 443         r600_setup_miptree(screen, rtex, array_mode);
 444
 445         /* If we initialized separate stencil for Evergreen. place it after depth. */
 446         if (rtex->stencil) {
 447                 unsigned stencil_align, stencil_offset;
 448
 449                 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
 450                 stencil_offset = align(rtex->size, stencil_align);
 451
 452                 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++)
 453                         rtex->stencil->offset[i] += stencil_offset;
 454
 455                 rtex->size = stencil_offset + rtex->stencil->size;
 456         }
 457
 458         /* Now create the backing buffer. */
 459         if (!buf && alloc_bo) {
 460                 struct pipe_resource *ptex = &rtex->resource.b.b.b;
 461                 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 462
 463                 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
 464                         pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
 465                         FREE(rtex);
 466                         return NULL;
 467                 }
 468         } else if (buf) {
 469                 resource->buf = buf;
 470                 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
 471         }
 472
 473         if (rtex->stencil) {
 474                 rtex->stencil->resource.buf = rtex->resource.buf;
 475                 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf;
 476         }
 477         return rtex;
 478 }
 479
 480 DEBUG_GET_ONCE_BOOL_OPTION(tiling_enabled, "R600_TILING", FALSE);
 481
 482 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 483                                                 const struct pipe_resource *templ)
 484 {
 485         struct r600_screen *rscreen = (struct r600_screen*)screen;
 486         unsigned array_mode = 0;
 487
 488         if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 489             !(templ->bind & PIPE_BIND_SCANOUT)) {
 490                 if (util_format_is_compressed(templ->format)) {
 491                         array_mode = V_038000_ARRAY_1D_TILED_THIN1;
 492                 }
 493                 else if (debug_get_option_tiling_enabled() &&
 494                          rscreen->info.drm_minor >= 9 &&
 495                          permit_hardware_blit(screen, templ)) {
 496                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 497                 }
 498         }
 499
 500         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 501                                                                   0, 0, NULL, TRUE);
 502 }
 503
 504 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 505                                                 struct pipe_resource *texture,
 506                                                 const struct pipe_surface *surf_tmpl)
 507 {
 508         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 509         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 510         unsigned level = surf_tmpl->u.tex.level;
 511
 512         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 513         if (surface == NULL)
 514                 return NULL;
 515         /* XXX no offset */
 516 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 517         pipe_reference_init(&surface->base.reference, 1);
 518         pipe_resource_reference(&surface->base.texture, texture);
 519         surface->base.context = pipe;
 520         surface->base.format = surf_tmpl->format;
 521         surface->base.width = mip_minify(texture->width0, level);
 522         surface->base.height = mip_minify(texture->height0, level);
 523         surface->base.usage = surf_tmpl->usage;
 524         surface->base.texture = texture;
 525         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 526         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 527         surface->base.u.tex.level = level;
 528
 529         surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
 530                                                             rtex, level);
 531         return &surface->base;
 532 }
 533
 534 static void r600_surface_destroy(struct pipe_context *pipe,
 535                                  struct pipe_surface *surface)
 536 {
 537         pipe_resource_reference(&surface->texture, NULL);
 538         FREE(surface);
 539 }
 540
 541 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 542                                                const struct pipe_resource *templ,
 543                                                struct winsys_handle *whandle)
 544 {
 545         struct r600_screen *rscreen = (struct r600_screen*)screen;
 546         struct pb_buffer *buf = NULL;
 547         unsigned stride = 0;
 548         unsigned array_mode = 0;
 549         enum radeon_bo_layout micro, macro;
 550
 551         /* Support only 2D textures without mipmaps */
 552         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 553               templ->depth0 != 1 || templ->last_level != 0)
 554                 return NULL;
 555
 556         buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
 557         if (!buf)
 558                 return NULL;
 559
 560         rscreen->ws->buffer_get_tiling(buf, &micro, &macro);
 561
 562         if (macro == RADEON_LAYOUT_TILED)
 563                 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
 564         else if (micro == RADEON_LAYOUT_TILED)
 565                 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
 566         else
 567                 array_mode = 0;
 568
 569         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 570                                                                   stride, 0, buf, FALSE);
 571 }
 572
 573 int r600_texture_depth_flush(struct pipe_context *ctx,
 574                              struct pipe_resource *texture, boolean just_create)
 575 {
 576         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 577         struct pipe_resource resource;
 578
 579         if (rtex->flushed_depth_texture)
 580                 goto out;
 581
 582         resource.target = texture->target;
 583         resource.format = texture->format;
 584         resource.width0 = texture->width0;
 585         resource.height0 = texture->height0;
 586         resource.depth0 = texture->depth0;
 587         resource.array_size = texture->array_size;
 588         resource.last_level = texture->last_level;
 589         resource.nr_samples = texture->nr_samples;
 590         resource.usage = PIPE_USAGE_DYNAMIC;
 591         resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL;
 592         resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags;
 593
 594         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 595         if (rtex->flushed_depth_texture == NULL) {
 596                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 597                 return -ENOMEM;
 598         }
 599
 600         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 601 out:
 602         if (just_create)
 603                 return 0;
 604
 605         /* XXX: only do this if the depth texture has actually changed:
 606          */
 607         r600_blit_uncompress_depth(ctx, rtex);
 608         return 0;
 609 }
 610
 611 /* Needs adjustment for pixelformat:
 612  */
 613 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 614 {
 615         return box->width * box->depth * box->height;
 616 };
 617
 618 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 619                                                 struct pipe_resource *texture,
 620                                                 unsigned level,
 621                                                 unsigned usage,
 622                                                 const struct pipe_box *box)
 623 {
 624         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 625         struct pipe_resource resource;
 626         struct r600_transfer *trans;
 627         int r;
 628         boolean use_staging_texture = FALSE;
 629
 630         /* We cannot map a tiled texture directly because the data is
 631          * in a different order, therefore we do detiling using a blit.
 632          *
 633          * Also, use a temporary in GTT memory for read transfers, as
 634          * the CPU is much happier reading out of cached system memory
 635          * than uncached VRAM.
 636          */
 637         if (R600_TEX_IS_TILED(rtex, level))
 638                 use_staging_texture = TRUE;
 639
 640         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 641                 use_staging_texture = TRUE;
 642
 643         /* XXX: Use a staging texture for uploads if the underlying BO
 644          * is busy.  No interface for checking that currently? so do
 645          * it eagerly whenever the transfer doesn't require a readback
 646          * and might block.
 647          */
 648         if ((usage & PIPE_TRANSFER_WRITE) &&
 649                         !(usage & (PIPE_TRANSFER_READ |
 650                                         PIPE_TRANSFER_DONTBLOCK |
 651                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 652                 use_staging_texture = TRUE;
 653
 654         if (!permit_hardware_blit(ctx->screen, texture) ||
 655                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 656                 use_staging_texture = FALSE;
 657
 658         if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
 659                 return NULL;
 660
 661         trans = CALLOC_STRUCT(r600_transfer);
 662         if (trans == NULL)
 663                 return NULL;
 664         pipe_resource_reference(&trans->transfer.resource, texture);
 665         trans->transfer.level = level;
 666         trans->transfer.usage = usage;
 667         trans->transfer.box = *box;
 668         if (rtex->depth) {
 669                 /* XXX: only readback the rectangle which is being mapped?
 670                 */
 671                 /* XXX: when discard is true, no need to read back from depth texture
 672                 */
 673                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 674                 if (r < 0) {
 675                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 676                         pipe_resource_reference(&trans->transfer.resource, NULL);
 677                         FREE(trans);
 678                         return NULL;
 679                 }
 680                 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
 681                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 682                 return &trans->transfer;
 683         } else if (use_staging_texture) {
 684                 resource.target = PIPE_TEXTURE_2D;
 685                 resource.format = texture->format;
 686                 resource.width0 = box->width;
 687                 resource.height0 = box->height;
 688                 resource.depth0 = 1;
 689                 resource.array_size = 1;
 690                 resource.last_level = 0;
 691                 resource.nr_samples = 0;
 692                 resource.usage = PIPE_USAGE_STAGING;
 693                 resource.bind = 0;
 694                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 695                 /* For texture reading, the temporary (detiled) texture is used as
 696                  * a render target when blitting from a tiled texture. */
 697                 if (usage & PIPE_TRANSFER_READ) {
 698                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 699                 }
 700                 /* For texture writing, the temporary texture is used as a sampler
 701                  * when blitting into a tiled texture. */
 702                 if (usage & PIPE_TRANSFER_WRITE) {
 703                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 704                 }
 705                 /* Create the temporary texture. */
 706                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 707                 if (trans->staging_texture == NULL) {
 708                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 709                         pipe_resource_reference(&trans->transfer.resource, NULL);
 710                         FREE(trans);
 711                         return NULL;
 712                 }
 713
 714                 trans->transfer.stride =
 715                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 716                 if (usage & PIPE_TRANSFER_READ) {
 717                         r600_copy_to_staging_texture(ctx, trans);
 718                         /* Always referenced in the blit. */
 719                         r600_flush(ctx, NULL, 0);
 720                 }
 721                 return &trans->transfer;
 722         }
 723         trans->transfer.stride = rtex->pitch_in_bytes[level];
 724         trans->transfer.layer_stride = rtex->layer_size[level];
 725         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 726         return &trans->transfer;
 727 }
 728
 729 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 730                                    struct pipe_transfer *transfer)
 731 {
 732         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 733         struct pipe_resource *texture = transfer->resource;
 734         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 735
 736         if (rtransfer->staging_texture) {
 737                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 738                         r600_copy_from_staging_texture(ctx, rtransfer);
 739                 }
 740                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 741         }
 742
 743         if (rtex->depth && !rtex->is_flushing_texture) {
 744                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 745                         r600_blit_push_depth(ctx, rtex);
 746         }
 747
 748         pipe_resource_reference(&transfer->resource, NULL);
 749         FREE(transfer);
 750 }
 751
 752 void* r600_texture_transfer_map(struct pipe_context *ctx,
 753                                 struct pipe_transfer* transfer)
 754 {
 755         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 756         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 757         struct pb_buffer *buf;
 758         enum pipe_format format = transfer->resource->format;
 759         unsigned offset = 0;
 760         char *map;
 761
 762         if (rtransfer->staging_texture) {
 763                 buf = ((struct r600_resource *)rtransfer->staging_texture)->buf;
 764         } else {
 765                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 766
 767                 if (rtex->flushed_depth_texture)
 768                         buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf;
 769                 else
 770                         buf = ((struct r600_resource *)transfer->resource)->buf;
 771
 772                 offset = rtransfer->offset +
 773                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 774                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 775         }
 776
 777         if (!(map = rctx->ws->buffer_map(buf, rctx->ctx.cs, transfer->usage))) {
 778                 return NULL;
 779         }
 780
 781         return map + offset;
 782 }
 783
 784 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 785                                  struct pipe_transfer* transfer)
 786 {
 787         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 788         struct r600_pipe_context *rctx = (struct r600_pipe_context*)ctx;
 789         struct pb_buffer *buf;
 790
 791         if (rtransfer->staging_texture) {
 792                 buf = ((struct r600_resource *)rtransfer->staging_texture)->buf;
 793         } else {
 794                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 795
 796                 if (rtex->flushed_depth_texture) {
 797                         buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf;
 798                 } else {
 799                         buf = ((struct r600_resource *)transfer->resource)->buf;
 800                 }
 801         }
 802         rctx->ws->buffer_unmap(buf);
 803 }
 804
 805 void r600_init_surface_functions(struct r600_pipe_context *r600)
 806 {
 807         r600->context.create_surface = r600_create_surface;
 808         r600->context.surface_destroy = r600_surface_destroy;
 809 }
 810
 811 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 812                 const unsigned char *swizzle_view)
 813 {
 814         unsigned i;
 815         unsigned char swizzle[4];
 816         unsigned result = 0;
 817         const uint32_t swizzle_shift[4] = {
 818                 16, 19, 22, 25,
 819         };
 820         const uint32_t swizzle_bit[4] = {
 821                 0, 1, 2, 3,
 822         };
 823
 824         if (swizzle_view) {
 825                 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
 826         } else {
 827                 memcpy(swizzle, swizzle_format, 4);
 828         }
 829
 830         /* Get swizzle. */
 831         for (i = 0; i < 4; i++) {
 832                 switch (swizzle[i]) {
 833                 case UTIL_FORMAT_SWIZZLE_Y:
 834                         result |= swizzle_bit[1] << swizzle_shift[i];
 835                         break;
 836                 case UTIL_FORMAT_SWIZZLE_Z:
 837                         result |= swizzle_bit[2] << swizzle_shift[i];
 838                         break;
 839                 case UTIL_FORMAT_SWIZZLE_W:
 840                         result |= swizzle_bit[3] << swizzle_shift[i];
 841                         break;
 842                 case UTIL_FORMAT_SWIZZLE_0:
 843                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 844                         break;
 845                 case UTIL_FORMAT_SWIZZLE_1:
 846                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 847                         break;
 848                 default: /* UTIL_FORMAT_SWIZZLE_X */
 849                         result |= swizzle_bit[0] << swizzle_shift[i];
 850                 }
 851         }
 852         return result;
 853 }
 854
 855 /* texture format translate */
 856 uint32_t r600_translate_texformat(struct pipe_screen *screen,
 857                                   enum pipe_format format,
 858                                   const unsigned char *swizzle_view,
 859                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 860 {
 861         uint32_t result = 0, word4 = 0, yuv_format = 0;
 862         const struct util_format_description *desc;
 863         boolean uniform = TRUE;
 864         static int r600_enable_s3tc = -1;
 865
 866         int i;
 867         const uint32_t sign_bit[4] = {
 868                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 869                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 870                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 871                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 872         };
 873         desc = util_format_description(format);
 874
 875         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 876
 877         /* Colorspace (return non-RGB formats directly). */
 878         switch (desc->colorspace) {
 879                 /* Depth stencil formats */
 880         case UTIL_FORMAT_COLORSPACE_ZS:
 881                 switch (format) {
 882                 case PIPE_FORMAT_Z16_UNORM:
 883                         result = FMT_16;
 884                         goto out_word4;
 885                 case PIPE_FORMAT_X24S8_UINT:
 886                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 887                 case PIPE_FORMAT_Z24X8_UNORM:
 888                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 889                         result = FMT_8_24;
 890                         goto out_word4;
 891                 case PIPE_FORMAT_S8X24_UINT:
 892                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 893                 case PIPE_FORMAT_X8Z24_UNORM:
 894                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 895                         result = FMT_24_8;
 896                         goto out_word4;
 897                 case PIPE_FORMAT_S8_UINT:
 898                         result = FMT_8;
 899                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 900                         goto out_word4;
 901                 case PIPE_FORMAT_Z32_FLOAT:
 902                         result = FMT_32_FLOAT;
 903                         goto out_word4;
 904                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 905                         result = FMT_X24_8_32_FLOAT;
 906                         goto out_word4;
 907                 default:
 908                         goto out_unknown;
 909                 }
 910
 911         case UTIL_FORMAT_COLORSPACE_YUV:
 912                 yuv_format |= (1 << 30);
 913                 switch (format) {
 914                 case PIPE_FORMAT_UYVY:
 915                 case PIPE_FORMAT_YUYV:
 916                 default:
 917                         break;
 918                 }
 919                 goto out_unknown; /* TODO */
 920
 921         case UTIL_FORMAT_COLORSPACE_SRGB:
 922                 word4 |= S_038010_FORCE_DEGAMMA(1);
 923                 break;
 924
 925         default:
 926                 break;
 927         }
 928
 929         if (r600_enable_s3tc == -1) {
 930                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 931                 if (rscreen->info.drm_minor >= 9)
 932                         r600_enable_s3tc = 1;
 933                 else
 934                         r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 935         }
 936
 937         if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 938                 if (!r600_enable_s3tc)
 939                         goto out_unknown;
 940
 941                 switch (format) {
 942                 case PIPE_FORMAT_RGTC1_SNORM:
 943                 case PIPE_FORMAT_LATC1_SNORM:
 944                         word4 |= sign_bit[0];
 945                 case PIPE_FORMAT_RGTC1_UNORM:
 946                 case PIPE_FORMAT_LATC1_UNORM:
 947                         result = FMT_BC4;
 948                         goto out_word4;
 949                 case PIPE_FORMAT_RGTC2_SNORM:
 950                 case PIPE_FORMAT_LATC2_SNORM:
 951                         word4 |= sign_bit[0] | sign_bit[1];
 952                 case PIPE_FORMAT_RGTC2_UNORM:
 953                 case PIPE_FORMAT_LATC2_UNORM:
 954                         result = FMT_BC5;
 955                         goto out_word4;
 956                 default:
 957                         goto out_unknown;
 958                 }
 959         }
 960
 961         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 962
 963                 if (!r600_enable_s3tc)
 964                         goto out_unknown;
 965
 966                 if (!util_format_s3tc_enabled) {
 967                         goto out_unknown;
 968                 }
 969
 970                 switch (format) {
 971                 case PIPE_FORMAT_DXT1_RGB:
 972                 case PIPE_FORMAT_DXT1_RGBA:
 973                 case PIPE_FORMAT_DXT1_SRGB:
 974                 case PIPE_FORMAT_DXT1_SRGBA:
 975                         result = FMT_BC1;
 976                         goto out_word4;
 977                 case PIPE_FORMAT_DXT3_RGBA:
 978                 case PIPE_FORMAT_DXT3_SRGBA:
 979                         result = FMT_BC2;
 980                         goto out_word4;
 981                 case PIPE_FORMAT_DXT5_RGBA:
 982                 case PIPE_FORMAT_DXT5_SRGBA:
 983                         result = FMT_BC3;
 984                         goto out_word4;
 985                 default:
 986                         goto out_unknown;
 987                 }
 988         }
 989
 990         if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
 991                 result = FMT_5_9_9_9_SHAREDEXP;
 992                 goto out_word4;
 993         } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 994                 result = FMT_10_11_11_FLOAT;
 995                 goto out_word4;
 996         }
 997
 998
 999         for (i = 0; i < desc->nr_channels; i++) {
1000                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1001                         word4 |= sign_bit[i];
1002                 }
1003         }
1004
1005         /* R8G8Bx_SNORM - TODO CxV8U8 */
1006
1007         /* See whether the components are of the same size. */
1008         for (i = 1; i < desc->nr_channels; i++) {
1009                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1010         }
1011
1012         /* Non-uniform formats. */
1013         if (!uniform) {
1014                 switch(desc->nr_channels) {
1015                 case 3:
1016                         if (desc->channel[0].size == 5 &&
1017                             desc->channel[1].size == 6 &&
1018                             desc->channel[2].size == 5) {
1019                                 result = FMT_5_6_5;
1020                                 goto out_word4;
1021                         }
1022                         goto out_unknown;
1023                 case 4:
1024                         if (desc->channel[0].size == 5 &&
1025                             desc->channel[1].size == 5 &&
1026                             desc->channel[2].size == 5 &&
1027                             desc->channel[3].size == 1) {
1028                                 result = FMT_1_5_5_5;
1029                                 goto out_word4;
1030                         }
1031                         if (desc->channel[0].size == 10 &&
1032                             desc->channel[1].size == 10 &&
1033                             desc->channel[2].size == 10 &&
1034                             desc->channel[3].size == 2) {
1035                                 result = FMT_2_10_10_10;
1036                                 goto out_word4;
1037                         }
1038                         goto out_unknown;
1039                 }
1040                 goto out_unknown;
1041         }
1042
1043         /* Find the first non-VOID channel. */
1044         for (i = 0; i < 4; i++) {
1045                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1046                         break;
1047                 }
1048         }
1049
1050         if (i == 4)
1051                 goto out_unknown;
1052
1053         /* uniform formats */
1054         switch (desc->channel[i].type) {
1055         case UTIL_FORMAT_TYPE_UNSIGNED:
1056         case UTIL_FORMAT_TYPE_SIGNED:
1057 #if 0
1058                 if (!desc->channel[i].normalized &&
1059                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1060                         goto out_unknown;
1061                 }
1062 #endif
1063                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1064                     desc->channel[i].pure_integer)
1065                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1066
1067                 switch (desc->channel[i].size) {
1068                 case 4:
1069                         switch (desc->nr_channels) {
1070                         case 2:
1071                                 result = FMT_4_4;
1072                                 goto out_word4;
1073                         case 4:
1074                                 result = FMT_4_4_4_4;
1075                                 goto out_word4;
1076                         }
1077                         goto out_unknown;
1078                 case 8:
1079                         switch (desc->nr_channels) {
1080                         case 1:
1081                                 result = FMT_8;
1082                                 goto out_word4;
1083                         case 2:
1084                                 result = FMT_8_8;
1085                                 goto out_word4;
1086                         case 4:
1087                                 result = FMT_8_8_8_8;
1088                                 goto out_word4;
1089                         }
1090                         goto out_unknown;
1091                 case 16:
1092                         switch (desc->nr_channels) {
1093                         case 1:
1094                                 result = FMT_16;
1095                                 goto out_word4;
1096                         case 2:
1097                                 result = FMT_16_16;
1098                                 goto out_word4;
1099                         case 4:
1100                                 result = FMT_16_16_16_16;
1101                                 goto out_word4;
1102                         }
1103                         goto out_unknown;
1104                 case 32:
1105                         switch (desc->nr_channels) {
1106                         case 1:
1107                                 result = FMT_32;
1108                                 goto out_word4;
1109                         case 2:
1110                                 result = FMT_32_32;
1111                                 goto out_word4;
1112                         case 4:
1113                                 result = FMT_32_32_32_32;
1114                                 goto out_word4;
1115                         }
1116                 }
1117                 goto out_unknown;
1118
1119         case UTIL_FORMAT_TYPE_FLOAT:
1120                 switch (desc->channel[i].size) {
1121                 case 16:
1122                         switch (desc->nr_channels) {
1123                         case 1:
1124                                 result = FMT_16_FLOAT;
1125                                 goto out_word4;
1126                         case 2:
1127                                 result = FMT_16_16_FLOAT;
1128                                 goto out_word4;
1129                         case 4:
1130                                 result = FMT_16_16_16_16_FLOAT;
1131                                 goto out_word4;
1132                         }
1133                         goto out_unknown;
1134                 case 32:
1135                         switch (desc->nr_channels) {
1136                         case 1:
1137                                 result = FMT_32_FLOAT;
1138                                 goto out_word4;
1139                         case 2:
1140                                 result = FMT_32_32_FLOAT;
1141                                 goto out_word4;
1142                         case 4:
1143                                 result = FMT_32_32_32_32_FLOAT;
1144                                 goto out_word4;
1145                         }
1146                 }
1147                 goto out_unknown;
1148         }
1149
1150 out_word4:
1151         if (word4_p)
1152                 *word4_p = word4;
1153         if (yuv_format_p)
1154                 *yuv_format_p = yuv_format;
1155         return result;
1156 out_unknown:
1157         /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1158         return ~0;
1159 }