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[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
36 {
37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
38 struct pipe_resource *texture = transfer->resource;
39
40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b,
41 0, 0, 0, 0, texture, transfer->level,
42 &transfer->box);
43 }
44
45
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
48 {
49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
50 struct pipe_resource *texture = transfer->resource;
51 struct pipe_box sbox;
52
53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
54
55 ctx->resource_copy_region(ctx, texture, transfer->level,
56 transfer->box.x, transfer->box.y, transfer->box.z,
57 &rtransfer->staging->b.b,
58 0, &sbox);
59 }
60
61 unsigned r600_texture_get_offset(struct r600_texture *rtex,
62 unsigned level, unsigned layer)
63 {
64 return rtex->surface.level[level].offset +
65 layer * rtex->surface.level[level].slice_size;
66 }
67
68 static int r600_init_surface(struct r600_screen *rscreen,
69 struct radeon_surface *surface,
70 const struct pipe_resource *ptex,
71 unsigned array_mode,
72 bool is_transfer, bool is_flushed_depth)
73 {
74 const struct util_format_description *desc =
75 util_format_description(ptex->format);
76 bool is_depth, is_stencil;
77
78 is_depth = util_format_has_depth(desc);
79 is_stencil = util_format_has_stencil(desc);
80
81 surface->npix_x = ptex->width0;
82 surface->npix_y = ptex->height0;
83 surface->npix_z = ptex->depth0;
84 surface->blk_w = util_format_get_blockwidth(ptex->format);
85 surface->blk_h = util_format_get_blockheight(ptex->format);
86 surface->blk_d = 1;
87 surface->array_size = 1;
88 surface->last_level = ptex->last_level;
89
90 if (rscreen->chip_class >= EVERGREEN &&
91 !is_transfer && !is_flushed_depth &&
92 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
93 surface->bpe = 4; /* stencil is allocated separately on evergreen */
94 } else {
95 surface->bpe = util_format_get_blocksize(ptex->format);
96 /* align byte per element on dword */
97 if (surface->bpe == 3) {
98 surface->bpe = 4;
99 }
100 }
101
102 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
103 surface->flags = 0;
104
105 switch (array_mode) {
106 case V_038000_ARRAY_1D_TILED_THIN1:
107 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
108 break;
109 case V_038000_ARRAY_2D_TILED_THIN1:
110 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
111 break;
112 case V_038000_ARRAY_LINEAR_ALIGNED:
113 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
114 break;
115 case V_038000_ARRAY_LINEAR_GENERAL:
116 default:
117 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
118 break;
119 }
120 switch (ptex->target) {
121 case PIPE_TEXTURE_1D:
122 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
123 break;
124 case PIPE_TEXTURE_RECT:
125 case PIPE_TEXTURE_2D:
126 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
127 break;
128 case PIPE_TEXTURE_3D:
129 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
130 break;
131 case PIPE_TEXTURE_1D_ARRAY:
132 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
133 surface->array_size = ptex->array_size;
134 break;
135 case PIPE_TEXTURE_2D_ARRAY:
136 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
137 surface->array_size = ptex->array_size;
138 break;
139 case PIPE_TEXTURE_CUBE:
140 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
141 break;
142 case PIPE_BUFFER:
143 default:
144 return -EINVAL;
145 }
146 if (ptex->bind & PIPE_BIND_SCANOUT) {
147 surface->flags |= RADEON_SURF_SCANOUT;
148 }
149
150 if (!is_transfer && !is_flushed_depth && is_depth) {
151 surface->flags |= RADEON_SURF_ZBUFFER;
152
153 if (is_stencil) {
154 surface->flags |= RADEON_SURF_SBUFFER;
155 }
156 }
157 return 0;
158 }
159
160 static int r600_setup_surface(struct pipe_screen *screen,
161 struct r600_texture *rtex,
162 unsigned pitch_in_bytes_override)
163 {
164 struct pipe_resource *ptex = &rtex->resource.b.b;
165 struct r600_screen *rscreen = (struct r600_screen*)screen;
166 unsigned i;
167 int r;
168
169 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
170 if (r) {
171 return r;
172 }
173 rtex->size = rtex->surface.bo_size;
174 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
175 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
176 * for those
177 */
178 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
179 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
180 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
181 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
182 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
183 }
184 }
185 for (i = 0; i <= ptex->last_level; i++) {
186 switch (rtex->surface.level[i].mode) {
187 case RADEON_SURF_MODE_LINEAR_ALIGNED:
188 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
189 break;
190 case RADEON_SURF_MODE_1D:
191 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
192 break;
193 case RADEON_SURF_MODE_2D:
194 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
195 break;
196 default:
197 case RADEON_SURF_MODE_LINEAR:
198 rtex->array_mode[i] = 0;
199 break;
200 }
201 }
202 return 0;
203 }
204
205 static boolean r600_texture_get_handle(struct pipe_screen* screen,
206 struct pipe_resource *ptex,
207 struct winsys_handle *whandle)
208 {
209 struct r600_texture *rtex = (struct r600_texture*)ptex;
210 struct r600_resource *resource = &rtex->resource;
211 struct radeon_surface *surface = &rtex->surface;
212 struct r600_screen *rscreen = (struct r600_screen*)screen;
213
214 rscreen->ws->buffer_set_tiling(resource->buf,
215 NULL,
216 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
217 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
218 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
219 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
220 surface->bankw, surface->bankh,
221 surface->tile_split,
222 surface->stencil_tile_split,
223 surface->mtilea,
224 rtex->surface.level[0].pitch_bytes);
225
226 return rscreen->ws->buffer_get_handle(resource->buf,
227 rtex->surface.level[0].pitch_bytes, whandle);
228 }
229
230 static void r600_texture_destroy(struct pipe_screen *screen,
231 struct pipe_resource *ptex)
232 {
233 struct r600_texture *rtex = (struct r600_texture*)ptex;
234 struct r600_resource *resource = &rtex->resource;
235
236 if (rtex->flushed_depth_texture)
237 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
238
239 pb_reference(&resource->buf, NULL);
240 FREE(rtex);
241 }
242
243 static const struct u_resource_vtbl r600_texture_vtbl =
244 {
245 r600_texture_get_handle, /* get_handle */
246 r600_texture_destroy, /* resource_destroy */
247 r600_texture_get_transfer, /* get_transfer */
248 r600_texture_transfer_destroy, /* transfer_destroy */
249 r600_texture_transfer_map, /* transfer_map */
250 NULL, /* transfer_flush_region */
251 r600_texture_transfer_unmap, /* transfer_unmap */
252 NULL /* transfer_inline_write */
253 };
254
255 static struct r600_texture *
256 r600_texture_create_object(struct pipe_screen *screen,
257 const struct pipe_resource *base,
258 unsigned pitch_in_bytes_override,
259 struct pb_buffer *buf,
260 boolean alloc_bo,
261 struct radeon_surface *surface)
262 {
263 struct r600_texture *rtex;
264 struct r600_resource *resource;
265 struct r600_screen *rscreen = (struct r600_screen*)screen;
266 int r;
267
268 rtex = CALLOC_STRUCT(r600_texture);
269 if (rtex == NULL)
270 return NULL;
271
272 resource = &rtex->resource;
273 resource->b.b = *base;
274 resource->b.vtbl = &r600_texture_vtbl;
275 pipe_reference_init(&resource->b.b.reference, 1);
276 resource->b.b.screen = screen;
277 rtex->pitch_override = pitch_in_bytes_override;
278
279 /* don't include stencil-only formats which we don't support for rendering */
280 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
281
282 rtex->surface = *surface;
283 r = r600_setup_surface(screen, rtex,
284 pitch_in_bytes_override);
285 if (r) {
286 FREE(rtex);
287 return NULL;
288 }
289
290 /* Now create the backing buffer. */
291 if (!buf && alloc_bo) {
292 unsigned base_align = rtex->surface.bo_alignment;
293 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
294
295 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, usage)) {
296 FREE(rtex);
297 return NULL;
298 }
299 } else if (buf) {
300 resource->buf = buf;
301 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
302 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
303 }
304 return rtex;
305 }
306
307 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
308 const struct pipe_resource *templ)
309 {
310 struct r600_screen *rscreen = (struct r600_screen*)screen;
311 struct radeon_surface surface;
312 unsigned array_mode = 0;
313 int r;
314
315 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) {
316 if (!(templ->bind & PIPE_BIND_SCANOUT) &&
317 templ->usage != PIPE_USAGE_STAGING &&
318 templ->usage != PIPE_USAGE_STREAM) {
319 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
320 } else if (util_format_is_compressed(templ->format)) {
321 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
322 }
323 }
324
325 /* XXX tiling is broken for the 422 formats */
326 if (util_format_description(templ->format)->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
327 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
328
329 r = r600_init_surface(rscreen, &surface, templ, array_mode,
330 templ->flags & R600_RESOURCE_FLAG_TRANSFER,
331 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
332 if (r) {
333 return NULL;
334 }
335 r = rscreen->ws->surface_best(rscreen->ws, &surface);
336 if (r) {
337 return NULL;
338 }
339 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
340 0, NULL, TRUE, &surface);
341 }
342
343 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
344 struct pipe_resource *texture,
345 const struct pipe_surface *templ)
346 {
347 struct r600_texture *rtex = (struct r600_texture*)texture;
348 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
349 unsigned level = templ->u.tex.level;
350
351 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
352 if (surface == NULL)
353 return NULL;
354 pipe_reference_init(&surface->base.reference, 1);
355 pipe_resource_reference(&surface->base.texture, texture);
356 surface->base.context = pipe;
357 surface->base.format = templ->format;
358 surface->base.width = rtex->surface.level[level].npix_x;
359 surface->base.height = rtex->surface.level[level].npix_y;
360 surface->base.usage = templ->usage;
361 surface->base.u = templ->u;
362 return &surface->base;
363 }
364
365 static void r600_surface_destroy(struct pipe_context *pipe,
366 struct pipe_surface *surface)
367 {
368 pipe_resource_reference(&surface->texture, NULL);
369 FREE(surface);
370 }
371
372 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
373 const struct pipe_resource *templ,
374 struct winsys_handle *whandle)
375 {
376 struct r600_screen *rscreen = (struct r600_screen*)screen;
377 struct pb_buffer *buf = NULL;
378 unsigned stride = 0;
379 unsigned array_mode = 0;
380 enum radeon_bo_layout micro, macro;
381 struct radeon_surface surface;
382 int r;
383
384 /* Support only 2D textures without mipmaps */
385 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
386 templ->depth0 != 1 || templ->last_level != 0)
387 return NULL;
388
389 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
390 if (!buf)
391 return NULL;
392
393 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
394 &surface.bankw, &surface.bankh,
395 &surface.tile_split,
396 &surface.stencil_tile_split,
397 &surface.mtilea);
398
399 if (macro == RADEON_LAYOUT_TILED)
400 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
401 else if (micro == RADEON_LAYOUT_TILED)
402 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
403 else
404 array_mode = 0;
405
406 r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false);
407 if (r) {
408 return NULL;
409 }
410 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
411 stride, buf, FALSE, &surface);
412 }
413
414 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
415 struct pipe_resource *texture,
416 struct r600_texture **staging)
417 {
418 struct r600_texture *rtex = (struct r600_texture*)texture;
419 struct pipe_resource resource;
420 struct r600_texture **flushed_depth_texture = staging ?
421 staging : &rtex->flushed_depth_texture;
422
423 if (!staging && rtex->flushed_depth_texture)
424 return true; /* it's ready */
425
426 resource.target = texture->target;
427 resource.format = texture->format;
428 resource.width0 = texture->width0;
429 resource.height0 = texture->height0;
430 resource.depth0 = texture->depth0;
431 resource.array_size = texture->array_size;
432 resource.last_level = texture->last_level;
433 resource.nr_samples = texture->nr_samples;
434 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
435 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
436 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
437
438 if (staging)
439 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
440
441 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
442 if (*flushed_depth_texture == NULL) {
443 R600_ERR("failed to create temporary texture to hold flushed depth\n");
444 return false;
445 }
446
447 (*flushed_depth_texture)->is_flushing_texture = TRUE;
448 return true;
449 }
450
451 /* Needs adjustment for pixelformat:
452 */
453 static INLINE unsigned u_box_volume( const struct pipe_box *box )
454 {
455 return box->width * box->depth * box->height;
456 }
457
458 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
459 struct pipe_resource *texture,
460 unsigned level,
461 unsigned usage,
462 const struct pipe_box *box)
463 {
464 struct r600_context *rctx = (struct r600_context*)ctx;
465 struct r600_texture *rtex = (struct r600_texture*)texture;
466 struct pipe_resource resource;
467 struct r600_transfer *trans;
468 boolean use_staging_texture = FALSE;
469
470 /* We cannot map a tiled texture directly because the data is
471 * in a different order, therefore we do detiling using a blit.
472 *
473 * Also, use a temporary in GTT memory for read transfers, as
474 * the CPU is much happier reading out of cached system memory
475 * than uncached VRAM.
476 */
477 if (R600_TEX_IS_TILED(rtex, level)) {
478 use_staging_texture = TRUE;
479 }
480
481 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
482 use_staging_texture = TRUE;
483
484 /* Use a staging texture for uploads if the underlying BO is busy. */
485 if (!(usage & PIPE_TRANSFER_READ) &&
486 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
487 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
488 use_staging_texture = TRUE;
489 }
490
491 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
492 use_staging_texture = FALSE;
493 }
494
495 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
496 return NULL;
497 }
498
499 trans = CALLOC_STRUCT(r600_transfer);
500 if (trans == NULL)
501 return NULL;
502 pipe_resource_reference(&trans->transfer.resource, texture);
503 trans->transfer.level = level;
504 trans->transfer.usage = usage;
505 trans->transfer.box = *box;
506 if (rtex->is_depth) {
507 /* XXX: only readback the rectangle which is being mapped?
508 */
509 /* XXX: when discard is true, no need to read back from depth texture
510 */
511 struct r600_texture *staging_depth;
512
513 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
514 R600_ERR("failed to create temporary texture to hold untiled copy\n");
515 pipe_resource_reference(&trans->transfer.resource, NULL);
516 FREE(trans);
517 return NULL;
518 }
519
520 r600_blit_uncompress_depth(ctx, rtex, staging_depth,
521 level, level,
522 box->z, box->z + box->depth - 1,
523 0, 0);
524
525 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
526 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
527 trans->staging = (struct r600_resource*)staging_depth;
528 return &trans->transfer;
529 } else if (use_staging_texture) {
530 resource.target = PIPE_TEXTURE_2D;
531 resource.format = texture->format;
532 resource.width0 = box->width;
533 resource.height0 = box->height;
534 resource.depth0 = 1;
535 resource.array_size = 1;
536 resource.last_level = 0;
537 resource.nr_samples = 0;
538 resource.usage = PIPE_USAGE_STAGING;
539 resource.bind = 0;
540 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
541 /* For texture reading, the temporary (detiled) texture is used as
542 * a render target when blitting from a tiled texture. */
543 if (usage & PIPE_TRANSFER_READ) {
544 resource.bind |= PIPE_BIND_RENDER_TARGET;
545 }
546 /* For texture writing, the temporary texture is used as a sampler
547 * when blitting into a tiled texture. */
548 if (usage & PIPE_TRANSFER_WRITE) {
549 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
550 }
551 /* Create the temporary texture. */
552 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
553 if (trans->staging == NULL) {
554 R600_ERR("failed to create temporary texture to hold untiled copy\n");
555 pipe_resource_reference(&trans->transfer.resource, NULL);
556 FREE(trans);
557 return NULL;
558 }
559
560 trans->transfer.stride =
561 ((struct r600_texture *)trans->staging)->surface.level[0].pitch_bytes;
562 if (usage & PIPE_TRANSFER_READ) {
563 r600_copy_to_staging_texture(ctx, trans);
564 /* Always referenced in the blit. */
565 r600_flush(ctx, NULL, 0);
566 }
567 return &trans->transfer;
568 }
569 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
570 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
571 trans->offset = r600_texture_get_offset(rtex, level, box->z);
572 return &trans->transfer;
573 }
574
575 void r600_texture_transfer_destroy(struct pipe_context *ctx,
576 struct pipe_transfer *transfer)
577 {
578 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
579 struct pipe_resource *texture = transfer->resource;
580 struct r600_texture *rtex = (struct r600_texture*)texture;
581
582 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
583 if (rtex->is_depth) {
584 ctx->resource_copy_region(ctx, texture, transfer->level,
585 transfer->box.x, transfer->box.y, transfer->box.z,
586 &rtransfer->staging->b.b, transfer->level,
587 &transfer->box);
588 } else {
589 r600_copy_from_staging_texture(ctx, rtransfer);
590 }
591 }
592
593 if (rtransfer->staging)
594 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
595
596 pipe_resource_reference(&transfer->resource, NULL);
597 FREE(transfer);
598 }
599
600 void* r600_texture_transfer_map(struct pipe_context *ctx,
601 struct pipe_transfer* transfer)
602 {
603 struct r600_context *rctx = (struct r600_context *)ctx;
604 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
605 struct radeon_winsys_cs_handle *buf;
606 struct r600_texture *rtex =
607 (struct r600_texture*)transfer->resource;
608 enum pipe_format format = transfer->resource->format;
609 unsigned offset = 0;
610 char *map;
611
612 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
613 return r600_compute_global_transfer_map(ctx, transfer);
614 }
615
616 if (rtransfer->staging) {
617 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
618 } else {
619 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
620 }
621
622 if (rtex->is_depth || !rtransfer->staging)
623 offset = rtransfer->offset +
624 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
625 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
626
627 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
628 return NULL;
629 }
630
631 return map + offset;
632 }
633
634 void r600_texture_transfer_unmap(struct pipe_context *ctx,
635 struct pipe_transfer* transfer)
636 {
637 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
638 struct r600_context *rctx = (struct r600_context*)ctx;
639 struct radeon_winsys_cs_handle *buf;
640
641 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
642 return r600_compute_global_transfer_unmap(ctx, transfer);
643 }
644
645 if (rtransfer->staging) {
646 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
647 } else {
648 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
649 }
650 rctx->ws->buffer_unmap(buf);
651 }
652
653 void r600_init_surface_functions(struct r600_context *r600)
654 {
655 r600->context.create_surface = r600_create_surface;
656 r600->context.surface_destroy = r600_surface_destroy;
657 }
658
659 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
660 const unsigned char *swizzle_view)
661 {
662 unsigned i;
663 unsigned char swizzle[4];
664 unsigned result = 0;
665 const uint32_t swizzle_shift[4] = {
666 16, 19, 22, 25,
667 };
668 const uint32_t swizzle_bit[4] = {
669 0, 1, 2, 3,
670 };
671
672 if (swizzle_view) {
673 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
674 } else {
675 memcpy(swizzle, swizzle_format, 4);
676 }
677
678 /* Get swizzle. */
679 for (i = 0; i < 4; i++) {
680 switch (swizzle[i]) {
681 case UTIL_FORMAT_SWIZZLE_Y:
682 result |= swizzle_bit[1] << swizzle_shift[i];
683 break;
684 case UTIL_FORMAT_SWIZZLE_Z:
685 result |= swizzle_bit[2] << swizzle_shift[i];
686 break;
687 case UTIL_FORMAT_SWIZZLE_W:
688 result |= swizzle_bit[3] << swizzle_shift[i];
689 break;
690 case UTIL_FORMAT_SWIZZLE_0:
691 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
692 break;
693 case UTIL_FORMAT_SWIZZLE_1:
694 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
695 break;
696 default: /* UTIL_FORMAT_SWIZZLE_X */
697 result |= swizzle_bit[0] << swizzle_shift[i];
698 }
699 }
700 return result;
701 }
702
703 /* texture format translate */
704 uint32_t r600_translate_texformat(struct pipe_screen *screen,
705 enum pipe_format format,
706 const unsigned char *swizzle_view,
707 uint32_t *word4_p, uint32_t *yuv_format_p)
708 {
709 uint32_t result = 0, word4 = 0, yuv_format = 0;
710 const struct util_format_description *desc;
711 boolean uniform = TRUE;
712 static int r600_enable_s3tc = -1;
713 bool is_srgb_valid = FALSE;
714
715 int i;
716 const uint32_t sign_bit[4] = {
717 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
718 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
719 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
720 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
721 };
722 desc = util_format_description(format);
723
724 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
725
726 /* Colorspace (return non-RGB formats directly). */
727 switch (desc->colorspace) {
728 /* Depth stencil formats */
729 case UTIL_FORMAT_COLORSPACE_ZS:
730 switch (format) {
731 case PIPE_FORMAT_Z16_UNORM:
732 result = FMT_16;
733 goto out_word4;
734 case PIPE_FORMAT_X24S8_UINT:
735 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
736 case PIPE_FORMAT_Z24X8_UNORM:
737 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
738 result = FMT_8_24;
739 goto out_word4;
740 case PIPE_FORMAT_S8X24_UINT:
741 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
742 case PIPE_FORMAT_X8Z24_UNORM:
743 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
744 result = FMT_24_8;
745 goto out_word4;
746 case PIPE_FORMAT_S8_UINT:
747 result = FMT_8;
748 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
749 goto out_word4;
750 case PIPE_FORMAT_Z32_FLOAT:
751 result = FMT_32_FLOAT;
752 goto out_word4;
753 case PIPE_FORMAT_X32_S8X24_UINT:
754 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
755 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
756 result = FMT_X24_8_32_FLOAT;
757 goto out_word4;
758 default:
759 goto out_unknown;
760 }
761
762 case UTIL_FORMAT_COLORSPACE_YUV:
763 yuv_format |= (1 << 30);
764 switch (format) {
765 case PIPE_FORMAT_UYVY:
766 case PIPE_FORMAT_YUYV:
767 default:
768 break;
769 }
770 goto out_unknown; /* XXX */
771
772 case UTIL_FORMAT_COLORSPACE_SRGB:
773 word4 |= S_038010_FORCE_DEGAMMA(1);
774 break;
775
776 default:
777 break;
778 }
779
780 if (r600_enable_s3tc == -1) {
781 struct r600_screen *rscreen = (struct r600_screen *)screen;
782 if (rscreen->info.drm_minor >= 9)
783 r600_enable_s3tc = 1;
784 else
785 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
786 }
787
788 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
789 if (!r600_enable_s3tc)
790 goto out_unknown;
791
792 switch (format) {
793 case PIPE_FORMAT_RGTC1_SNORM:
794 case PIPE_FORMAT_LATC1_SNORM:
795 word4 |= sign_bit[0];
796 case PIPE_FORMAT_RGTC1_UNORM:
797 case PIPE_FORMAT_LATC1_UNORM:
798 result = FMT_BC4;
799 goto out_word4;
800 case PIPE_FORMAT_RGTC2_SNORM:
801 case PIPE_FORMAT_LATC2_SNORM:
802 word4 |= sign_bit[0] | sign_bit[1];
803 case PIPE_FORMAT_RGTC2_UNORM:
804 case PIPE_FORMAT_LATC2_UNORM:
805 result = FMT_BC5;
806 goto out_word4;
807 default:
808 goto out_unknown;
809 }
810 }
811
812 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
813
814 if (!r600_enable_s3tc)
815 goto out_unknown;
816
817 if (!util_format_s3tc_enabled) {
818 goto out_unknown;
819 }
820
821 switch (format) {
822 case PIPE_FORMAT_DXT1_RGB:
823 case PIPE_FORMAT_DXT1_RGBA:
824 case PIPE_FORMAT_DXT1_SRGB:
825 case PIPE_FORMAT_DXT1_SRGBA:
826 result = FMT_BC1;
827 is_srgb_valid = TRUE;
828 goto out_word4;
829 case PIPE_FORMAT_DXT3_RGBA:
830 case PIPE_FORMAT_DXT3_SRGBA:
831 result = FMT_BC2;
832 is_srgb_valid = TRUE;
833 goto out_word4;
834 case PIPE_FORMAT_DXT5_RGBA:
835 case PIPE_FORMAT_DXT5_SRGBA:
836 result = FMT_BC3;
837 is_srgb_valid = TRUE;
838 goto out_word4;
839 default:
840 goto out_unknown;
841 }
842 }
843
844 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
845 switch (format) {
846 case PIPE_FORMAT_R8G8_B8G8_UNORM:
847 case PIPE_FORMAT_G8R8_B8R8_UNORM:
848 result = FMT_GB_GR;
849 goto out_word4;
850 case PIPE_FORMAT_G8R8_G8B8_UNORM:
851 case PIPE_FORMAT_R8G8_R8B8_UNORM:
852 result = FMT_BG_RG;
853 goto out_word4;
854 default:
855 goto out_unknown;
856 }
857 }
858
859 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
860 result = FMT_5_9_9_9_SHAREDEXP;
861 goto out_word4;
862 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
863 result = FMT_10_11_11_FLOAT;
864 goto out_word4;
865 }
866
867
868 for (i = 0; i < desc->nr_channels; i++) {
869 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
870 word4 |= sign_bit[i];
871 }
872 }
873
874 /* R8G8Bx_SNORM - XXX CxV8U8 */
875
876 /* See whether the components are of the same size. */
877 for (i = 1; i < desc->nr_channels; i++) {
878 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
879 }
880
881 /* Non-uniform formats. */
882 if (!uniform) {
883 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
884 desc->channel[0].pure_integer)
885 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
886 switch(desc->nr_channels) {
887 case 3:
888 if (desc->channel[0].size == 5 &&
889 desc->channel[1].size == 6 &&
890 desc->channel[2].size == 5) {
891 result = FMT_5_6_5;
892 goto out_word4;
893 }
894 goto out_unknown;
895 case 4:
896 if (desc->channel[0].size == 5 &&
897 desc->channel[1].size == 5 &&
898 desc->channel[2].size == 5 &&
899 desc->channel[3].size == 1) {
900 result = FMT_1_5_5_5;
901 goto out_word4;
902 }
903 if (desc->channel[0].size == 10 &&
904 desc->channel[1].size == 10 &&
905 desc->channel[2].size == 10 &&
906 desc->channel[3].size == 2) {
907 result = FMT_2_10_10_10;
908 goto out_word4;
909 }
910 goto out_unknown;
911 }
912 goto out_unknown;
913 }
914
915 /* Find the first non-VOID channel. */
916 for (i = 0; i < 4; i++) {
917 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
918 break;
919 }
920 }
921
922 if (i == 4)
923 goto out_unknown;
924
925 /* uniform formats */
926 switch (desc->channel[i].type) {
927 case UTIL_FORMAT_TYPE_UNSIGNED:
928 case UTIL_FORMAT_TYPE_SIGNED:
929 #if 0
930 if (!desc->channel[i].normalized &&
931 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
932 goto out_unknown;
933 }
934 #endif
935 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
936 desc->channel[i].pure_integer)
937 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
938
939 switch (desc->channel[i].size) {
940 case 4:
941 switch (desc->nr_channels) {
942 case 2:
943 result = FMT_4_4;
944 goto out_word4;
945 case 4:
946 result = FMT_4_4_4_4;
947 goto out_word4;
948 }
949 goto out_unknown;
950 case 8:
951 switch (desc->nr_channels) {
952 case 1:
953 result = FMT_8;
954 goto out_word4;
955 case 2:
956 result = FMT_8_8;
957 goto out_word4;
958 case 4:
959 result = FMT_8_8_8_8;
960 is_srgb_valid = TRUE;
961 goto out_word4;
962 }
963 goto out_unknown;
964 case 16:
965 switch (desc->nr_channels) {
966 case 1:
967 result = FMT_16;
968 goto out_word4;
969 case 2:
970 result = FMT_16_16;
971 goto out_word4;
972 case 4:
973 result = FMT_16_16_16_16;
974 goto out_word4;
975 }
976 goto out_unknown;
977 case 32:
978 switch (desc->nr_channels) {
979 case 1:
980 result = FMT_32;
981 goto out_word4;
982 case 2:
983 result = FMT_32_32;
984 goto out_word4;
985 case 4:
986 result = FMT_32_32_32_32;
987 goto out_word4;
988 }
989 }
990 goto out_unknown;
991
992 case UTIL_FORMAT_TYPE_FLOAT:
993 switch (desc->channel[i].size) {
994 case 16:
995 switch (desc->nr_channels) {
996 case 1:
997 result = FMT_16_FLOAT;
998 goto out_word4;
999 case 2:
1000 result = FMT_16_16_FLOAT;
1001 goto out_word4;
1002 case 4:
1003 result = FMT_16_16_16_16_FLOAT;
1004 goto out_word4;
1005 }
1006 goto out_unknown;
1007 case 32:
1008 switch (desc->nr_channels) {
1009 case 1:
1010 result = FMT_32_FLOAT;
1011 goto out_word4;
1012 case 2:
1013 result = FMT_32_32_FLOAT;
1014 goto out_word4;
1015 case 4:
1016 result = FMT_32_32_32_32_FLOAT;
1017 goto out_word4;
1018 }
1019 }
1020 goto out_unknown;
1021 }
1022
1023 out_word4:
1024
1025 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1026 return ~0;
1027 if (word4_p)
1028 *word4_p = word4;
1029 if (yuv_format_p)
1030 *yuv_format_p = yuv_format;
1031 return result;
1032 out_unknown:
1033 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1034 return ~0;
1035 }