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r600g: do fine-grained depth texture flushing
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
36 {
37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
38 struct pipe_resource *texture = transfer->resource;
39
40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b,
41 0, 0, 0, 0, texture, transfer->level,
42 &transfer->box);
43 }
44
45
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
48 {
49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
50 struct pipe_resource *texture = transfer->resource;
51 struct pipe_box sbox;
52
53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
54
55 ctx->resource_copy_region(ctx, texture, transfer->level,
56 transfer->box.x, transfer->box.y, transfer->box.z,
57 &rtransfer->staging->b.b,
58 0, &sbox);
59 }
60
61 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
62 unsigned level, unsigned layer)
63 {
64 unsigned offset = rtex->offset[level];
65
66 switch (rtex->resource.b.b.target) {
67 case PIPE_TEXTURE_3D:
68 case PIPE_TEXTURE_CUBE:
69 default:
70 return offset + layer * rtex->layer_size[level];
71 }
72 }
73
74 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
75 enum pipe_format format,
76 unsigned array_mode)
77 {
78 struct r600_screen* rscreen = (struct r600_screen *)screen;
79 unsigned pixsize = util_format_get_blocksize(format);
80 int p_align;
81
82 switch(array_mode) {
83 case V_038000_ARRAY_1D_TILED_THIN1:
84 p_align = MAX2(8,
85 ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
86 break;
87 case V_038000_ARRAY_2D_TILED_THIN1:
88 p_align = MAX2(rscreen->tiling_info.num_banks,
89 (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
90 rscreen->tiling_info.num_banks)) * 8;
91 break;
92 case V_038000_ARRAY_LINEAR_ALIGNED:
93 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
94 break;
95 case V_038000_ARRAY_LINEAR_GENERAL:
96 default:
97 p_align = rscreen->tiling_info.group_bytes / pixsize;
98 break;
99 }
100 return p_align;
101 }
102
103 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
104 unsigned array_mode)
105 {
106 struct r600_screen* rscreen = (struct r600_screen *)screen;
107 int h_align;
108
109 switch (array_mode) {
110 case V_038000_ARRAY_2D_TILED_THIN1:
111 h_align = rscreen->tiling_info.num_channels * 8;
112 break;
113 case V_038000_ARRAY_1D_TILED_THIN1:
114 case V_038000_ARRAY_LINEAR_ALIGNED:
115 h_align = 8;
116 break;
117 case V_038000_ARRAY_LINEAR_GENERAL:
118 default:
119 h_align = 1;
120 break;
121 }
122 return h_align;
123 }
124
125 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
126 enum pipe_format format,
127 unsigned array_mode)
128 {
129 struct r600_screen* rscreen = (struct r600_screen *)screen;
130 unsigned pixsize = util_format_get_blocksize(format);
131 int p_align = r600_get_block_alignment(screen, format, array_mode);
132 int h_align = r600_get_height_alignment(screen, array_mode);
133 int b_align;
134
135 switch (array_mode) {
136 case V_038000_ARRAY_2D_TILED_THIN1:
137 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
138 p_align * pixsize * h_align);
139 break;
140 case V_038000_ARRAY_1D_TILED_THIN1:
141 case V_038000_ARRAY_LINEAR_ALIGNED:
142 case V_038000_ARRAY_LINEAR_GENERAL:
143 default:
144 b_align = rscreen->tiling_info.group_bytes;
145 break;
146 }
147 return b_align;
148 }
149
150 static unsigned mip_minify(unsigned size, unsigned level)
151 {
152 unsigned val;
153 val = u_minify(size, level);
154 if (level > 0)
155 val = util_next_power_of_two(val);
156 return val;
157 }
158
159 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
160 struct r600_resource_texture *rtex,
161 unsigned level)
162 {
163 struct pipe_resource *ptex = &rtex->resource.b.b;
164 unsigned nblocksx, block_align, width;
165 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
166
167 if (rtex->pitch_override)
168 return rtex->pitch_override / blocksize;
169
170 width = mip_minify(ptex->width0, level);
171 nblocksx = util_format_get_nblocksx(rtex->real_format, width);
172
173 block_align = r600_get_block_alignment(screen, rtex->real_format,
174 rtex->array_mode[level]);
175 nblocksx = align(nblocksx, block_align);
176 return nblocksx;
177 }
178
179 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
180 struct r600_resource_texture *rtex,
181 unsigned level)
182 {
183 struct pipe_resource *ptex = &rtex->resource.b.b;
184 unsigned height, tile_height;
185
186 height = mip_minify(ptex->height0, level);
187 height = util_format_get_nblocksy(rtex->real_format, height);
188 tile_height = r600_get_height_alignment(screen,
189 rtex->array_mode[level]);
190
191 /* XXX Hack around an alignment issue. Less tests fail with this.
192 *
193 * The thing is depth-stencil buffers should be tiled, i.e.
194 * the alignment should be >=8. If I make them tiled, stencil starts
195 * working because it no longer overlaps with the depth buffer
196 * in memory, but texturing like drawpix-stencil breaks. */
197 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
198 tile_height = 8;
199
200 height = align(height, tile_height);
201 return height;
202 }
203
204 static void r600_texture_set_array_mode(struct pipe_screen *screen,
205 struct r600_resource_texture *rtex,
206 unsigned level, unsigned array_mode)
207 {
208 struct pipe_resource *ptex = &rtex->resource.b.b;
209
210 switch (array_mode) {
211 case V_0280A0_ARRAY_LINEAR_GENERAL:
212 case V_0280A0_ARRAY_LINEAR_ALIGNED:
213 case V_0280A0_ARRAY_1D_TILED_THIN1:
214 default:
215 rtex->array_mode[level] = array_mode;
216 break;
217 case V_0280A0_ARRAY_2D_TILED_THIN1:
218 {
219 unsigned w, h, tile_height, tile_width;
220
221 tile_height = r600_get_height_alignment(screen, array_mode);
222 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
223
224 w = mip_minify(ptex->width0, level);
225 h = mip_minify(ptex->height0, level);
226 if (w <= tile_width || h <= tile_height)
227 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
228 else
229 rtex->array_mode[level] = array_mode;
230 }
231 break;
232 }
233 }
234
235 static int r600_init_surface(struct radeon_surface *surface,
236 const struct pipe_resource *ptex,
237 unsigned array_mode, bool is_transfer)
238 {
239 surface->npix_x = ptex->width0;
240 surface->npix_y = ptex->height0;
241 surface->npix_z = ptex->depth0;
242 surface->blk_w = util_format_get_blockwidth(ptex->format);
243 surface->blk_h = util_format_get_blockheight(ptex->format);
244 surface->blk_d = 1;
245 surface->array_size = 1;
246 surface->last_level = ptex->last_level;
247 surface->bpe = util_format_get_blocksize(ptex->format);
248 /* align byte per element on dword */
249 if (surface->bpe == 3) {
250 surface->bpe = 4;
251 }
252 surface->nsamples = 1;
253 surface->flags = 0;
254 switch (array_mode) {
255 case V_038000_ARRAY_1D_TILED_THIN1:
256 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
257 break;
258 case V_038000_ARRAY_2D_TILED_THIN1:
259 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
260 break;
261 case V_038000_ARRAY_LINEAR_ALIGNED:
262 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
263 break;
264 case V_038000_ARRAY_LINEAR_GENERAL:
265 default:
266 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
267 break;
268 }
269 switch (ptex->target) {
270 case PIPE_TEXTURE_1D:
271 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
272 break;
273 case PIPE_TEXTURE_RECT:
274 case PIPE_TEXTURE_2D:
275 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
276 break;
277 case PIPE_TEXTURE_3D:
278 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
279 break;
280 case PIPE_TEXTURE_1D_ARRAY:
281 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
282 surface->array_size = ptex->array_size;
283 break;
284 case PIPE_TEXTURE_2D_ARRAY:
285 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
286 surface->array_size = ptex->array_size;
287 break;
288 case PIPE_TEXTURE_CUBE:
289 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
290 break;
291 case PIPE_BUFFER:
292 default:
293 return -EINVAL;
294 }
295 if (ptex->bind & PIPE_BIND_SCANOUT) {
296 surface->flags |= RADEON_SURF_SCANOUT;
297 }
298 if ((ptex->bind & PIPE_BIND_DEPTH_STENCIL) &&
299 util_format_is_depth_and_stencil(ptex->format) && !is_transfer) {
300 surface->flags |= RADEON_SURF_ZBUFFER;
301 surface->flags |= RADEON_SURF_SBUFFER;
302 }
303
304 return 0;
305 }
306
307 static int r600_setup_surface(struct pipe_screen *screen,
308 struct r600_resource_texture *rtex,
309 unsigned array_mode,
310 unsigned pitch_in_bytes_override)
311 {
312 struct pipe_resource *ptex = &rtex->resource.b.b;
313 struct r600_screen *rscreen = (struct r600_screen*)screen;
314 unsigned i;
315 int r;
316
317 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
318 if (r) {
319 return r;
320 }
321 rtex->size = rtex->surface.bo_size;
322 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
323 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
324 * for those
325 */
326 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
327 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
328 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
329 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
330 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
331 }
332 }
333 for (i = 0; i <= ptex->last_level; i++) {
334 rtex->offset[i] = rtex->surface.level[i].offset;
335 rtex->layer_size[i] = rtex->surface.level[i].slice_size;
336 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
337 switch (rtex->surface.level[i].mode) {
338 case RADEON_SURF_MODE_LINEAR_ALIGNED:
339 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
340 break;
341 case RADEON_SURF_MODE_1D:
342 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
343 break;
344 case RADEON_SURF_MODE_2D:
345 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
346 break;
347 default:
348 case RADEON_SURF_MODE_LINEAR:
349 rtex->array_mode[i] = 0;
350 break;
351 }
352 }
353 return 0;
354 }
355
356 static void r600_setup_miptree(struct pipe_screen *screen,
357 struct r600_resource_texture *rtex,
358 unsigned array_mode)
359 {
360 struct pipe_resource *ptex = &rtex->resource.b.b;
361 enum chip_class chipc = ((struct r600_screen*)screen)->chip_class;
362 unsigned size, layer_size, i, offset;
363 unsigned nblocksx, nblocksy;
364
365 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
366 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
367 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
368
369 r600_texture_set_array_mode(screen, rtex, i, array_mode);
370
371 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
372 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
373
374 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL)
375 layer_size = align(nblocksx, 64) * nblocksy * blocksize;
376 else
377 layer_size = nblocksx * nblocksy * blocksize;
378
379 if (ptex->target == PIPE_TEXTURE_CUBE) {
380 if (chipc >= R700)
381 size = layer_size * 8;
382 else
383 size = layer_size * 6;
384 }
385 else if (ptex->target == PIPE_TEXTURE_3D)
386 size = layer_size * u_minify(ptex->depth0, i);
387 else
388 size = layer_size * ptex->array_size;
389
390 /* align base image and start of miptree */
391 if ((i == 0) || (i == 1))
392 offset = align(offset, base_align);
393 rtex->offset[i] = offset;
394 rtex->layer_size[i] = layer_size;
395 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
396 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
397
398 offset += size;
399 }
400 rtex->size = offset;
401 }
402
403 /* Figure out whether u_blitter will fallback to a transfer operation.
404 * If so, don't use a staging resource.
405 */
406 static boolean permit_hardware_blit(struct pipe_screen *screen,
407 const struct pipe_resource *res)
408 {
409 unsigned bind;
410
411 if (util_format_is_depth_or_stencil(res->format))
412 bind = PIPE_BIND_DEPTH_STENCIL;
413 else
414 bind = PIPE_BIND_RENDER_TARGET;
415
416 /* hackaround for S3TC */
417 if (util_format_is_compressed(res->format))
418 return TRUE;
419
420 if (!screen->is_format_supported(screen,
421 res->format,
422 res->target,
423 res->nr_samples,
424 bind))
425 return FALSE;
426
427 if (!screen->is_format_supported(screen,
428 res->format,
429 res->target,
430 res->nr_samples,
431 PIPE_BIND_SAMPLER_VIEW))
432 return FALSE;
433
434 return TRUE;
435 }
436
437 static boolean r600_texture_get_handle(struct pipe_screen* screen,
438 struct pipe_resource *ptex,
439 struct winsys_handle *whandle)
440 {
441 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
442 struct r600_resource *resource = &rtex->resource;
443 struct radeon_surface *surface = &rtex->surface;
444 struct r600_screen *rscreen = (struct r600_screen*)screen;
445
446 rscreen->ws->buffer_set_tiling(resource->buf,
447 NULL,
448 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
449 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
450 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
451 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
452 surface->bankw, surface->bankh,
453 surface->tile_split,
454 surface->stencil_tile_split,
455 surface->mtilea,
456 rtex->pitch_in_bytes[0]);
457
458 return rscreen->ws->buffer_get_handle(resource->buf,
459 rtex->pitch_in_bytes[0], whandle);
460 }
461
462 static void r600_texture_destroy(struct pipe_screen *screen,
463 struct pipe_resource *ptex)
464 {
465 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
466 struct r600_resource *resource = &rtex->resource;
467
468 if (rtex->flushed_depth_texture)
469 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
470
471 if (rtex->stencil)
472 pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL);
473
474 pb_reference(&resource->buf, NULL);
475 FREE(rtex);
476 }
477
478 static const struct u_resource_vtbl r600_texture_vtbl =
479 {
480 r600_texture_get_handle, /* get_handle */
481 r600_texture_destroy, /* resource_destroy */
482 r600_texture_get_transfer, /* get_transfer */
483 r600_texture_transfer_destroy, /* transfer_destroy */
484 r600_texture_transfer_map, /* transfer_map */
485 NULL, /* transfer_flush_region */
486 r600_texture_transfer_unmap, /* transfer_unmap */
487 NULL /* transfer_inline_write */
488 };
489
490 static struct r600_resource_texture *
491 r600_texture_create_object(struct pipe_screen *screen,
492 const struct pipe_resource *base,
493 unsigned array_mode,
494 unsigned pitch_in_bytes_override,
495 unsigned max_buffer_size,
496 struct pb_buffer *buf,
497 boolean alloc_bo,
498 struct radeon_surface *surface)
499 {
500 struct r600_resource_texture *rtex;
501 struct r600_resource *resource;
502 struct r600_screen *rscreen = (struct r600_screen*)screen;
503 int r;
504
505 rtex = CALLOC_STRUCT(r600_resource_texture);
506 if (rtex == NULL)
507 return NULL;
508
509 resource = &rtex->resource;
510 resource->b.b = *base;
511 resource->b.vtbl = &r600_texture_vtbl;
512 pipe_reference_init(&resource->b.b.reference, 1);
513 resource->b.b.screen = screen;
514 rtex->pitch_override = pitch_in_bytes_override;
515 rtex->real_format = base->format;
516
517 /* We must split depth and stencil into two separate buffers on Evergreen. */
518 if ((base->bind & PIPE_BIND_DEPTH_STENCIL) &&
519 ((struct r600_screen*)screen)->chip_class >= EVERGREEN &&
520 util_format_is_depth_and_stencil(base->format) &&
521 !rscreen->use_surface_alloc) {
522 struct pipe_resource stencil;
523 unsigned stencil_pitch_override = 0;
524
525 switch (base->format) {
526 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
527 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
528 break;
529 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
530 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
531 break;
532 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
533 rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
534 break;
535 default:
536 assert(0);
537 FREE(rtex);
538 return NULL;
539 }
540
541 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
542 if (pitch_in_bytes_override) {
543 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT ||
544 base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
545 stencil_pitch_override = pitch_in_bytes_override / 4;
546 }
547
548 /* Allocate the stencil buffer. */
549 stencil = *base;
550 stencil.format = PIPE_FORMAT_S8_UINT;
551 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
552 stencil_pitch_override,
553 max_buffer_size, NULL, FALSE, surface);
554 if (!rtex->stencil) {
555 FREE(rtex);
556 return NULL;
557 }
558 /* Proceed in creating the depth buffer. */
559 }
560
561 /* only mark depth textures the HW can hit as depth textures */
562 if (util_format_is_depth_or_stencil(rtex->real_format) &&
563 permit_hardware_blit(screen, base))
564 rtex->is_depth = true;
565
566 r600_setup_miptree(screen, rtex, array_mode);
567 if (rscreen->use_surface_alloc) {
568 rtex->surface = *surface;
569 r = r600_setup_surface(screen, rtex, array_mode,
570 pitch_in_bytes_override);
571 if (r) {
572 FREE(rtex);
573 return NULL;
574 }
575 }
576
577 /* If we initialized separate stencil for Evergreen. place it after depth. */
578 if (rtex->stencil) {
579 unsigned stencil_align, stencil_offset;
580
581 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
582 stencil_offset = align(rtex->size, stencil_align);
583
584 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.last_level; i++)
585 rtex->stencil->offset[i] += stencil_offset;
586
587 rtex->size = stencil_offset + rtex->stencil->size;
588 }
589
590 /* Now create the backing buffer. */
591 if (!buf && alloc_bo) {
592 struct pipe_resource *ptex = &rtex->resource.b.b;
593 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
594
595 if (rscreen->use_surface_alloc) {
596 base_align = rtex->surface.bo_alignment;
597 } else if (util_format_is_depth_or_stencil(rtex->real_format)) {
598 /* ugly work around depth buffer need stencil room at end of bo */
599 rtex->size += ptex->width0 * ptex->height0;
600 }
601 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
602 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
603 FREE(rtex);
604 return NULL;
605 }
606 } else if (buf) {
607 resource->buf = buf;
608 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
609 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
610 }
611
612 if (rtex->stencil) {
613 pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf);
614 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf;
615 rtex->stencil->resource.domains = rtex->resource.domains;
616 }
617 return rtex;
618 }
619
620 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
621 const struct pipe_resource *templ)
622 {
623 struct r600_screen *rscreen = (struct r600_screen*)screen;
624 struct radeon_surface surface;
625 unsigned array_mode = 0;
626 int r;
627
628 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) {
629 if (rscreen->use_surface_alloc &&
630 !(templ->bind & PIPE_BIND_SCANOUT) &&
631 templ->usage != PIPE_USAGE_STAGING &&
632 templ->usage != PIPE_USAGE_STREAM &&
633 permit_hardware_blit(screen, templ)) {
634 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
635 } else if (util_format_is_compressed(templ->format)) {
636 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
637 }
638 }
639
640 r = r600_init_surface(&surface, templ, array_mode,
641 templ->flags & R600_RESOURCE_FLAG_TRANSFER);
642 if (r) {
643 return NULL;
644 }
645 r = rscreen->ws->surface_best(rscreen->ws, &surface);
646 if (r) {
647 return NULL;
648 }
649 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
650 0, 0, NULL, TRUE, &surface);
651 }
652
653 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
654 struct pipe_resource *texture,
655 const struct pipe_surface *surf_tmpl)
656 {
657 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
658 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
659 unsigned level = surf_tmpl->u.tex.level;
660
661 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
662 if (surface == NULL)
663 return NULL;
664 pipe_reference_init(&surface->base.reference, 1);
665 pipe_resource_reference(&surface->base.texture, texture);
666 surface->base.context = pipe;
667 surface->base.format = surf_tmpl->format;
668 surface->base.width = mip_minify(texture->width0, level);
669 surface->base.height = mip_minify(texture->height0, level);
670 surface->base.usage = surf_tmpl->usage;
671 surface->base.texture = texture;
672 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
673 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
674 surface->base.u.tex.level = level;
675
676 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
677 rtex, level);
678 return &surface->base;
679 }
680
681 static void r600_surface_destroy(struct pipe_context *pipe,
682 struct pipe_surface *surface)
683 {
684 pipe_resource_reference(&surface->texture, NULL);
685 FREE(surface);
686 }
687
688 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
689 const struct pipe_resource *templ,
690 struct winsys_handle *whandle)
691 {
692 struct r600_screen *rscreen = (struct r600_screen*)screen;
693 struct pb_buffer *buf = NULL;
694 unsigned stride = 0;
695 unsigned array_mode = 0;
696 enum radeon_bo_layout micro, macro;
697 struct radeon_surface surface;
698 int r;
699
700 /* Support only 2D textures without mipmaps */
701 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
702 templ->depth0 != 1 || templ->last_level != 0)
703 return NULL;
704
705 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
706 if (!buf)
707 return NULL;
708
709 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
710 &surface.bankw, &surface.bankh,
711 &surface.tile_split,
712 &surface.stencil_tile_split,
713 &surface.mtilea);
714
715 if (macro == RADEON_LAYOUT_TILED)
716 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
717 else if (micro == RADEON_LAYOUT_TILED)
718 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
719 else
720 array_mode = 0;
721
722 r = r600_init_surface(&surface, templ, array_mode, 0);
723 if (r) {
724 return NULL;
725 }
726 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
727 stride, 0, buf, FALSE, &surface);
728 }
729
730 void r600_init_flushed_depth_texture(struct pipe_context *ctx,
731 struct pipe_resource *texture,
732 struct r600_resource_texture **staging)
733 {
734 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
735 struct pipe_resource resource;
736 struct r600_resource_texture **flushed_depth_texture = staging ?
737 staging : &rtex->flushed_depth_texture;
738
739 if (!staging && rtex->flushed_depth_texture)
740 return; /* it's ready */
741
742 resource.target = texture->target;
743 resource.format = texture->format;
744 resource.width0 = texture->width0;
745 resource.height0 = texture->height0;
746 resource.depth0 = texture->depth0;
747 resource.array_size = texture->array_size;
748 resource.last_level = texture->last_level;
749 resource.nr_samples = texture->nr_samples;
750 resource.usage = staging ? PIPE_USAGE_DYNAMIC : PIPE_USAGE_DEFAULT;
751 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
752 resource.flags = texture->flags;
753
754 if (staging)
755 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
756 else
757 rtex->dirty_db_mask = (1 << (resource.last_level+1)) - 1;
758
759 *flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
760 if (*flushed_depth_texture == NULL) {
761 R600_ERR("failed to create temporary texture to hold flushed depth\n");
762 return;
763 }
764
765 (*flushed_depth_texture)->is_flushing_texture = TRUE;
766
767 }
768
769 void r600_texture_depth_flush(struct pipe_context *ctx,
770 struct pipe_resource *texture,
771 struct r600_resource_texture **staging,
772 unsigned first_level, unsigned last_level,
773 unsigned first_layer, unsigned last_layer)
774 {
775 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
776
777 r600_init_flushed_depth_texture(ctx, texture, staging);
778
779 if (staging) {
780 if (!*staging)
781 return; /* error */
782
783 r600_blit_uncompress_depth(ctx, rtex, *staging,
784 first_level, last_level,
785 first_layer, last_layer);
786 } else {
787 if (!rtex->flushed_depth_texture)
788 return; /* error */
789
790 r600_blit_uncompress_depth(ctx, rtex, NULL,
791 first_level, last_level,
792 first_layer, last_layer);
793 }
794 }
795
796 /* Needs adjustment for pixelformat:
797 */
798 static INLINE unsigned u_box_volume( const struct pipe_box *box )
799 {
800 return box->width * box->depth * box->height;
801 }
802
803 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
804 struct pipe_resource *texture,
805 unsigned level,
806 unsigned usage,
807 const struct pipe_box *box)
808 {
809 struct r600_context *rctx = (struct r600_context*)ctx;
810 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
811 struct pipe_resource resource;
812 struct r600_transfer *trans;
813 boolean use_staging_texture = FALSE;
814
815 /* We cannot map a tiled texture directly because the data is
816 * in a different order, therefore we do detiling using a blit.
817 *
818 * Also, use a temporary in GTT memory for read transfers, as
819 * the CPU is much happier reading out of cached system memory
820 * than uncached VRAM.
821 */
822 if (R600_TEX_IS_TILED(rtex, level)) {
823 use_staging_texture = TRUE;
824 }
825
826 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
827 use_staging_texture = TRUE;
828
829 /* Use a staging texture for uploads if the underlying BO is busy. */
830 if (!(usage & PIPE_TRANSFER_READ) &&
831 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
832 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
833 use_staging_texture = TRUE;
834 }
835
836 if (!permit_hardware_blit(ctx->screen, texture) ||
837 (texture->flags & R600_RESOURCE_FLAG_TRANSFER)) {
838 use_staging_texture = FALSE;
839 }
840
841 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
842 return NULL;
843 }
844
845 trans = CALLOC_STRUCT(r600_transfer);
846 if (trans == NULL)
847 return NULL;
848 pipe_resource_reference(&trans->transfer.resource, texture);
849 trans->transfer.level = level;
850 trans->transfer.usage = usage;
851 trans->transfer.box = *box;
852 if (rtex->is_depth) {
853 /* XXX: only readback the rectangle which is being mapped?
854 */
855 /* XXX: when discard is true, no need to read back from depth texture
856 */
857 struct r600_resource_texture *staging_depth;
858
859 r600_texture_depth_flush(ctx, texture, &staging_depth,
860 level, level,
861 box->z, box->z + box->depth - 1);
862 if (!staging_depth) {
863 R600_ERR("failed to create temporary texture to hold untiled copy\n");
864 pipe_resource_reference(&trans->transfer.resource, NULL);
865 FREE(trans);
866 return NULL;
867 }
868 trans->transfer.stride = staging_depth->pitch_in_bytes[level];
869 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
870 trans->staging = (struct r600_resource*)staging_depth;
871 return &trans->transfer;
872 } else if (use_staging_texture) {
873 resource.target = PIPE_TEXTURE_2D;
874 resource.format = texture->format;
875 resource.width0 = box->width;
876 resource.height0 = box->height;
877 resource.depth0 = 1;
878 resource.array_size = 1;
879 resource.last_level = 0;
880 resource.nr_samples = 0;
881 resource.usage = PIPE_USAGE_STAGING;
882 resource.bind = 0;
883 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
884 /* For texture reading, the temporary (detiled) texture is used as
885 * a render target when blitting from a tiled texture. */
886 if (usage & PIPE_TRANSFER_READ) {
887 resource.bind |= PIPE_BIND_RENDER_TARGET;
888 }
889 /* For texture writing, the temporary texture is used as a sampler
890 * when blitting into a tiled texture. */
891 if (usage & PIPE_TRANSFER_WRITE) {
892 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
893 }
894 /* Create the temporary texture. */
895 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
896 if (trans->staging == NULL) {
897 R600_ERR("failed to create temporary texture to hold untiled copy\n");
898 pipe_resource_reference(&trans->transfer.resource, NULL);
899 FREE(trans);
900 return NULL;
901 }
902
903 trans->transfer.stride =
904 ((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0];
905 if (usage & PIPE_TRANSFER_READ) {
906 r600_copy_to_staging_texture(ctx, trans);
907 /* Always referenced in the blit. */
908 r600_flush(ctx, NULL, 0);
909 }
910 return &trans->transfer;
911 }
912 trans->transfer.stride = rtex->pitch_in_bytes[level];
913 trans->transfer.layer_stride = rtex->layer_size[level];
914 trans->offset = r600_texture_get_offset(rtex, level, box->z);
915 return &trans->transfer;
916 }
917
918 void r600_texture_transfer_destroy(struct pipe_context *ctx,
919 struct pipe_transfer *transfer)
920 {
921 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
922 struct pipe_resource *texture = transfer->resource;
923 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
924
925 if (rtex->is_depth) {
926 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
927 struct pipe_box sbox;
928
929 u_box_origin_2d(texture->width0, texture->height0, &sbox);
930
931 ctx->resource_copy_region(ctx, texture, 0, 0, 0, 0,
932 &rtransfer->staging->b.b, 0,
933 &sbox);
934 }
935 } else if (rtransfer->staging) {
936 if (transfer->usage & PIPE_TRANSFER_WRITE) {
937 r600_copy_from_staging_texture(ctx, rtransfer);
938 }
939 }
940
941 if (rtransfer->staging)
942 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
943
944 pipe_resource_reference(&transfer->resource, NULL);
945 FREE(transfer);
946 }
947
948 void* r600_texture_transfer_map(struct pipe_context *ctx,
949 struct pipe_transfer* transfer)
950 {
951 struct r600_context *rctx = (struct r600_context *)ctx;
952 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
953 struct radeon_winsys_cs_handle *buf;
954 struct r600_resource_texture *rtex =
955 (struct r600_resource_texture*)transfer->resource;
956 enum pipe_format format = transfer->resource->format;
957 unsigned offset = 0;
958 char *map;
959
960 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
961 return r600_compute_global_transfer_map(ctx, transfer);
962 }
963
964 if (rtransfer->staging) {
965 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
966 } else {
967 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
968 }
969
970 if (rtex->is_depth || !rtransfer->staging)
971 offset = rtransfer->offset +
972 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
973 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
974
975 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
976 return NULL;
977 }
978
979 return map + offset;
980 }
981
982 void r600_texture_transfer_unmap(struct pipe_context *ctx,
983 struct pipe_transfer* transfer)
984 {
985 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
986 struct r600_context *rctx = (struct r600_context*)ctx;
987 struct radeon_winsys_cs_handle *buf;
988
989 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
990 return r600_compute_global_transfer_unmap(ctx, transfer);
991 }
992
993 if (rtransfer->staging) {
994 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
995 } else {
996 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
997 }
998 rctx->ws->buffer_unmap(buf);
999 }
1000
1001 void r600_init_surface_functions(struct r600_context *r600)
1002 {
1003 r600->context.create_surface = r600_create_surface;
1004 r600->context.surface_destroy = r600_surface_destroy;
1005 }
1006
1007 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
1008 const unsigned char *swizzle_view)
1009 {
1010 unsigned i;
1011 unsigned char swizzle[4];
1012 unsigned result = 0;
1013 const uint32_t swizzle_shift[4] = {
1014 16, 19, 22, 25,
1015 };
1016 const uint32_t swizzle_bit[4] = {
1017 0, 1, 2, 3,
1018 };
1019
1020 if (swizzle_view) {
1021 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1022 } else {
1023 memcpy(swizzle, swizzle_format, 4);
1024 }
1025
1026 /* Get swizzle. */
1027 for (i = 0; i < 4; i++) {
1028 switch (swizzle[i]) {
1029 case UTIL_FORMAT_SWIZZLE_Y:
1030 result |= swizzle_bit[1] << swizzle_shift[i];
1031 break;
1032 case UTIL_FORMAT_SWIZZLE_Z:
1033 result |= swizzle_bit[2] << swizzle_shift[i];
1034 break;
1035 case UTIL_FORMAT_SWIZZLE_W:
1036 result |= swizzle_bit[3] << swizzle_shift[i];
1037 break;
1038 case UTIL_FORMAT_SWIZZLE_0:
1039 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1040 break;
1041 case UTIL_FORMAT_SWIZZLE_1:
1042 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1043 break;
1044 default: /* UTIL_FORMAT_SWIZZLE_X */
1045 result |= swizzle_bit[0] << swizzle_shift[i];
1046 }
1047 }
1048 return result;
1049 }
1050
1051 /* texture format translate */
1052 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1053 enum pipe_format format,
1054 const unsigned char *swizzle_view,
1055 uint32_t *word4_p, uint32_t *yuv_format_p)
1056 {
1057 uint32_t result = 0, word4 = 0, yuv_format = 0;
1058 const struct util_format_description *desc;
1059 boolean uniform = TRUE;
1060 static int r600_enable_s3tc = -1;
1061 bool is_srgb_valid = FALSE;
1062
1063 int i;
1064 const uint32_t sign_bit[4] = {
1065 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1066 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1067 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1068 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1069 };
1070 desc = util_format_description(format);
1071
1072 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
1073
1074 /* Colorspace (return non-RGB formats directly). */
1075 switch (desc->colorspace) {
1076 /* Depth stencil formats */
1077 case UTIL_FORMAT_COLORSPACE_ZS:
1078 switch (format) {
1079 case PIPE_FORMAT_Z16_UNORM:
1080 result = FMT_16;
1081 goto out_word4;
1082 case PIPE_FORMAT_X24S8_UINT:
1083 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1084 case PIPE_FORMAT_Z24X8_UNORM:
1085 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1086 result = FMT_8_24;
1087 goto out_word4;
1088 case PIPE_FORMAT_S8X24_UINT:
1089 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1090 case PIPE_FORMAT_X8Z24_UNORM:
1091 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1092 result = FMT_24_8;
1093 goto out_word4;
1094 case PIPE_FORMAT_S8_UINT:
1095 result = FMT_8;
1096 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1097 goto out_word4;
1098 case PIPE_FORMAT_Z32_FLOAT:
1099 result = FMT_32_FLOAT;
1100 goto out_word4;
1101 case PIPE_FORMAT_X32_S8X24_UINT:
1102 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1103 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1104 result = FMT_X24_8_32_FLOAT;
1105 goto out_word4;
1106 default:
1107 goto out_unknown;
1108 }
1109
1110 case UTIL_FORMAT_COLORSPACE_YUV:
1111 yuv_format |= (1 << 30);
1112 switch (format) {
1113 case PIPE_FORMAT_UYVY:
1114 case PIPE_FORMAT_YUYV:
1115 default:
1116 break;
1117 }
1118 goto out_unknown; /* XXX */
1119
1120 case UTIL_FORMAT_COLORSPACE_SRGB:
1121 word4 |= S_038010_FORCE_DEGAMMA(1);
1122 break;
1123
1124 default:
1125 break;
1126 }
1127
1128 if (r600_enable_s3tc == -1) {
1129 struct r600_screen *rscreen = (struct r600_screen *)screen;
1130 if (rscreen->info.drm_minor >= 9)
1131 r600_enable_s3tc = 1;
1132 else
1133 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
1134 }
1135
1136 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1137 if (!r600_enable_s3tc)
1138 goto out_unknown;
1139
1140 switch (format) {
1141 case PIPE_FORMAT_RGTC1_SNORM:
1142 case PIPE_FORMAT_LATC1_SNORM:
1143 word4 |= sign_bit[0];
1144 case PIPE_FORMAT_RGTC1_UNORM:
1145 case PIPE_FORMAT_LATC1_UNORM:
1146 result = FMT_BC4;
1147 goto out_word4;
1148 case PIPE_FORMAT_RGTC2_SNORM:
1149 case PIPE_FORMAT_LATC2_SNORM:
1150 word4 |= sign_bit[0] | sign_bit[1];
1151 case PIPE_FORMAT_RGTC2_UNORM:
1152 case PIPE_FORMAT_LATC2_UNORM:
1153 result = FMT_BC5;
1154 goto out_word4;
1155 default:
1156 goto out_unknown;
1157 }
1158 }
1159
1160 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1161
1162 if (!r600_enable_s3tc)
1163 goto out_unknown;
1164
1165 if (!util_format_s3tc_enabled) {
1166 goto out_unknown;
1167 }
1168
1169 switch (format) {
1170 case PIPE_FORMAT_DXT1_RGB:
1171 case PIPE_FORMAT_DXT1_RGBA:
1172 case PIPE_FORMAT_DXT1_SRGB:
1173 case PIPE_FORMAT_DXT1_SRGBA:
1174 result = FMT_BC1;
1175 is_srgb_valid = TRUE;
1176 goto out_word4;
1177 case PIPE_FORMAT_DXT3_RGBA:
1178 case PIPE_FORMAT_DXT3_SRGBA:
1179 result = FMT_BC2;
1180 is_srgb_valid = TRUE;
1181 goto out_word4;
1182 case PIPE_FORMAT_DXT5_RGBA:
1183 case PIPE_FORMAT_DXT5_SRGBA:
1184 result = FMT_BC3;
1185 is_srgb_valid = TRUE;
1186 goto out_word4;
1187 default:
1188 goto out_unknown;
1189 }
1190 }
1191
1192 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1193 switch (format) {
1194 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1195 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1196 result = FMT_GB_GR;
1197 goto out_word4;
1198 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1199 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1200 result = FMT_BG_RG;
1201 goto out_word4;
1202 default:
1203 goto out_unknown;
1204 }
1205 }
1206
1207 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1208 result = FMT_5_9_9_9_SHAREDEXP;
1209 goto out_word4;
1210 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1211 result = FMT_10_11_11_FLOAT;
1212 goto out_word4;
1213 }
1214
1215
1216 for (i = 0; i < desc->nr_channels; i++) {
1217 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1218 word4 |= sign_bit[i];
1219 }
1220 }
1221
1222 /* R8G8Bx_SNORM - XXX CxV8U8 */
1223
1224 /* See whether the components are of the same size. */
1225 for (i = 1; i < desc->nr_channels; i++) {
1226 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1227 }
1228
1229 /* Non-uniform formats. */
1230 if (!uniform) {
1231 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1232 desc->channel[0].pure_integer)
1233 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1234 switch(desc->nr_channels) {
1235 case 3:
1236 if (desc->channel[0].size == 5 &&
1237 desc->channel[1].size == 6 &&
1238 desc->channel[2].size == 5) {
1239 result = FMT_5_6_5;
1240 goto out_word4;
1241 }
1242 goto out_unknown;
1243 case 4:
1244 if (desc->channel[0].size == 5 &&
1245 desc->channel[1].size == 5 &&
1246 desc->channel[2].size == 5 &&
1247 desc->channel[3].size == 1) {
1248 result = FMT_1_5_5_5;
1249 goto out_word4;
1250 }
1251 if (desc->channel[0].size == 10 &&
1252 desc->channel[1].size == 10 &&
1253 desc->channel[2].size == 10 &&
1254 desc->channel[3].size == 2) {
1255 result = FMT_2_10_10_10;
1256 goto out_word4;
1257 }
1258 goto out_unknown;
1259 }
1260 goto out_unknown;
1261 }
1262
1263 /* Find the first non-VOID channel. */
1264 for (i = 0; i < 4; i++) {
1265 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1266 break;
1267 }
1268 }
1269
1270 if (i == 4)
1271 goto out_unknown;
1272
1273 /* uniform formats */
1274 switch (desc->channel[i].type) {
1275 case UTIL_FORMAT_TYPE_UNSIGNED:
1276 case UTIL_FORMAT_TYPE_SIGNED:
1277 #if 0
1278 if (!desc->channel[i].normalized &&
1279 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1280 goto out_unknown;
1281 }
1282 #endif
1283 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1284 desc->channel[i].pure_integer)
1285 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1286
1287 switch (desc->channel[i].size) {
1288 case 4:
1289 switch (desc->nr_channels) {
1290 case 2:
1291 result = FMT_4_4;
1292 goto out_word4;
1293 case 4:
1294 result = FMT_4_4_4_4;
1295 goto out_word4;
1296 }
1297 goto out_unknown;
1298 case 8:
1299 switch (desc->nr_channels) {
1300 case 1:
1301 result = FMT_8;
1302 goto out_word4;
1303 case 2:
1304 result = FMT_8_8;
1305 goto out_word4;
1306 case 4:
1307 result = FMT_8_8_8_8;
1308 is_srgb_valid = TRUE;
1309 goto out_word4;
1310 }
1311 goto out_unknown;
1312 case 16:
1313 switch (desc->nr_channels) {
1314 case 1:
1315 result = FMT_16;
1316 goto out_word4;
1317 case 2:
1318 result = FMT_16_16;
1319 goto out_word4;
1320 case 4:
1321 result = FMT_16_16_16_16;
1322 goto out_word4;
1323 }
1324 goto out_unknown;
1325 case 32:
1326 switch (desc->nr_channels) {
1327 case 1:
1328 result = FMT_32;
1329 goto out_word4;
1330 case 2:
1331 result = FMT_32_32;
1332 goto out_word4;
1333 case 4:
1334 result = FMT_32_32_32_32;
1335 goto out_word4;
1336 }
1337 }
1338 goto out_unknown;
1339
1340 case UTIL_FORMAT_TYPE_FLOAT:
1341 switch (desc->channel[i].size) {
1342 case 16:
1343 switch (desc->nr_channels) {
1344 case 1:
1345 result = FMT_16_FLOAT;
1346 goto out_word4;
1347 case 2:
1348 result = FMT_16_16_FLOAT;
1349 goto out_word4;
1350 case 4:
1351 result = FMT_16_16_16_16_FLOAT;
1352 goto out_word4;
1353 }
1354 goto out_unknown;
1355 case 32:
1356 switch (desc->nr_channels) {
1357 case 1:
1358 result = FMT_32_FLOAT;
1359 goto out_word4;
1360 case 2:
1361 result = FMT_32_32_FLOAT;
1362 goto out_word4;
1363 case 4:
1364 result = FMT_32_32_32_32_FLOAT;
1365 goto out_word4;
1366 }
1367 }
1368 goto out_unknown;
1369 }
1370
1371 out_word4:
1372
1373 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1374 return ~0;
1375 if (word4_p)
1376 *word4_p = word4;
1377 if (yuv_format_p)
1378 *yuv_format_p = yuv_format;
1379 return result;
1380 out_unknown:
1381 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1382 return ~0;
1383 }