2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_formats.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
37 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
38 struct pipe_resource
*texture
= transfer
->resource
;
40 ctx
->resource_copy_region(ctx
, &rtransfer
->staging
->b
.b
,
41 0, 0, 0, 0, texture
, transfer
->level
,
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
49 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
50 struct pipe_resource
*texture
= transfer
->resource
;
53 u_box_origin_2d(transfer
->box
.width
, transfer
->box
.height
, &sbox
);
55 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
56 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
57 &rtransfer
->staging
->b
.b
,
61 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
62 unsigned level
, unsigned layer
)
64 unsigned offset
= rtex
->offset
[level
];
66 switch (rtex
->resource
.b
.b
.target
) {
68 case PIPE_TEXTURE_CUBE
:
70 return offset
+ layer
* rtex
->layer_size
[level
];
74 static unsigned r600_get_block_alignment(struct pipe_screen
*screen
,
75 enum pipe_format format
,
78 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
79 unsigned pixsize
= util_format_get_blocksize(format
);
83 case V_038000_ARRAY_1D_TILED_THIN1
:
85 ((rscreen
->tiling_info
.group_bytes
/ 8 / pixsize
)));
87 case V_038000_ARRAY_2D_TILED_THIN1
:
88 p_align
= MAX2(rscreen
->tiling_info
.num_banks
,
89 (((rscreen
->tiling_info
.group_bytes
/ 8 / pixsize
)) *
90 rscreen
->tiling_info
.num_banks
)) * 8;
92 case V_038000_ARRAY_LINEAR_ALIGNED
:
93 p_align
= MAX2(64, rscreen
->tiling_info
.group_bytes
/ pixsize
);
95 case V_038000_ARRAY_LINEAR_GENERAL
:
97 p_align
= rscreen
->tiling_info
.group_bytes
/ pixsize
;
103 static unsigned r600_get_height_alignment(struct pipe_screen
*screen
,
106 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
109 switch (array_mode
) {
110 case V_038000_ARRAY_2D_TILED_THIN1
:
111 h_align
= rscreen
->tiling_info
.num_channels
* 8;
113 case V_038000_ARRAY_1D_TILED_THIN1
:
114 case V_038000_ARRAY_LINEAR_ALIGNED
:
117 case V_038000_ARRAY_LINEAR_GENERAL
:
125 static unsigned r600_get_base_alignment(struct pipe_screen
*screen
,
126 enum pipe_format format
,
129 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
130 unsigned pixsize
= util_format_get_blocksize(format
);
131 int p_align
= r600_get_block_alignment(screen
, format
, array_mode
);
132 int h_align
= r600_get_height_alignment(screen
, array_mode
);
135 switch (array_mode
) {
136 case V_038000_ARRAY_2D_TILED_THIN1
:
137 b_align
= MAX2(rscreen
->tiling_info
.num_banks
* rscreen
->tiling_info
.num_channels
* 8 * 8 * pixsize
,
138 p_align
* pixsize
* h_align
);
140 case V_038000_ARRAY_1D_TILED_THIN1
:
141 case V_038000_ARRAY_LINEAR_ALIGNED
:
142 case V_038000_ARRAY_LINEAR_GENERAL
:
144 b_align
= rscreen
->tiling_info
.group_bytes
;
150 static unsigned mip_minify(unsigned size
, unsigned level
)
153 val
= u_minify(size
, level
);
155 val
= util_next_power_of_two(val
);
159 static unsigned r600_texture_get_nblocksx(struct pipe_screen
*screen
,
160 struct r600_resource_texture
*rtex
,
163 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
164 unsigned nblocksx
, block_align
, width
;
165 unsigned blocksize
= util_format_get_blocksize(rtex
->real_format
);
167 if (rtex
->pitch_override
)
168 return rtex
->pitch_override
/ blocksize
;
170 width
= mip_minify(ptex
->width0
, level
);
171 nblocksx
= util_format_get_nblocksx(rtex
->real_format
, width
);
173 block_align
= r600_get_block_alignment(screen
, rtex
->real_format
,
174 rtex
->array_mode
[level
]);
175 nblocksx
= align(nblocksx
, block_align
);
179 static unsigned r600_texture_get_nblocksy(struct pipe_screen
*screen
,
180 struct r600_resource_texture
*rtex
,
183 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
184 unsigned height
, tile_height
;
186 height
= mip_minify(ptex
->height0
, level
);
187 height
= util_format_get_nblocksy(rtex
->real_format
, height
);
188 tile_height
= r600_get_height_alignment(screen
,
189 rtex
->array_mode
[level
]);
191 /* XXX Hack around an alignment issue. Less tests fail with this.
193 * The thing is depth-stencil buffers should be tiled, i.e.
194 * the alignment should be >=8. If I make them tiled, stencil starts
195 * working because it no longer overlaps with the depth buffer
196 * in memory, but texturing like drawpix-stencil breaks. */
197 if (util_format_is_depth_or_stencil(rtex
->real_format
) && tile_height
< 8)
200 height
= align(height
, tile_height
);
204 static void r600_texture_set_array_mode(struct pipe_screen
*screen
,
205 struct r600_resource_texture
*rtex
,
206 unsigned level
, unsigned array_mode
)
208 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
210 switch (array_mode
) {
211 case V_0280A0_ARRAY_LINEAR_GENERAL
:
212 case V_0280A0_ARRAY_LINEAR_ALIGNED
:
213 case V_0280A0_ARRAY_1D_TILED_THIN1
:
215 rtex
->array_mode
[level
] = array_mode
;
217 case V_0280A0_ARRAY_2D_TILED_THIN1
:
219 unsigned w
, h
, tile_height
, tile_width
;
221 tile_height
= r600_get_height_alignment(screen
, array_mode
);
222 tile_width
= r600_get_block_alignment(screen
, rtex
->real_format
, array_mode
);
224 w
= mip_minify(ptex
->width0
, level
);
225 h
= mip_minify(ptex
->height0
, level
);
226 if (w
<= tile_width
|| h
<= tile_height
)
227 rtex
->array_mode
[level
] = V_0280A0_ARRAY_1D_TILED_THIN1
;
229 rtex
->array_mode
[level
] = array_mode
;
235 static int r600_init_surface(struct radeon_surface
*surface
,
236 const struct pipe_resource
*ptex
,
238 bool is_transfer
, bool is_flushed_depth
)
240 const struct util_format_description
*desc
=
241 util_format_description(ptex
->format
);
242 bool is_depth
, is_stencil
;
244 is_depth
= util_format_has_depth(desc
);
245 is_stencil
= util_format_has_stencil(desc
);
247 surface
->npix_x
= ptex
->width0
;
248 surface
->npix_y
= ptex
->height0
;
249 surface
->npix_z
= ptex
->depth0
;
250 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
251 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
253 surface
->array_size
= 1;
254 surface
->last_level
= ptex
->last_level
;
255 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
256 /* align byte per element on dword */
257 if (surface
->bpe
== 3) {
260 surface
->nsamples
= 1;
262 switch (array_mode
) {
263 case V_038000_ARRAY_1D_TILED_THIN1
:
264 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
266 case V_038000_ARRAY_2D_TILED_THIN1
:
267 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
269 case V_038000_ARRAY_LINEAR_ALIGNED
:
270 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
272 case V_038000_ARRAY_LINEAR_GENERAL
:
274 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR
, MODE
);
277 switch (ptex
->target
) {
278 case PIPE_TEXTURE_1D
:
279 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
281 case PIPE_TEXTURE_RECT
:
282 case PIPE_TEXTURE_2D
:
283 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
285 case PIPE_TEXTURE_3D
:
286 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
288 case PIPE_TEXTURE_1D_ARRAY
:
289 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
290 surface
->array_size
= ptex
->array_size
;
292 case PIPE_TEXTURE_2D_ARRAY
:
293 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
294 surface
->array_size
= ptex
->array_size
;
296 case PIPE_TEXTURE_CUBE
:
297 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
303 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
304 surface
->flags
|= RADEON_SURF_SCANOUT
;
307 if (!is_transfer
&& !is_flushed_depth
&& is_depth
) {
308 surface
->flags
|= RADEON_SURF_ZBUFFER
;
311 surface
->flags
|= RADEON_SURF_SBUFFER
;
317 static int r600_setup_surface(struct pipe_screen
*screen
,
318 struct r600_resource_texture
*rtex
,
320 unsigned pitch_in_bytes_override
)
322 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
323 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
327 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
331 rtex
->size
= rtex
->surface
.bo_size
;
332 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
333 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
336 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
337 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
338 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
339 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
340 rtex
->surface
.stencil_offset
= rtex
->surface
.level
[0].slice_size
;
343 for (i
= 0; i
<= ptex
->last_level
; i
++) {
344 rtex
->offset
[i
] = rtex
->surface
.level
[i
].offset
;
345 rtex
->layer_size
[i
] = rtex
->surface
.level
[i
].slice_size
;
346 rtex
->pitch_in_bytes
[i
] = rtex
->surface
.level
[i
].pitch_bytes
;
347 switch (rtex
->surface
.level
[i
].mode
) {
348 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
349 rtex
->array_mode
[i
] = V_038000_ARRAY_LINEAR_ALIGNED
;
351 case RADEON_SURF_MODE_1D
:
352 rtex
->array_mode
[i
] = V_038000_ARRAY_1D_TILED_THIN1
;
354 case RADEON_SURF_MODE_2D
:
355 rtex
->array_mode
[i
] = V_038000_ARRAY_2D_TILED_THIN1
;
358 case RADEON_SURF_MODE_LINEAR
:
359 rtex
->array_mode
[i
] = 0;
366 static void r600_setup_miptree(struct pipe_screen
*screen
,
367 struct r600_resource_texture
*rtex
,
370 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
371 enum chip_class chipc
= ((struct r600_screen
*)screen
)->chip_class
;
372 unsigned size
, layer_size
, i
, offset
;
373 unsigned nblocksx
, nblocksy
;
375 for (i
= 0, offset
= 0; i
<= ptex
->last_level
; i
++) {
376 unsigned blocksize
= util_format_get_blocksize(rtex
->real_format
);
377 unsigned base_align
= r600_get_base_alignment(screen
, rtex
->real_format
, array_mode
);
379 r600_texture_set_array_mode(screen
, rtex
, i
, array_mode
);
381 nblocksx
= r600_texture_get_nblocksx(screen
, rtex
, i
);
382 nblocksy
= r600_texture_get_nblocksy(screen
, rtex
, i
);
384 if (chipc
>= EVERGREEN
&& array_mode
== V_038000_ARRAY_LINEAR_GENERAL
)
385 layer_size
= align(nblocksx
, 64) * nblocksy
* blocksize
;
387 layer_size
= nblocksx
* nblocksy
* blocksize
;
389 if (ptex
->target
== PIPE_TEXTURE_CUBE
) {
391 size
= layer_size
* 8;
393 size
= layer_size
* 6;
395 else if (ptex
->target
== PIPE_TEXTURE_3D
)
396 size
= layer_size
* u_minify(ptex
->depth0
, i
);
398 size
= layer_size
* ptex
->array_size
;
400 /* align base image and start of miptree */
401 if ((i
== 0) || (i
== 1))
402 offset
= align(offset
, base_align
);
403 rtex
->offset
[i
] = offset
;
404 rtex
->layer_size
[i
] = layer_size
;
405 rtex
->pitch_in_blocks
[i
] = nblocksx
; /* CB talks in elements */
406 rtex
->pitch_in_bytes
[i
] = nblocksx
* blocksize
;
413 /* Figure out whether u_blitter will fallback to a transfer operation.
414 * If so, don't use a staging resource.
416 static boolean
permit_hardware_blit(struct pipe_screen
*screen
,
417 const struct pipe_resource
*res
)
421 if (util_format_is_depth_or_stencil(res
->format
))
422 bind
= PIPE_BIND_DEPTH_STENCIL
;
424 bind
= PIPE_BIND_RENDER_TARGET
;
426 /* hackaround for S3TC */
427 if (util_format_is_compressed(res
->format
))
430 if (!screen
->is_format_supported(screen
,
437 if (!screen
->is_format_supported(screen
,
441 PIPE_BIND_SAMPLER_VIEW
))
447 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
448 struct pipe_resource
*ptex
,
449 struct winsys_handle
*whandle
)
451 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
452 struct r600_resource
*resource
= &rtex
->resource
;
453 struct radeon_surface
*surface
= &rtex
->surface
;
454 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
456 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
458 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
459 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
460 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
461 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
462 surface
->bankw
, surface
->bankh
,
464 surface
->stencil_tile_split
,
466 rtex
->pitch_in_bytes
[0]);
468 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
469 rtex
->pitch_in_bytes
[0], whandle
);
472 static void r600_texture_destroy(struct pipe_screen
*screen
,
473 struct pipe_resource
*ptex
)
475 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
476 struct r600_resource
*resource
= &rtex
->resource
;
478 if (rtex
->flushed_depth_texture
)
479 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
482 pipe_resource_reference((struct pipe_resource
**)&rtex
->stencil
, NULL
);
484 pb_reference(&resource
->buf
, NULL
);
488 static const struct u_resource_vtbl r600_texture_vtbl
=
490 r600_texture_get_handle
, /* get_handle */
491 r600_texture_destroy
, /* resource_destroy */
492 r600_texture_get_transfer
, /* get_transfer */
493 r600_texture_transfer_destroy
, /* transfer_destroy */
494 r600_texture_transfer_map
, /* transfer_map */
495 NULL
, /* transfer_flush_region */
496 r600_texture_transfer_unmap
, /* transfer_unmap */
497 NULL
/* transfer_inline_write */
500 static struct r600_resource_texture
*
501 r600_texture_create_object(struct pipe_screen
*screen
,
502 const struct pipe_resource
*base
,
504 unsigned pitch_in_bytes_override
,
505 unsigned max_buffer_size
,
506 struct pb_buffer
*buf
,
508 struct radeon_surface
*surface
)
510 struct r600_resource_texture
*rtex
;
511 struct r600_resource
*resource
;
512 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
515 rtex
= CALLOC_STRUCT(r600_resource_texture
);
519 resource
= &rtex
->resource
;
520 resource
->b
.b
= *base
;
521 resource
->b
.vtbl
= &r600_texture_vtbl
;
522 pipe_reference_init(&resource
->b
.b
.reference
, 1);
523 resource
->b
.b
.screen
= screen
;
524 rtex
->pitch_override
= pitch_in_bytes_override
;
525 rtex
->real_format
= base
->format
;
527 /* We must split depth and stencil into two separate buffers on Evergreen. */
528 if ((base
->bind
& PIPE_BIND_DEPTH_STENCIL
) &&
529 ((struct r600_screen
*)screen
)->chip_class
>= EVERGREEN
&&
530 util_format_is_depth_and_stencil(base
->format
) &&
531 !rscreen
->use_surface_alloc
) {
532 struct pipe_resource stencil
;
533 unsigned stencil_pitch_override
= 0;
535 switch (base
->format
) {
536 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
537 rtex
->real_format
= PIPE_FORMAT_Z24X8_UNORM
;
539 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
540 rtex
->real_format
= PIPE_FORMAT_X8Z24_UNORM
;
542 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
543 rtex
->real_format
= PIPE_FORMAT_Z32_FLOAT
;
551 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
552 if (pitch_in_bytes_override
) {
553 assert(base
->format
== PIPE_FORMAT_Z24_UNORM_S8_UINT
||
554 base
->format
== PIPE_FORMAT_S8_UINT_Z24_UNORM
);
555 stencil_pitch_override
= pitch_in_bytes_override
/ 4;
558 /* Allocate the stencil buffer. */
560 stencil
.format
= PIPE_FORMAT_S8_UINT
;
561 rtex
->stencil
= r600_texture_create_object(screen
, &stencil
, array_mode
,
562 stencil_pitch_override
,
563 max_buffer_size
, NULL
, FALSE
, surface
);
564 if (!rtex
->stencil
) {
568 /* Proceed in creating the depth buffer. */
571 /* only mark depth textures the HW can hit as depth textures */
572 if (util_format_is_depth_or_stencil(rtex
->real_format
) &&
573 permit_hardware_blit(screen
, base
))
574 rtex
->is_depth
= true;
576 r600_setup_miptree(screen
, rtex
, array_mode
);
577 if (rscreen
->use_surface_alloc
) {
578 rtex
->surface
= *surface
;
579 r
= r600_setup_surface(screen
, rtex
, array_mode
,
580 pitch_in_bytes_override
);
587 /* If we initialized separate stencil for Evergreen. place it after depth. */
589 unsigned stencil_align
, stencil_offset
;
591 stencil_align
= r600_get_base_alignment(screen
, rtex
->stencil
->real_format
, array_mode
);
592 stencil_offset
= align(rtex
->size
, stencil_align
);
594 for (unsigned i
= 0; i
<= rtex
->stencil
->resource
.b
.b
.last_level
; i
++)
595 rtex
->stencil
->offset
[i
] += stencil_offset
;
597 rtex
->size
= stencil_offset
+ rtex
->stencil
->size
;
600 /* Now create the backing buffer. */
601 if (!buf
&& alloc_bo
) {
602 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
603 unsigned base_align
= r600_get_base_alignment(screen
, ptex
->format
, array_mode
);
605 if (rscreen
->use_surface_alloc
) {
606 base_align
= rtex
->surface
.bo_alignment
;
607 } else if (util_format_is_depth_or_stencil(rtex
->real_format
)) {
608 /* ugly work around depth buffer need stencil room at end of bo */
609 rtex
->size
+= ptex
->width0
* ptex
->height0
;
611 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, base
->bind
, base
->usage
)) {
612 pipe_resource_reference((struct pipe_resource
**)&rtex
->stencil
, NULL
);
618 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
619 resource
->domains
= RADEON_DOMAIN_GTT
| RADEON_DOMAIN_VRAM
;
623 pb_reference(&rtex
->stencil
->resource
.buf
, rtex
->resource
.buf
);
624 rtex
->stencil
->resource
.cs_buf
= rtex
->resource
.cs_buf
;
625 rtex
->stencil
->resource
.domains
= rtex
->resource
.domains
;
630 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
631 const struct pipe_resource
*templ
)
633 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
634 struct radeon_surface surface
;
635 unsigned array_mode
= 0;
638 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)) {
639 if (rscreen
->use_surface_alloc
&&
640 !(templ
->bind
& PIPE_BIND_SCANOUT
) &&
641 templ
->usage
!= PIPE_USAGE_STAGING
&&
642 templ
->usage
!= PIPE_USAGE_STREAM
&&
643 permit_hardware_blit(screen
, templ
)) {
644 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
645 } else if (util_format_is_compressed(templ
->format
)) {
646 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
650 r
= r600_init_surface(&surface
, templ
, array_mode
,
651 templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
,
652 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
656 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
660 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
661 0, 0, NULL
, TRUE
, &surface
);
664 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
665 struct pipe_resource
*texture
,
666 const struct pipe_surface
*surf_tmpl
)
668 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
669 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
670 unsigned level
= surf_tmpl
->u
.tex
.level
;
672 assert(surf_tmpl
->u
.tex
.first_layer
== surf_tmpl
->u
.tex
.last_layer
);
675 pipe_reference_init(&surface
->base
.reference
, 1);
676 pipe_resource_reference(&surface
->base
.texture
, texture
);
677 surface
->base
.context
= pipe
;
678 surface
->base
.format
= surf_tmpl
->format
;
679 surface
->base
.width
= mip_minify(texture
->width0
, level
);
680 surface
->base
.height
= mip_minify(texture
->height0
, level
);
681 surface
->base
.usage
= surf_tmpl
->usage
;
682 surface
->base
.texture
= texture
;
683 surface
->base
.u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
684 surface
->base
.u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
685 surface
->base
.u
.tex
.level
= level
;
687 surface
->aligned_height
= r600_texture_get_nblocksy(pipe
->screen
,
689 return &surface
->base
;
692 static void r600_surface_destroy(struct pipe_context
*pipe
,
693 struct pipe_surface
*surface
)
695 pipe_resource_reference(&surface
->texture
, NULL
);
699 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
700 const struct pipe_resource
*templ
,
701 struct winsys_handle
*whandle
)
703 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
704 struct pb_buffer
*buf
= NULL
;
706 unsigned array_mode
= 0;
707 enum radeon_bo_layout micro
, macro
;
708 struct radeon_surface surface
;
711 /* Support only 2D textures without mipmaps */
712 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
713 templ
->depth0
!= 1 || templ
->last_level
!= 0)
716 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
720 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
721 &surface
.bankw
, &surface
.bankh
,
723 &surface
.stencil_tile_split
,
726 if (macro
== RADEON_LAYOUT_TILED
)
727 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
728 else if (micro
== RADEON_LAYOUT_TILED
)
729 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
733 r
= r600_init_surface(&surface
, templ
, array_mode
, false, false);
737 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
738 stride
, 0, buf
, FALSE
, &surface
);
741 void r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
742 struct pipe_resource
*texture
,
743 struct r600_resource_texture
**staging
)
745 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
746 struct pipe_resource resource
;
747 struct r600_resource_texture
**flushed_depth_texture
= staging
?
748 staging
: &rtex
->flushed_depth_texture
;
750 if (!staging
&& rtex
->flushed_depth_texture
)
751 return; /* it's ready */
753 resource
.target
= texture
->target
;
754 resource
.format
= texture
->format
;
755 resource
.width0
= texture
->width0
;
756 resource
.height0
= texture
->height0
;
757 resource
.depth0
= texture
->depth0
;
758 resource
.array_size
= texture
->array_size
;
759 resource
.last_level
= texture
->last_level
;
760 resource
.nr_samples
= texture
->nr_samples
;
761 resource
.usage
= staging
? PIPE_USAGE_DYNAMIC
: PIPE_USAGE_DEFAULT
;
762 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
763 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
766 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
768 *flushed_depth_texture
= (struct r600_resource_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
769 if (*flushed_depth_texture
== NULL
) {
770 R600_ERR("failed to create temporary texture to hold flushed depth\n");
774 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
778 void r600_texture_depth_flush(struct pipe_context
*ctx
,
779 struct pipe_resource
*texture
,
780 struct r600_resource_texture
**staging
,
781 unsigned first_level
, unsigned last_level
,
782 unsigned first_layer
, unsigned last_layer
)
784 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
786 r600_init_flushed_depth_texture(ctx
, texture
, staging
);
792 r600_blit_uncompress_depth(ctx
, rtex
, *staging
,
793 first_level
, last_level
,
794 first_layer
, last_layer
);
796 if (!rtex
->flushed_depth_texture
)
799 r600_blit_uncompress_depth(ctx
, rtex
, NULL
,
800 first_level
, last_level
,
801 first_layer
, last_layer
);
805 /* Needs adjustment for pixelformat:
807 static INLINE
unsigned u_box_volume( const struct pipe_box
*box
)
809 return box
->width
* box
->depth
* box
->height
;
812 struct pipe_transfer
* r600_texture_get_transfer(struct pipe_context
*ctx
,
813 struct pipe_resource
*texture
,
816 const struct pipe_box
*box
)
818 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
819 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
820 struct pipe_resource resource
;
821 struct r600_transfer
*trans
;
822 boolean use_staging_texture
= FALSE
;
824 /* We cannot map a tiled texture directly because the data is
825 * in a different order, therefore we do detiling using a blit.
827 * Also, use a temporary in GTT memory for read transfers, as
828 * the CPU is much happier reading out of cached system memory
829 * than uncached VRAM.
831 if (R600_TEX_IS_TILED(rtex
, level
)) {
832 use_staging_texture
= TRUE
;
835 if ((usage
& PIPE_TRANSFER_READ
) && u_box_volume(box
) > 1024)
836 use_staging_texture
= TRUE
;
838 /* Use a staging texture for uploads if the underlying BO is busy. */
839 if (!(usage
& PIPE_TRANSFER_READ
) &&
840 (rctx
->ws
->cs_is_buffer_referenced(rctx
->cs
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
841 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
))) {
842 use_staging_texture
= TRUE
;
845 if (!permit_hardware_blit(ctx
->screen
, texture
) ||
846 (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
)) {
847 use_staging_texture
= FALSE
;
850 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
854 trans
= CALLOC_STRUCT(r600_transfer
);
857 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
858 trans
->transfer
.level
= level
;
859 trans
->transfer
.usage
= usage
;
860 trans
->transfer
.box
= *box
;
861 if (rtex
->is_depth
) {
862 /* XXX: only readback the rectangle which is being mapped?
864 /* XXX: when discard is true, no need to read back from depth texture
866 struct r600_resource_texture
*staging_depth
;
868 r600_texture_depth_flush(ctx
, texture
, &staging_depth
,
870 box
->z
, box
->z
+ box
->depth
- 1);
871 if (!staging_depth
) {
872 R600_ERR("failed to create temporary texture to hold untiled copy\n");
873 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
877 trans
->transfer
.stride
= staging_depth
->pitch_in_bytes
[level
];
878 trans
->offset
= r600_texture_get_offset(staging_depth
, level
, box
->z
);
879 trans
->staging
= (struct r600_resource
*)staging_depth
;
880 return &trans
->transfer
;
881 } else if (use_staging_texture
) {
882 resource
.target
= PIPE_TEXTURE_2D
;
883 resource
.format
= texture
->format
;
884 resource
.width0
= box
->width
;
885 resource
.height0
= box
->height
;
887 resource
.array_size
= 1;
888 resource
.last_level
= 0;
889 resource
.nr_samples
= 0;
890 resource
.usage
= PIPE_USAGE_STAGING
;
892 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
893 /* For texture reading, the temporary (detiled) texture is used as
894 * a render target when blitting from a tiled texture. */
895 if (usage
& PIPE_TRANSFER_READ
) {
896 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
898 /* For texture writing, the temporary texture is used as a sampler
899 * when blitting into a tiled texture. */
900 if (usage
& PIPE_TRANSFER_WRITE
) {
901 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
903 /* Create the temporary texture. */
904 trans
->staging
= (struct r600_resource
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
905 if (trans
->staging
== NULL
) {
906 R600_ERR("failed to create temporary texture to hold untiled copy\n");
907 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
912 trans
->transfer
.stride
=
913 ((struct r600_resource_texture
*)trans
->staging
)->pitch_in_bytes
[0];
914 if (usage
& PIPE_TRANSFER_READ
) {
915 r600_copy_to_staging_texture(ctx
, trans
);
916 /* Always referenced in the blit. */
917 r600_flush(ctx
, NULL
, 0);
919 return &trans
->transfer
;
921 trans
->transfer
.stride
= rtex
->pitch_in_bytes
[level
];
922 trans
->transfer
.layer_stride
= rtex
->layer_size
[level
];
923 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
924 return &trans
->transfer
;
927 void r600_texture_transfer_destroy(struct pipe_context
*ctx
,
928 struct pipe_transfer
*transfer
)
930 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
931 struct pipe_resource
*texture
= transfer
->resource
;
932 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
934 if (rtex
->is_depth
) {
935 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
936 struct pipe_box sbox
;
938 u_box_origin_2d(texture
->width0
, texture
->height0
, &sbox
);
940 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
941 0, 0, transfer
->box
.z
,
942 &rtransfer
->staging
->b
.b
, transfer
->level
,
945 } else if (rtransfer
->staging
) {
946 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
947 r600_copy_from_staging_texture(ctx
, rtransfer
);
951 if (rtransfer
->staging
)
952 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
954 pipe_resource_reference(&transfer
->resource
, NULL
);
958 void* r600_texture_transfer_map(struct pipe_context
*ctx
,
959 struct pipe_transfer
* transfer
)
961 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
962 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
963 struct radeon_winsys_cs_handle
*buf
;
964 struct r600_resource_texture
*rtex
=
965 (struct r600_resource_texture
*)transfer
->resource
;
966 enum pipe_format format
= transfer
->resource
->format
;
970 if ((transfer
->resource
->bind
& PIPE_BIND_GLOBAL
) && transfer
->resource
->target
== PIPE_BUFFER
) {
971 return r600_compute_global_transfer_map(ctx
, transfer
);
974 if (rtransfer
->staging
) {
975 buf
= ((struct r600_resource
*)rtransfer
->staging
)->cs_buf
;
977 buf
= ((struct r600_resource
*)transfer
->resource
)->cs_buf
;
980 if (rtex
->is_depth
|| !rtransfer
->staging
)
981 offset
= rtransfer
->offset
+
982 transfer
->box
.y
/ util_format_get_blockheight(format
) * transfer
->stride
+
983 transfer
->box
.x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
985 if (!(map
= rctx
->ws
->buffer_map(buf
, rctx
->cs
, transfer
->usage
))) {
992 void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
993 struct pipe_transfer
* transfer
)
995 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
996 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
997 struct radeon_winsys_cs_handle
*buf
;
999 if ((transfer
->resource
->bind
& PIPE_BIND_GLOBAL
) && transfer
->resource
->target
== PIPE_BUFFER
) {
1000 return r600_compute_global_transfer_unmap(ctx
, transfer
);
1003 if (rtransfer
->staging
) {
1004 buf
= ((struct r600_resource
*)rtransfer
->staging
)->cs_buf
;
1006 buf
= ((struct r600_resource
*)transfer
->resource
)->cs_buf
;
1008 rctx
->ws
->buffer_unmap(buf
);
1011 void r600_init_surface_functions(struct r600_context
*r600
)
1013 r600
->context
.create_surface
= r600_create_surface
;
1014 r600
->context
.surface_destroy
= r600_surface_destroy
;
1017 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
1018 const unsigned char *swizzle_view
)
1021 unsigned char swizzle
[4];
1022 unsigned result
= 0;
1023 const uint32_t swizzle_shift
[4] = {
1026 const uint32_t swizzle_bit
[4] = {
1031 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
1033 memcpy(swizzle
, swizzle_format
, 4);
1037 for (i
= 0; i
< 4; i
++) {
1038 switch (swizzle
[i
]) {
1039 case UTIL_FORMAT_SWIZZLE_Y
:
1040 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
1042 case UTIL_FORMAT_SWIZZLE_Z
:
1043 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
1045 case UTIL_FORMAT_SWIZZLE_W
:
1046 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
1048 case UTIL_FORMAT_SWIZZLE_0
:
1049 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
1051 case UTIL_FORMAT_SWIZZLE_1
:
1052 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
1054 default: /* UTIL_FORMAT_SWIZZLE_X */
1055 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
1061 /* texture format translate */
1062 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
1063 enum pipe_format format
,
1064 const unsigned char *swizzle_view
,
1065 uint32_t *word4_p
, uint32_t *yuv_format_p
)
1067 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
1068 const struct util_format_description
*desc
;
1069 boolean uniform
= TRUE
;
1070 static int r600_enable_s3tc
= -1;
1071 bool is_srgb_valid
= FALSE
;
1074 const uint32_t sign_bit
[4] = {
1075 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
1076 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
1077 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
1078 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
1080 desc
= util_format_description(format
);
1082 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
1084 /* Colorspace (return non-RGB formats directly). */
1085 switch (desc
->colorspace
) {
1086 /* Depth stencil formats */
1087 case UTIL_FORMAT_COLORSPACE_ZS
:
1089 case PIPE_FORMAT_Z16_UNORM
:
1092 case PIPE_FORMAT_X24S8_UINT
:
1093 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1094 case PIPE_FORMAT_Z24X8_UNORM
:
1095 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1098 case PIPE_FORMAT_S8X24_UINT
:
1099 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1100 case PIPE_FORMAT_X8Z24_UNORM
:
1101 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1104 case PIPE_FORMAT_S8_UINT
:
1106 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1108 case PIPE_FORMAT_Z32_FLOAT
:
1109 result
= FMT_32_FLOAT
;
1111 case PIPE_FORMAT_X32_S8X24_UINT
:
1112 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1113 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1114 result
= FMT_X24_8_32_FLOAT
;
1120 case UTIL_FORMAT_COLORSPACE_YUV
:
1121 yuv_format
|= (1 << 30);
1123 case PIPE_FORMAT_UYVY
:
1124 case PIPE_FORMAT_YUYV
:
1128 goto out_unknown
; /* XXX */
1130 case UTIL_FORMAT_COLORSPACE_SRGB
:
1131 word4
|= S_038010_FORCE_DEGAMMA(1);
1138 if (r600_enable_s3tc
== -1) {
1139 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1140 if (rscreen
->info
.drm_minor
>= 9)
1141 r600_enable_s3tc
= 1;
1143 r600_enable_s3tc
= debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
1146 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1147 if (!r600_enable_s3tc
)
1151 case PIPE_FORMAT_RGTC1_SNORM
:
1152 case PIPE_FORMAT_LATC1_SNORM
:
1153 word4
|= sign_bit
[0];
1154 case PIPE_FORMAT_RGTC1_UNORM
:
1155 case PIPE_FORMAT_LATC1_UNORM
:
1158 case PIPE_FORMAT_RGTC2_SNORM
:
1159 case PIPE_FORMAT_LATC2_SNORM
:
1160 word4
|= sign_bit
[0] | sign_bit
[1];
1161 case PIPE_FORMAT_RGTC2_UNORM
:
1162 case PIPE_FORMAT_LATC2_UNORM
:
1170 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1172 if (!r600_enable_s3tc
)
1175 if (!util_format_s3tc_enabled
) {
1180 case PIPE_FORMAT_DXT1_RGB
:
1181 case PIPE_FORMAT_DXT1_RGBA
:
1182 case PIPE_FORMAT_DXT1_SRGB
:
1183 case PIPE_FORMAT_DXT1_SRGBA
:
1185 is_srgb_valid
= TRUE
;
1187 case PIPE_FORMAT_DXT3_RGBA
:
1188 case PIPE_FORMAT_DXT3_SRGBA
:
1190 is_srgb_valid
= TRUE
;
1192 case PIPE_FORMAT_DXT5_RGBA
:
1193 case PIPE_FORMAT_DXT5_SRGBA
:
1195 is_srgb_valid
= TRUE
;
1202 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1204 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1205 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1208 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1209 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1217 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1218 result
= FMT_5_9_9_9_SHAREDEXP
;
1220 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1221 result
= FMT_10_11_11_FLOAT
;
1226 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1227 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1228 word4
|= sign_bit
[i
];
1232 /* R8G8Bx_SNORM - XXX CxV8U8 */
1234 /* See whether the components are of the same size. */
1235 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1236 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1239 /* Non-uniform formats. */
1241 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1242 desc
->channel
[0].pure_integer
)
1243 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1244 switch(desc
->nr_channels
) {
1246 if (desc
->channel
[0].size
== 5 &&
1247 desc
->channel
[1].size
== 6 &&
1248 desc
->channel
[2].size
== 5) {
1254 if (desc
->channel
[0].size
== 5 &&
1255 desc
->channel
[1].size
== 5 &&
1256 desc
->channel
[2].size
== 5 &&
1257 desc
->channel
[3].size
== 1) {
1258 result
= FMT_1_5_5_5
;
1261 if (desc
->channel
[0].size
== 10 &&
1262 desc
->channel
[1].size
== 10 &&
1263 desc
->channel
[2].size
== 10 &&
1264 desc
->channel
[3].size
== 2) {
1265 result
= FMT_2_10_10_10
;
1273 /* Find the first non-VOID channel. */
1274 for (i
= 0; i
< 4; i
++) {
1275 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1283 /* uniform formats */
1284 switch (desc
->channel
[i
].type
) {
1285 case UTIL_FORMAT_TYPE_UNSIGNED
:
1286 case UTIL_FORMAT_TYPE_SIGNED
:
1288 if (!desc
->channel
[i
].normalized
&&
1289 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
1293 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1294 desc
->channel
[i
].pure_integer
)
1295 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1297 switch (desc
->channel
[i
].size
) {
1299 switch (desc
->nr_channels
) {
1304 result
= FMT_4_4_4_4
;
1309 switch (desc
->nr_channels
) {
1317 result
= FMT_8_8_8_8
;
1318 is_srgb_valid
= TRUE
;
1323 switch (desc
->nr_channels
) {
1331 result
= FMT_16_16_16_16
;
1336 switch (desc
->nr_channels
) {
1344 result
= FMT_32_32_32_32
;
1350 case UTIL_FORMAT_TYPE_FLOAT
:
1351 switch (desc
->channel
[i
].size
) {
1353 switch (desc
->nr_channels
) {
1355 result
= FMT_16_FLOAT
;
1358 result
= FMT_16_16_FLOAT
;
1361 result
= FMT_16_16_16_16_FLOAT
;
1366 switch (desc
->nr_channels
) {
1368 result
= FMT_32_FLOAT
;
1371 result
= FMT_32_32_FLOAT
;
1374 result
= FMT_32_32_32_32_FLOAT
;
1383 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
1388 *yuv_format_p
= yuv_format
;
1391 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */