src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_math.h>
  31 #include <util/u_inlines.h>
  32 #include <util/u_memory.h>
  33 #include "state_tracker/drm_driver.h"
  34 #include "pipebuffer/pb_buffer.h"
  35 #include "r600_pipe.h"
  36 #include "r600_resource.h"
  37 #include "r600_state_inlines.h"
  38 #include "r600d.h"
  39 #include "r600_formats.h"
  40
  41 extern struct u_resource_vtbl r600_texture_vtbl;
  42
  43 /* Copy from a full GPU texture to a transfer's staging one. */
  44 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  45 {
  46         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  47         struct pipe_resource *texture = transfer->resource;
  48
  49         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  50                                 0, 0, 0, 0, texture, transfer->level,
  51                                 &transfer->box);
  52 }
  53
  54
  55 /* Copy from a transfer's staging texture to a full GPU one. */
  56 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  57 {
  58         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  59         struct pipe_resource *texture = transfer->resource;
  60         struct pipe_box sbox;
  61
  62         sbox.x = sbox.y = sbox.z = 0;
  63         sbox.width = transfer->box.width;
  64         sbox.height = transfer->box.height;
  65         /* XXX that might be wrong */
  66         sbox.depth = 1;
  67         ctx->resource_copy_region(ctx, texture, transfer->level,
  68                                   transfer->box.x, transfer->box.y, transfer->box.z,
  69                                   rtransfer->staging_texture,
  70                                   0, &sbox);
  71
  72         ctx->flush(ctx, 0, NULL);
  73 }
  74
  75 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  76                                         unsigned level, unsigned layer)
  77 {
  78         unsigned offset = rtex->offset[level];
  79
  80         switch (rtex->resource.base.b.target) {
  81         case PIPE_TEXTURE_3D:
  82         case PIPE_TEXTURE_CUBE:
  83                 return offset + layer * rtex->layer_size[level];
  84         default:
  85                 assert(layer == 0);
  86                 return offset;
  87         }
  88 }
  89
  90 static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
  91                                          enum pipe_format format,
  92                                          unsigned array_mode)
  93 {
  94         struct r600_screen* rscreen = (struct r600_screen *)screen;
  95         unsigned pixsize = util_format_get_blocksize(format);
  96         int p_align;
  97
  98         switch(array_mode) {
  99         case V_038000_ARRAY_1D_TILED_THIN1:
 100                 p_align = MAX2(8,
 101                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
 102                 break;
 103         case V_038000_ARRAY_2D_TILED_THIN1:
 104                 p_align = MAX2(rscreen->tiling_info->num_banks,
 105                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 106                                 rscreen->tiling_info->num_banks)) * 8;
 107                 break;
 108         case V_038000_ARRAY_LINEAR_GENERAL:
 109         default:
 110                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 111                 break;
 112         }
 113         return p_align;
 114 }
 115
 116 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 117                                           unsigned array_mode)
 118 {
 119         struct r600_screen* rscreen = (struct r600_screen *)screen;
 120         int h_align;
 121
 122         switch (array_mode) {
 123         case V_038000_ARRAY_2D_TILED_THIN1:
 124                 h_align = rscreen->tiling_info->num_channels * 8;
 125                 break;
 126         case V_038000_ARRAY_1D_TILED_THIN1:
 127                 h_align = 8;
 128                 break;
 129         default:
 130                 h_align = 1;
 131                 break;
 132         }
 133         return h_align;
 134 }
 135
 136 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 137                                         enum pipe_format format,
 138                                         unsigned array_mode)
 139 {
 140         struct r600_screen* rscreen = (struct r600_screen *)screen;
 141         unsigned pixsize = util_format_get_blocksize(format);
 142         int p_align = r600_get_pixel_alignment(screen, format, array_mode);
 143         int h_align = r600_get_height_alignment(screen, array_mode);
 144         int b_align;
 145
 146         switch (array_mode) {
 147         case V_038000_ARRAY_2D_TILED_THIN1:
 148                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 149                                p_align * pixsize * h_align);
 150                 break;
 151         case V_038000_ARRAY_1D_TILED_THIN1:
 152         default:
 153                 b_align = rscreen->tiling_info->group_bytes;
 154                 break;
 155         }
 156         return b_align;
 157 }
 158
 159 static unsigned mip_minify(unsigned size, unsigned level)
 160 {
 161         unsigned val;
 162         val = u_minify(size, level);
 163         if (level > 0)
 164                 val = util_next_power_of_two(val);
 165         return val;
 166 }
 167
 168 static unsigned r600_texture_get_stride(struct pipe_screen *screen,
 169                                         struct r600_resource_texture *rtex,
 170                                         unsigned level)
 171 {
 172         struct pipe_resource *ptex = &rtex->resource.base.b;
 173         unsigned width, stride, tile_width;
 174
 175         if (rtex->pitch_override)
 176                 return rtex->pitch_override;
 177
 178         width = mip_minify(ptex->width0, level);
 179         if (util_format_is_plain(ptex->format)) {
 180                 tile_width = r600_get_pixel_alignment(screen, ptex->format,
 181                                                       rtex->array_mode[level]);
 182                 width = align(width, tile_width);
 183         }
 184         stride = util_format_get_stride(ptex->format, width);
 185
 186         return stride;
 187 }
 188
 189 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 190                                           struct r600_resource_texture *rtex,
 191                                           unsigned level)
 192 {
 193         struct pipe_resource *ptex = &rtex->resource.base.b;
 194         unsigned height, tile_height;
 195
 196         height = mip_minify(ptex->height0, level);
 197         if (util_format_is_plain(ptex->format)) {
 198                 tile_height = r600_get_height_alignment(screen,
 199                                                         rtex->array_mode[level]);
 200                 height = align(height, tile_height);
 201         }
 202         return util_format_get_nblocksy(ptex->format, height);
 203 }
 204
 205 /* Get a width in pixels from a stride in bytes. */
 206 static unsigned pitch_to_width(enum pipe_format format, unsigned pitch_in_bytes)
 207 {
 208         return (pitch_in_bytes / util_format_get_blocksize(format)) *
 209                 util_format_get_blockwidth(format);
 210 }
 211
 212 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 213                                         struct r600_resource_texture *rtex,
 214                                         unsigned level, unsigned array_mode)
 215 {
 216         struct pipe_resource *ptex = &rtex->resource.base.b;
 217
 218         switch (array_mode) {
 219         case V_0280A0_ARRAY_LINEAR_GENERAL:
 220         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 221         case V_0280A0_ARRAY_1D_TILED_THIN1:
 222         default:
 223                 rtex->array_mode[level] = array_mode;
 224                 break;
 225         case V_0280A0_ARRAY_2D_TILED_THIN1:
 226         {
 227                 unsigned w, h, tile_height, tile_width;
 228
 229                 tile_height = r600_get_height_alignment(screen, array_mode);
 230                 tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode);
 231
 232                 w = mip_minify(ptex->width0, level);
 233                 h = mip_minify(ptex->height0, level);
 234                 if (w < tile_width || h < tile_height)
 235                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 236                 else
 237                         rtex->array_mode[level] = array_mode;
 238         }
 239         break;
 240         }
 241 }
 242
 243 static void r600_setup_miptree(struct pipe_screen *screen,
 244                                struct r600_resource_texture *rtex,
 245                                unsigned array_mode)
 246 {
 247         struct pipe_resource *ptex = &rtex->resource.base.b;
 248         struct radeon *radeon = (struct radeon *)screen->winsys;
 249         enum chip_class chipc = r600_get_family_class(radeon);
 250         unsigned pitch, size, layer_size, i, offset;
 251         unsigned nblocksy;
 252
 253         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 254                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 255
 256                 pitch = r600_texture_get_stride(screen, rtex, i);
 257                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 258
 259                 layer_size = pitch * nblocksy;
 260
 261                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 262                         if (chipc >= R700)
 263                                 size = layer_size * 8;
 264                         else
 265                                 size = layer_size * 6;
 266                 }
 267                 else
 268                         size = layer_size * u_minify(ptex->depth0, i);
 269                 /* align base image and start of miptree */
 270                 if ((i == 0) || (i == 1))
 271                         offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
 272                 rtex->offset[i] = offset;
 273                 rtex->layer_size[i] = layer_size;
 274                 rtex->pitch_in_bytes[i] = pitch;
 275                 rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
 276                 offset += size;
 277         }
 278         rtex->size = offset;
 279 }
 280
 281 static struct r600_resource_texture *
 282 r600_texture_create_object(struct pipe_screen *screen,
 283                            const struct pipe_resource *base,
 284                            unsigned array_mode,
 285                            unsigned pitch_in_bytes_override,
 286                            unsigned max_buffer_size,
 287                            struct r600_bo *bo)
 288 {
 289         struct r600_resource_texture *rtex;
 290         struct r600_resource *resource;
 291         struct radeon *radeon = (struct radeon *)screen->winsys;
 292
 293         rtex = CALLOC_STRUCT(r600_resource_texture);
 294         if (rtex == NULL)
 295                 return NULL;
 296
 297         resource = &rtex->resource;
 298         resource->base.b = *base;
 299         resource->base.vtbl = &r600_texture_vtbl;
 300         pipe_reference_init(&resource->base.b.reference, 1);
 301         resource->base.b.screen = screen;
 302         resource->bo = bo;
 303         rtex->pitch_override = pitch_in_bytes_override;
 304
 305         if (array_mode)
 306                 rtex->tiled = 1;
 307         r600_setup_miptree(screen, rtex, array_mode);
 308
 309         resource->size = rtex->size;
 310
 311         if (!resource->bo) {
 312                 struct pipe_resource *ptex = &rtex->resource.base.b;
 313                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 314
 315                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 316                 if (!resource->bo) {
 317                         FREE(rtex);
 318                         return NULL;
 319                 }
 320         }
 321         return rtex;
 322 }
 323
 324 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 325                                                 const struct pipe_resource *templ)
 326 {
 327         unsigned array_mode = 0;
 328         static int force_tiling = -1;
 329
 330         /* Would like some magic "get_bool_option_once" routine.
 331          */
 332         if (force_tiling == -1)
 333                 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
 334
 335         if (force_tiling) {
 336                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 337                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 338                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 339                 }
 340         }
 341
 342         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 343                                                                   0, 0, NULL);
 344
 345 }
 346
 347 static void r600_texture_destroy(struct pipe_screen *screen,
 348                                  struct pipe_resource *ptex)
 349 {
 350         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 351         struct r600_resource *resource = &rtex->resource;
 352         struct radeon *radeon = (struct radeon *)screen->winsys;
 353
 354         if (rtex->flushed_depth_texture)
 355                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 356
 357         if (resource->bo) {
 358                 r600_bo_reference(radeon, &resource->bo, NULL);
 359         }
 360         FREE(rtex);
 361 }
 362
 363 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 364                                         struct pipe_resource *ptex,
 365                                         struct winsys_handle *whandle)
 366 {
 367         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 368         struct r600_resource *resource = &rtex->resource;
 369         struct radeon *radeon = (struct radeon *)screen->winsys;
 370
 371         return r600_bo_get_winsys_handle(radeon, resource->bo,
 372                         rtex->pitch_in_bytes[0], whandle);
 373 }
 374
 375 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 376                                                 struct pipe_resource *texture,
 377                                                 const struct pipe_surface *surf_tmpl)
 378 {
 379         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 380         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 381         unsigned tile_height;
 382         unsigned level = surf_tmpl->u.tex.level;
 383
 384         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 385         if (surface == NULL)
 386                 return NULL;
 387         /* XXX no offset */
 388 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 389         pipe_reference_init(&surface->base.reference, 1);
 390         pipe_resource_reference(&surface->base.texture, texture);
 391         surface->base.context = pipe;
 392         surface->base.format = surf_tmpl->format;
 393         surface->base.width = mip_minify(texture->width0, level);
 394         surface->base.height = mip_minify(texture->height0, level);
 395         surface->base.usage = surf_tmpl->usage;
 396         surface->base.texture = texture;
 397         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 398         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 399         surface->base.u.tex.level = level;
 400
 401         tile_height = r600_get_height_alignment(pipe->screen, rtex->array_mode[level]);
 402         surface->aligned_height = align(surface->base.height, tile_height);
 403         return &surface->base;
 404 }
 405
 406 static void r600_surface_destroy(struct pipe_context *pipe,
 407                                  struct pipe_surface *surface)
 408 {
 409         pipe_resource_reference(&surface->texture, NULL);
 410         FREE(surface);
 411 }
 412
 413
 414 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 415                                                const struct pipe_resource *templ,
 416                                                struct winsys_handle *whandle)
 417 {
 418         struct radeon *rw = (struct radeon*)screen->winsys;
 419         struct r600_bo *bo = NULL;
 420         unsigned array_mode = 0;
 421
 422         /* Support only 2D textures without mipmaps */
 423         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 424               templ->depth0 != 1 || templ->last_level != 0)
 425                 return NULL;
 426
 427         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 428         if (bo == NULL) {
 429                 return NULL;
 430         }
 431
 432         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 433                                                                   whandle->stride,
 434                                                                   0,
 435                                                                   bo);
 436 }
 437
 438 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 439                                                 struct pipe_resource *texture,
 440                                                 unsigned level, int layer)
 441 {
 442         /* FIXME */
 443         return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 444 }
 445
 446 int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct r600_resource_texture *texture);
 447
 448 int r600_texture_depth_flush(struct pipe_context *ctx,
 449                              struct pipe_resource *texture)
 450 {
 451         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 452         struct pipe_resource resource;
 453
 454         if (rtex->flushed_depth_texture)
 455                 goto out;
 456
 457         resource.target = PIPE_TEXTURE_2D;
 458         resource.format = texture->format;
 459         resource.width0 = texture->width0;
 460         resource.height0 = texture->height0;
 461         resource.depth0 = 1;
 462         resource.last_level = 0;
 463         resource.nr_samples = 0;
 464         resource.usage = PIPE_USAGE_DYNAMIC;
 465         resource.bind = 0;
 466         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 467
 468         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 469
 470         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 471         if (rtex->flushed_depth_texture == NULL) {
 472                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 473                 return -ENOMEM;
 474         }
 475
 476 out:
 477         /* XXX: only do this if the depth texture has actually changed:
 478          */
 479         r600_blit_uncompress_depth_ptr(ctx, rtex);
 480         return 0;
 481 }
 482
 483 /* Needs adjustment for pixelformat:
 484  */
 485 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 486 {
 487         return box->width * box->depth * box->height;
 488 };
 489
 490
 491 /* Figure out whether u_blitter will fallback to a transfer operation.
 492  * If so, don't use a staging resource.
 493  */
 494 static boolean permit_hardware_blit(struct pipe_screen *screen,
 495                                         struct pipe_resource *res)
 496 {
 497         unsigned bind;
 498
 499         if (util_format_is_depth_or_stencil(res->format))
 500                 bind = PIPE_BIND_DEPTH_STENCIL;
 501         else
 502                 bind = PIPE_BIND_RENDER_TARGET;
 503
 504         /* See r600_resource_copy_region: there is something wrong
 505          * with depth resource copies at the moment so avoid them for
 506          * now.
 507          */
 508         if (util_format_get_component_bits(res->format,
 509                                 UTIL_FORMAT_COLORSPACE_ZS,
 510                                 0) != 0)
 511                 return FALSE;
 512
 513         if (!screen->is_format_supported(screen,
 514                                 res->format,
 515                                 res->target,
 516                                 res->nr_samples,
 517                                 bind, 0))
 518                 return FALSE;
 519
 520         if (!screen->is_format_supported(screen,
 521                                 res->format,
 522                                 res->target,
 523                                 res->nr_samples,
 524                                 PIPE_BIND_SAMPLER_VIEW, 0))
 525                 return FALSE;
 526
 527         return TRUE;
 528 }
 529
 530 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 531                                                 struct pipe_resource *texture,
 532                                                 unsigned level,
 533                                                 unsigned usage,
 534                                                 const struct pipe_box *box)
 535 {
 536         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 537         struct pipe_resource resource;
 538         struct r600_transfer *trans;
 539         int r;
 540         boolean use_staging_texture = FALSE;
 541
 542         /* We cannot map a tiled texture directly because the data is
 543          * in a different order, therefore we do detiling using a blit.
 544          *
 545          * Also, use a temporary in GTT memory for read transfers, as
 546          * the CPU is much happier reading out of cached system memory
 547          * than uncached VRAM.
 548          */
 549         if (rtex->tiled)
 550                 use_staging_texture = TRUE;
 551
 552         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 553                 use_staging_texture = TRUE;
 554
 555         /* XXX: Use a staging texture for uploads if the underlying BO
 556          * is busy.  No interface for checking that currently? so do
 557          * it eagerly whenever the transfer doesn't require a readback
 558          * and might block.
 559          */
 560         if ((usage & PIPE_TRANSFER_WRITE) &&
 561                         !(usage & (PIPE_TRANSFER_READ |
 562                                         PIPE_TRANSFER_DONTBLOCK |
 563                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 564                 use_staging_texture = TRUE;
 565
 566         if (!permit_hardware_blit(ctx->screen, texture) ||
 567                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 568                 use_staging_texture = FALSE;
 569
 570         trans = CALLOC_STRUCT(r600_transfer);
 571         if (trans == NULL)
 572                 return NULL;
 573         pipe_resource_reference(&trans->transfer.resource, texture);
 574         trans->transfer.level = level;
 575         trans->transfer.usage = usage;
 576         trans->transfer.box = *box;
 577         if (rtex->depth) {
 578                 /* XXX: only readback the rectangle which is being mapped?
 579                 */
 580                 /* XXX: when discard is true, no need to read back from depth texture
 581                 */
 582                 r = r600_texture_depth_flush(ctx, texture);
 583                 if (r < 0) {
 584                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 585                         pipe_resource_reference(&trans->transfer.resource, NULL);
 586                         FREE(trans);
 587                         return NULL;
 588                 }
 589         } else if (use_staging_texture) {
 590                 resource.target = PIPE_TEXTURE_2D;
 591                 resource.format = texture->format;
 592                 resource.width0 = box->width;
 593                 resource.height0 = box->height;
 594                 resource.depth0 = 1;
 595                 resource.array_size = 1;
 596                 resource.last_level = 0;
 597                 resource.nr_samples = 0;
 598                 resource.usage = PIPE_USAGE_STAGING;
 599                 resource.bind = 0;
 600                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 601                 /* For texture reading, the temporary (detiled) texture is used as
 602                  * a render target when blitting from a tiled texture. */
 603                 if (usage & PIPE_TRANSFER_READ) {
 604                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 605                 }
 606                 /* For texture writing, the temporary texture is used as a sampler
 607                  * when blitting into a tiled texture. */
 608                 if (usage & PIPE_TRANSFER_WRITE) {
 609                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 610                 }
 611                 /* Create the temporary texture. */
 612                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 613                 if (trans->staging_texture == NULL) {
 614                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 615                         pipe_resource_reference(&trans->transfer.resource, NULL);
 616                         FREE(trans);
 617                         return NULL;
 618                 }
 619
 620                 trans->transfer.stride =
 621                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 622                 if (usage & PIPE_TRANSFER_READ) {
 623                         r600_copy_to_staging_texture(ctx, trans);
 624                         /* Always referenced in the blit. */
 625                         ctx->flush(ctx, 0, NULL);
 626                 }
 627                 return &trans->transfer;
 628         }
 629         trans->transfer.stride = rtex->pitch_in_bytes[level];
 630         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 631         return &trans->transfer;
 632 }
 633
 634 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 635                                    struct pipe_transfer *transfer)
 636 {
 637         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 638         struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 639
 640         if (rtransfer->staging_texture) {
 641                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 642                         r600_copy_from_staging_texture(ctx, rtransfer);
 643                 }
 644                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 645         }
 646         if (rtex->flushed_depth_texture) {
 647                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 648         }
 649         pipe_resource_reference(&transfer->resource, NULL);
 650         FREE(transfer);
 651 }
 652
 653 void* r600_texture_transfer_map(struct pipe_context *ctx,
 654                                 struct pipe_transfer* transfer)
 655 {
 656         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 657         struct r600_bo *bo;
 658         enum pipe_format format = transfer->resource->format;
 659         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 660         unsigned offset = 0;
 661         unsigned usage = 0;
 662         char *map;
 663
 664         if (rtransfer->staging_texture) {
 665                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 666         } else {
 667                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 668
 669                 if (rtex->flushed_depth_texture)
 670                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 671                 else
 672                         bo = ((struct r600_resource *)transfer->resource)->bo;
 673
 674                 offset = rtransfer->offset +
 675                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 676                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 677         }
 678
 679         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 680                 usage |= PB_USAGE_CPU_WRITE;
 681
 682                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 683                 }
 684
 685                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 686                 }
 687         }
 688
 689         if (transfer->usage & PIPE_TRANSFER_READ) {
 690                 usage |= PB_USAGE_CPU_READ;
 691         }
 692
 693         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 694                 usage |= PB_USAGE_DONTBLOCK;
 695         }
 696
 697         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 698                 usage |= PB_USAGE_UNSYNCHRONIZED;
 699         }
 700
 701         map = r600_bo_map(radeon, bo, usage, ctx);
 702         if (!map) {
 703                 return NULL;
 704         }
 705
 706         return map + offset;
 707 }
 708
 709 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 710                                  struct pipe_transfer* transfer)
 711 {
 712         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 713         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 714         struct r600_bo *bo;
 715
 716         if (rtransfer->staging_texture) {
 717                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 718         } else {
 719                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 720
 721                 if (rtex->flushed_depth_texture) {
 722                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 723                 } else {
 724                         bo = ((struct r600_resource *)transfer->resource)->bo;
 725                 }
 726         }
 727         r600_bo_unmap(radeon, bo);
 728 }
 729
 730 struct u_resource_vtbl r600_texture_vtbl =
 731 {
 732         r600_texture_get_handle,        /* get_handle */
 733         r600_texture_destroy,           /* resource_destroy */
 734         r600_texture_is_referenced,     /* is_resource_referenced */
 735         r600_texture_get_transfer,      /* get_transfer */
 736         r600_texture_transfer_destroy,  /* transfer_destroy */
 737         r600_texture_transfer_map,      /* transfer_map */
 738         u_default_transfer_flush_region,/* transfer_flush_region */
 739         r600_texture_transfer_unmap,    /* transfer_unmap */
 740         u_default_transfer_inline_write /* transfer_inline_write */
 741 };
 742
 743 void r600_init_surface_functions(struct r600_pipe_context *r600)
 744 {
 745         r600->context.create_surface = r600_create_surface;
 746         r600->context.surface_destroy = r600_surface_destroy;
 747 }
 748
 749 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 750                 const unsigned char *swizzle_view)
 751 {
 752         unsigned i;
 753         unsigned char swizzle[4];
 754         unsigned result = 0;
 755         const uint32_t swizzle_shift[4] = {
 756                 16, 19, 22, 25,
 757         };
 758         const uint32_t swizzle_bit[4] = {
 759                 0, 1, 2, 3,
 760         };
 761
 762         if (swizzle_view) {
 763                 /* Combine two sets of swizzles. */
 764                 for (i = 0; i < 4; i++) {
 765                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 766                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 767                 }
 768         } else {
 769                 memcpy(swizzle, swizzle_format, 4);
 770         }
 771
 772         /* Get swizzle. */
 773         for (i = 0; i < 4; i++) {
 774                 switch (swizzle[i]) {
 775                 case UTIL_FORMAT_SWIZZLE_Y:
 776                         result |= swizzle_bit[1] << swizzle_shift[i];
 777                         break;
 778                 case UTIL_FORMAT_SWIZZLE_Z:
 779                         result |= swizzle_bit[2] << swizzle_shift[i];
 780                         break;
 781                 case UTIL_FORMAT_SWIZZLE_W:
 782                         result |= swizzle_bit[3] << swizzle_shift[i];
 783                         break;
 784                 case UTIL_FORMAT_SWIZZLE_0:
 785                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 786                         break;
 787                 case UTIL_FORMAT_SWIZZLE_1:
 788                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 789                         break;
 790                 default: /* UTIL_FORMAT_SWIZZLE_X */
 791                         result |= swizzle_bit[0] << swizzle_shift[i];
 792                 }
 793         }
 794         return result;
 795 }
 796
 797 /* texture format translate */
 798 uint32_t r600_translate_texformat(enum pipe_format format,
 799                                   const unsigned char *swizzle_view,
 800                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 801 {
 802         uint32_t result = 0, word4 = 0, yuv_format = 0;
 803         const struct util_format_description *desc;
 804         boolean uniform = TRUE;
 805         int i;
 806         const uint32_t sign_bit[4] = {
 807                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 808                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 809                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 810                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 811         };
 812         desc = util_format_description(format);
 813
 814         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 815
 816         /* Colorspace (return non-RGB formats directly). */
 817         switch (desc->colorspace) {
 818                 /* Depth stencil formats */
 819         case UTIL_FORMAT_COLORSPACE_ZS:
 820                 switch (format) {
 821                 case PIPE_FORMAT_Z16_UNORM:
 822                         result = FMT_16;
 823                         goto out_word4;
 824                 case PIPE_FORMAT_X24S8_USCALED:
 825                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 826                 case PIPE_FORMAT_Z24X8_UNORM:
 827                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 828                         result = FMT_8_24;
 829                         goto out_word4;
 830                 case PIPE_FORMAT_S8X24_USCALED:
 831                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 832                 case PIPE_FORMAT_X8Z24_UNORM:
 833                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 834                         result = FMT_24_8;
 835                         goto out_word4;
 836                 case PIPE_FORMAT_S8_USCALED:
 837                         result = FMT_8;
 838                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 839                         goto out_word4;
 840                 default:
 841                         goto out_unknown;
 842                 }
 843
 844         case UTIL_FORMAT_COLORSPACE_YUV:
 845                 yuv_format |= (1 << 30);
 846                 switch (format) {
 847                 case PIPE_FORMAT_UYVY:
 848                 case PIPE_FORMAT_YUYV:
 849                 default:
 850                         break;
 851                 }
 852                 goto out_unknown; /* TODO */
 853
 854         case UTIL_FORMAT_COLORSPACE_SRGB:
 855                 word4 |= S_038010_FORCE_DEGAMMA(1);
 856                 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
 857                         goto out_unknown; /* fails for some reason - TODO */
 858                 break;
 859
 860         default:
 861                 break;
 862         }
 863
 864         /* S3TC formats. TODO */
 865         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 866                 static int r600_enable_s3tc = -1;
 867
 868                 if (r600_enable_s3tc == -1)
 869                         r600_enable_s3tc =
 870                                 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 871
 872                 if (!r600_enable_s3tc)
 873                         goto out_unknown;
 874
 875                 switch (format) {
 876                 case PIPE_FORMAT_DXT1_RGB:
 877                 case PIPE_FORMAT_DXT1_RGBA:
 878                         result = FMT_BC1;
 879                         goto out_word4;
 880                 case PIPE_FORMAT_DXT3_RGBA:
 881                         result = FMT_BC2;
 882                         goto out_word4;
 883                 case PIPE_FORMAT_DXT5_RGBA:
 884                         result = FMT_BC3;
 885                         goto out_word4;
 886                 default:
 887                         goto out_unknown;
 888                 }
 889         }
 890
 891
 892         for (i = 0; i < desc->nr_channels; i++) {
 893                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 894                         word4 |= sign_bit[i];
 895                 }
 896         }
 897
 898         /* R8G8Bx_SNORM - TODO CxV8U8 */
 899
 900         /* RGTC - TODO */
 901
 902         /* See whether the components are of the same size. */
 903         for (i = 1; i < desc->nr_channels; i++) {
 904                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 905         }
 906
 907         /* Non-uniform formats. */
 908         if (!uniform) {
 909                 switch(desc->nr_channels) {
 910                 case 3:
 911                         if (desc->channel[0].size == 5 &&
 912                             desc->channel[1].size == 6 &&
 913                             desc->channel[2].size == 5) {
 914                                 result = FMT_5_6_5;
 915                                 goto out_word4;
 916                         }
 917                         goto out_unknown;
 918                 case 4:
 919                         if (desc->channel[0].size == 5 &&
 920                             desc->channel[1].size == 5 &&
 921                             desc->channel[2].size == 5 &&
 922                             desc->channel[3].size == 1) {
 923                                 result = FMT_1_5_5_5;
 924                                 goto out_word4;
 925                         }
 926                         if (desc->channel[0].size == 10 &&
 927                             desc->channel[1].size == 10 &&
 928                             desc->channel[2].size == 10 &&
 929                             desc->channel[3].size == 2) {
 930                                 result = FMT_10_10_10_2;
 931                                 goto out_word4;
 932                         }
 933                         goto out_unknown;
 934                 }
 935                 goto out_unknown;
 936         }
 937
 938         /* Find the first non-VOID channel. */
 939         for (i = 0; i < 4; i++) {
 940                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 941                         break;
 942                 }
 943         }
 944
 945         if (i == 4)
 946                 goto out_unknown;
 947
 948         /* uniform formats */
 949         switch (desc->channel[i].type) {
 950         case UTIL_FORMAT_TYPE_UNSIGNED:
 951         case UTIL_FORMAT_TYPE_SIGNED:
 952                 if (!desc->channel[i].normalized &&
 953                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 954                         goto out_unknown;
 955                 }
 956
 957                 switch (desc->channel[i].size) {
 958                 case 4:
 959                         switch (desc->nr_channels) {
 960                         case 2:
 961                                 result = FMT_4_4;
 962                                 goto out_word4;
 963                         case 4:
 964                                 result = FMT_4_4_4_4;
 965                                 goto out_word4;
 966                         }
 967                         goto out_unknown;
 968                 case 8:
 969                         switch (desc->nr_channels) {
 970                         case 1:
 971                                 result = FMT_8;
 972                                 goto out_word4;
 973                         case 2:
 974                                 result = FMT_8_8;
 975                                 goto out_word4;
 976                         case 4:
 977                                 result = FMT_8_8_8_8;
 978                                 goto out_word4;
 979                         }
 980                         goto out_unknown;
 981                 case 16:
 982                         switch (desc->nr_channels) {
 983                         case 1:
 984                                 result = FMT_16;
 985                                 goto out_word4;
 986                         case 2:
 987                                 result = FMT_16_16;
 988                                 goto out_word4;
 989                         case 4:
 990                                 result = FMT_16_16_16_16;
 991                                 goto out_word4;
 992                         }
 993                 }
 994                 goto out_unknown;
 995
 996         case UTIL_FORMAT_TYPE_FLOAT:
 997                 switch (desc->channel[i].size) {
 998                 case 16:
 999                         switch (desc->nr_channels) {
1000                         case 1:
1001                                 result = FMT_16_FLOAT;
1002                                 goto out_word4;
1003                         case 2:
1004                                 result = FMT_16_16_FLOAT;
1005                                 goto out_word4;
1006                         case 4:
1007                                 result = FMT_16_16_16_16_FLOAT;
1008                                 goto out_word4;
1009                         }
1010                         goto out_unknown;
1011                 case 32:
1012                         switch (desc->nr_channels) {
1013                         case 1:
1014                                 result = FMT_32_FLOAT;
1015                                 goto out_word4;
1016                         case 2:
1017                                 result = FMT_32_32_FLOAT;
1018                                 goto out_word4;
1019                         case 4:
1020                                 result = FMT_32_32_32_32_FLOAT;
1021                                 goto out_word4;
1022                         }
1023                 }
1024
1025         }
1026 out_word4:
1027         if (word4_p)
1028                 *word4_p = word4;
1029         if (yuv_format_p)
1030                 *yuv_format_p = yuv_format;
1031         return result;
1032 out_unknown:
1033 //      R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1034         return ~0;
1035 }