src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_math.h>
  31 #include <util/u_inlines.h>
  32 #include <util/u_memory.h>
  33 #include "state_tracker/drm_driver.h"
  34 #include "pipebuffer/pb_buffer.h"
  35 #include "r600_pipe.h"
  36 #include "r600_resource.h"
  37 #include "r600_state_inlines.h"
  38 #include "r600d.h"
  39 #include "r600_formats.h"
  40
  41 /* Copy from a full GPU texture to a transfer's staging one. */
  42 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  43 {
  44         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  45         struct pipe_resource *texture = transfer->resource;
  46
  47         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  48                                 0, 0, 0, 0, texture, transfer->level,
  49                                 &transfer->box);
  50 }
  51
  52
  53 /* Copy from a transfer's staging texture to a full GPU one. */
  54 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  55 {
  56         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  57         struct pipe_resource *texture = transfer->resource;
  58         struct pipe_box sbox;
  59
  60         sbox.x = sbox.y = sbox.z = 0;
  61         sbox.width = transfer->box.width;
  62         sbox.height = transfer->box.height;
  63         /* XXX that might be wrong */
  64         sbox.depth = 1;
  65         ctx->resource_copy_region(ctx, texture, transfer->level,
  66                                   transfer->box.x, transfer->box.y, transfer->box.z,
  67                                   rtransfer->staging_texture,
  68                                   0, &sbox);
  69
  70         ctx->flush(ctx, 0, NULL);
  71 }
  72
  73 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  74                                         unsigned level, unsigned layer)
  75 {
  76         unsigned offset = rtex->offset[level];
  77
  78         switch (rtex->resource.b.b.b.target) {
  79         case PIPE_TEXTURE_3D:
  80         case PIPE_TEXTURE_CUBE:
  81                 return offset + layer * rtex->layer_size[level];
  82         default:
  83                 assert(layer == 0);
  84                 return offset;
  85         }
  86 }
  87
  88 static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
  89                                          enum pipe_format format,
  90                                          unsigned array_mode)
  91 {
  92         struct r600_screen* rscreen = (struct r600_screen *)screen;
  93         unsigned pixsize = util_format_get_blocksize(format);
  94         int p_align;
  95
  96         switch(array_mode) {
  97         case V_038000_ARRAY_1D_TILED_THIN1:
  98                 p_align = MAX2(8,
  99                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
 100                 break;
 101         case V_038000_ARRAY_2D_TILED_THIN1:
 102                 p_align = MAX2(rscreen->tiling_info->num_banks,
 103                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 104                                 rscreen->tiling_info->num_banks)) * 8;
 105                 break;
 106         case V_038000_ARRAY_LINEAR_GENERAL:
 107         default:
 108                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 109                 break;
 110         }
 111         return p_align;
 112 }
 113
 114 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 115                                           unsigned array_mode)
 116 {
 117         struct r600_screen* rscreen = (struct r600_screen *)screen;
 118         int h_align;
 119
 120         switch (array_mode) {
 121         case V_038000_ARRAY_2D_TILED_THIN1:
 122                 h_align = rscreen->tiling_info->num_channels * 8;
 123                 break;
 124         case V_038000_ARRAY_1D_TILED_THIN1:
 125                 h_align = 8;
 126                 break;
 127         default:
 128                 h_align = 1;
 129                 break;
 130         }
 131         return h_align;
 132 }
 133
 134 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 135                                         enum pipe_format format,
 136                                         unsigned array_mode)
 137 {
 138         struct r600_screen* rscreen = (struct r600_screen *)screen;
 139         unsigned pixsize = util_format_get_blocksize(format);
 140         int p_align = r600_get_pixel_alignment(screen, format, array_mode);
 141         int h_align = r600_get_height_alignment(screen, array_mode);
 142         int b_align;
 143
 144         switch (array_mode) {
 145         case V_038000_ARRAY_2D_TILED_THIN1:
 146                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 147                                p_align * pixsize * h_align);
 148                 break;
 149         case V_038000_ARRAY_1D_TILED_THIN1:
 150         default:
 151                 b_align = rscreen->tiling_info->group_bytes;
 152                 break;
 153         }
 154         return b_align;
 155 }
 156
 157 static unsigned mip_minify(unsigned size, unsigned level)
 158 {
 159         unsigned val;
 160         val = u_minify(size, level);
 161         if (level > 0)
 162                 val = util_next_power_of_two(val);
 163         return val;
 164 }
 165
 166 static unsigned r600_texture_get_stride(struct pipe_screen *screen,
 167                                         struct r600_resource_texture *rtex,
 168                                         unsigned level)
 169 {
 170         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 171         unsigned width, stride, tile_width;
 172
 173         if (rtex->pitch_override)
 174                 return rtex->pitch_override;
 175
 176         width = mip_minify(ptex->width0, level);
 177         if (util_format_is_plain(ptex->format)) {
 178                 tile_width = r600_get_pixel_alignment(screen, ptex->format,
 179                                                       rtex->array_mode[level]);
 180                 width = align(width, tile_width);
 181         }
 182         stride = util_format_get_stride(ptex->format, width);
 183
 184         return stride;
 185 }
 186
 187 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 188                                           struct r600_resource_texture *rtex,
 189                                           unsigned level)
 190 {
 191         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 192         unsigned height, tile_height;
 193
 194         height = mip_minify(ptex->height0, level);
 195         if (util_format_is_plain(ptex->format)) {
 196                 tile_height = r600_get_height_alignment(screen,
 197                                                         rtex->array_mode[level]);
 198                 height = align(height, tile_height);
 199         }
 200         return util_format_get_nblocksy(ptex->format, height);
 201 }
 202
 203 /* Get a width in pixels from a stride in bytes. */
 204 static unsigned pitch_to_width(enum pipe_format format, unsigned pitch_in_bytes)
 205 {
 206         return (pitch_in_bytes / util_format_get_blocksize(format)) *
 207                 util_format_get_blockwidth(format);
 208 }
 209
 210 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 211                                         struct r600_resource_texture *rtex,
 212                                         unsigned level, unsigned array_mode)
 213 {
 214         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 215
 216         switch (array_mode) {
 217         case V_0280A0_ARRAY_LINEAR_GENERAL:
 218         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 219         case V_0280A0_ARRAY_1D_TILED_THIN1:
 220         default:
 221                 rtex->array_mode[level] = array_mode;
 222                 break;
 223         case V_0280A0_ARRAY_2D_TILED_THIN1:
 224         {
 225                 unsigned w, h, tile_height, tile_width;
 226
 227                 tile_height = r600_get_height_alignment(screen, array_mode);
 228                 tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode);
 229
 230                 w = mip_minify(ptex->width0, level);
 231                 h = mip_minify(ptex->height0, level);
 232                 if (w < tile_width || h < tile_height)
 233                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 234                 else
 235                         rtex->array_mode[level] = array_mode;
 236         }
 237         break;
 238         }
 239 }
 240
 241 static void r600_setup_miptree(struct pipe_screen *screen,
 242                                struct r600_resource_texture *rtex,
 243                                unsigned array_mode)
 244 {
 245         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 246         struct radeon *radeon = (struct radeon *)screen->winsys;
 247         enum chip_class chipc = r600_get_family_class(radeon);
 248         unsigned pitch, size, layer_size, i, offset;
 249         unsigned nblocksy;
 250
 251         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 252                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 253
 254                 pitch = r600_texture_get_stride(screen, rtex, i);
 255                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 256
 257                 layer_size = pitch * nblocksy;
 258
 259                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 260                         if (chipc >= R700)
 261                                 size = layer_size * 8;
 262                         else
 263                                 size = layer_size * 6;
 264                 }
 265                 else
 266                         size = layer_size * u_minify(ptex->depth0, i);
 267                 /* align base image and start of miptree */
 268                 if ((i == 0) || (i == 1))
 269                         offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
 270                 rtex->offset[i] = offset;
 271                 rtex->layer_size[i] = layer_size;
 272                 rtex->pitch_in_bytes[i] = pitch;
 273                 rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
 274                 offset += size;
 275         }
 276         rtex->size = offset;
 277 }
 278
 279 /* Figure out whether u_blitter will fallback to a transfer operation.
 280  * If so, don't use a staging resource.
 281  */
 282 static boolean permit_hardware_blit(struct pipe_screen *screen,
 283                                         const struct pipe_resource *res)
 284 {
 285         unsigned bind;
 286
 287         if (util_format_is_depth_or_stencil(res->format))
 288                 bind = PIPE_BIND_DEPTH_STENCIL;
 289         else
 290                 bind = PIPE_BIND_RENDER_TARGET;
 291
 292         if (!screen->is_format_supported(screen,
 293                                 res->format,
 294                                 res->target,
 295                                 res->nr_samples,
 296                                 bind, 0))
 297                 return FALSE;
 298
 299         if (!screen->is_format_supported(screen,
 300                                 res->format,
 301                                 res->target,
 302                                 res->nr_samples,
 303                                 PIPE_BIND_SAMPLER_VIEW, 0))
 304                 return FALSE;
 305
 306         return TRUE;
 307 }
 308
 309 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 310                                         struct pipe_resource *ptex,
 311                                         struct winsys_handle *whandle)
 312 {
 313         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 314         struct r600_resource *resource = &rtex->resource;
 315         struct radeon *radeon = (struct radeon *)screen->winsys;
 316
 317         return r600_bo_get_winsys_handle(radeon, resource->bo,
 318                         rtex->pitch_in_bytes[0], whandle);
 319 }
 320
 321 static void r600_texture_destroy(struct pipe_screen *screen,
 322                                  struct pipe_resource *ptex)
 323 {
 324         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 325         struct r600_resource *resource = &rtex->resource;
 326         struct radeon *radeon = (struct radeon *)screen->winsys;
 327
 328         if (rtex->flushed_depth_texture)
 329                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 330
 331         if (resource->bo) {
 332                 r600_bo_reference(radeon, &resource->bo, NULL);
 333         }
 334         FREE(rtex);
 335 }
 336
 337 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 338                                                 struct pipe_resource *texture,
 339                                                 unsigned level, int layer)
 340 {
 341         /* FIXME */
 342         return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 343 }
 344
 345 static const struct u_resource_vtbl r600_texture_vtbl =
 346 {
 347         r600_texture_get_handle,        /* get_handle */
 348         r600_texture_destroy,           /* resource_destroy */
 349         r600_texture_is_referenced,     /* is_resource_referenced */
 350         r600_texture_get_transfer,      /* get_transfer */
 351         r600_texture_transfer_destroy,  /* transfer_destroy */
 352         r600_texture_transfer_map,      /* transfer_map */
 353         u_default_transfer_flush_region,/* transfer_flush_region */
 354         r600_texture_transfer_unmap,    /* transfer_unmap */
 355         u_default_transfer_inline_write /* transfer_inline_write */
 356 };
 357
 358 static struct r600_resource_texture *
 359 r600_texture_create_object(struct pipe_screen *screen,
 360                            const struct pipe_resource *base,
 361                            unsigned array_mode,
 362                            unsigned pitch_in_bytes_override,
 363                            unsigned max_buffer_size,
 364                            struct r600_bo *bo)
 365 {
 366         struct r600_resource_texture *rtex;
 367         struct r600_resource *resource;
 368         struct radeon *radeon = (struct radeon *)screen->winsys;
 369
 370         rtex = CALLOC_STRUCT(r600_resource_texture);
 371         if (rtex == NULL)
 372                 return NULL;
 373
 374         resource = &rtex->resource;
 375         resource->b.b.b = *base;
 376         resource->b.b.vtbl = &r600_texture_vtbl;
 377         pipe_reference_init(&resource->b.b.b.reference, 1);
 378         resource->b.b.b.screen = screen;
 379         resource->bo = bo;
 380         rtex->pitch_override = pitch_in_bytes_override;
 381         /* only mark depth textures the HW can hit as depth textures */
 382         if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
 383                 rtex->depth = 1;
 384
 385         if (array_mode)
 386                 rtex->tiled = 1;
 387         r600_setup_miptree(screen, rtex, array_mode);
 388
 389         resource->size = rtex->size;
 390
 391         if (!resource->bo) {
 392                 struct pipe_resource *ptex = &rtex->resource.b.b.b;
 393                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 394
 395                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 396                 if (!resource->bo) {
 397                         FREE(rtex);
 398                         return NULL;
 399                 }
 400         }
 401         return rtex;
 402 }
 403
 404 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 405                                                 const struct pipe_resource *templ)
 406 {
 407         unsigned array_mode = 0;
 408         static int force_tiling = -1;
 409
 410         /* Would like some magic "get_bool_option_once" routine.
 411          */
 412         if (force_tiling == -1)
 413                 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
 414
 415         if (force_tiling && permit_hardware_blit(screen, templ)) {
 416                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 417                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 418                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 419                 }
 420         }
 421
 422         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 423                                                                   0, 0, NULL);
 424
 425 }
 426
 427 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 428                                                 struct pipe_resource *texture,
 429                                                 const struct pipe_surface *surf_tmpl)
 430 {
 431         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 432         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 433         unsigned tile_height;
 434         unsigned level = surf_tmpl->u.tex.level;
 435
 436         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 437         if (surface == NULL)
 438                 return NULL;
 439         /* XXX no offset */
 440 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 441         pipe_reference_init(&surface->base.reference, 1);
 442         pipe_resource_reference(&surface->base.texture, texture);
 443         surface->base.context = pipe;
 444         surface->base.format = surf_tmpl->format;
 445         surface->base.width = mip_minify(texture->width0, level);
 446         surface->base.height = mip_minify(texture->height0, level);
 447         surface->base.usage = surf_tmpl->usage;
 448         surface->base.texture = texture;
 449         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 450         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 451         surface->base.u.tex.level = level;
 452
 453         tile_height = r600_get_height_alignment(pipe->screen, rtex->array_mode[level]);
 454         surface->aligned_height = align(surface->base.height, tile_height);
 455         return &surface->base;
 456 }
 457
 458 static void r600_surface_destroy(struct pipe_context *pipe,
 459                                  struct pipe_surface *surface)
 460 {
 461         pipe_resource_reference(&surface->texture, NULL);
 462         FREE(surface);
 463 }
 464
 465
 466 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 467                                                const struct pipe_resource *templ,
 468                                                struct winsys_handle *whandle)
 469 {
 470         struct radeon *rw = (struct radeon*)screen->winsys;
 471         struct r600_bo *bo = NULL;
 472         unsigned array_mode = 0;
 473
 474         /* Support only 2D textures without mipmaps */
 475         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 476               templ->depth0 != 1 || templ->last_level != 0)
 477                 return NULL;
 478
 479         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 480         if (bo == NULL) {
 481                 return NULL;
 482         }
 483
 484         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 485                                                                   whandle->stride,
 486                                                                   0,
 487                                                                   bo);
 488 }
 489
 490 int r600_texture_depth_flush(struct pipe_context *ctx,
 491                              struct pipe_resource *texture, boolean just_create)
 492 {
 493         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 494         struct pipe_resource resource;
 495
 496         if (rtex->flushed_depth_texture)
 497                 goto out;
 498
 499         resource.target = PIPE_TEXTURE_2D;
 500         resource.format = texture->format;
 501         resource.width0 = texture->width0;
 502         resource.height0 = texture->height0;
 503         resource.depth0 = 1;
 504         resource.last_level = texture->last_level;
 505         resource.nr_samples = 0;
 506         resource.usage = PIPE_USAGE_DYNAMIC;
 507         resource.bind = 0;
 508         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 509
 510         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 511
 512         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 513         if (rtex->flushed_depth_texture == NULL) {
 514                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 515                 return -ENOMEM;
 516         }
 517
 518         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 519 out:
 520         if (just_create)
 521                 return 0;
 522
 523         /* XXX: only do this if the depth texture has actually changed:
 524          */
 525         r600_blit_uncompress_depth(ctx, rtex);
 526         return 0;
 527 }
 528
 529 /* Needs adjustment for pixelformat:
 530  */
 531 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 532 {
 533         return box->width * box->depth * box->height;
 534 };
 535
 536 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 537                                                 struct pipe_resource *texture,
 538                                                 unsigned level,
 539                                                 unsigned usage,
 540                                                 const struct pipe_box *box)
 541 {
 542         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 543         struct pipe_resource resource;
 544         struct r600_transfer *trans;
 545         int r;
 546         boolean use_staging_texture = FALSE;
 547
 548         /* We cannot map a tiled texture directly because the data is
 549          * in a different order, therefore we do detiling using a blit.
 550          *
 551          * Also, use a temporary in GTT memory for read transfers, as
 552          * the CPU is much happier reading out of cached system memory
 553          * than uncached VRAM.
 554          */
 555         if (rtex->tiled)
 556                 use_staging_texture = TRUE;
 557
 558         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 559                 use_staging_texture = TRUE;
 560
 561         /* XXX: Use a staging texture for uploads if the underlying BO
 562          * is busy.  No interface for checking that currently? so do
 563          * it eagerly whenever the transfer doesn't require a readback
 564          * and might block.
 565          */
 566         if ((usage & PIPE_TRANSFER_WRITE) &&
 567                         !(usage & (PIPE_TRANSFER_READ |
 568                                         PIPE_TRANSFER_DONTBLOCK |
 569                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 570                 use_staging_texture = TRUE;
 571
 572         if (!permit_hardware_blit(ctx->screen, texture) ||
 573                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 574                 use_staging_texture = FALSE;
 575
 576         trans = CALLOC_STRUCT(r600_transfer);
 577         if (trans == NULL)
 578                 return NULL;
 579         pipe_resource_reference(&trans->transfer.resource, texture);
 580         trans->transfer.level = level;
 581         trans->transfer.usage = usage;
 582         trans->transfer.box = *box;
 583         if (rtex->depth) {
 584                 /* XXX: only readback the rectangle which is being mapped?
 585                 */
 586                 /* XXX: when discard is true, no need to read back from depth texture
 587                 */
 588                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 589                 if (r < 0) {
 590                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 591                         pipe_resource_reference(&trans->transfer.resource, NULL);
 592                         FREE(trans);
 593                         return NULL;
 594                 }
 595                 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
 596                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 597                 return &trans->transfer;
 598         } else if (use_staging_texture) {
 599                 resource.target = PIPE_TEXTURE_2D;
 600                 resource.format = texture->format;
 601                 resource.width0 = box->width;
 602                 resource.height0 = box->height;
 603                 resource.depth0 = 1;
 604                 resource.array_size = 1;
 605                 resource.last_level = 0;
 606                 resource.nr_samples = 0;
 607                 resource.usage = PIPE_USAGE_STAGING;
 608                 resource.bind = 0;
 609                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 610                 /* For texture reading, the temporary (detiled) texture is used as
 611                  * a render target when blitting from a tiled texture. */
 612                 if (usage & PIPE_TRANSFER_READ) {
 613                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 614                 }
 615                 /* For texture writing, the temporary texture is used as a sampler
 616                  * when blitting into a tiled texture. */
 617                 if (usage & PIPE_TRANSFER_WRITE) {
 618                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 619                 }
 620                 /* Create the temporary texture. */
 621                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 622                 if (trans->staging_texture == NULL) {
 623                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 624                         pipe_resource_reference(&trans->transfer.resource, NULL);
 625                         FREE(trans);
 626                         return NULL;
 627                 }
 628
 629                 trans->transfer.stride =
 630                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 631                 if (usage & PIPE_TRANSFER_READ) {
 632                         r600_copy_to_staging_texture(ctx, trans);
 633                         /* Always referenced in the blit. */
 634                         ctx->flush(ctx, 0, NULL);
 635                 }
 636                 return &trans->transfer;
 637         }
 638         trans->transfer.stride = rtex->pitch_in_bytes[level];
 639         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 640         return &trans->transfer;
 641 }
 642
 643 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 644                                    struct pipe_transfer *transfer)
 645 {
 646         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 647         struct pipe_resource *texture = transfer->resource;
 648         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 649
 650         if (rtransfer->staging_texture) {
 651                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 652                         r600_copy_from_staging_texture(ctx, rtransfer);
 653                 }
 654                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 655         }
 656
 657         if (rtex->depth && !rtex->is_flushing_texture) {
 658                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 659                         r600_blit_push_depth(ctx, rtex);
 660         }
 661
 662         pipe_resource_reference(&transfer->resource, NULL);
 663         FREE(transfer);
 664 }
 665
 666 void* r600_texture_transfer_map(struct pipe_context *ctx,
 667                                 struct pipe_transfer* transfer)
 668 {
 669         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 670         struct r600_bo *bo;
 671         enum pipe_format format = transfer->resource->format;
 672         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 673         unsigned offset = 0;
 674         unsigned usage = 0;
 675         char *map;
 676
 677         if (rtransfer->staging_texture) {
 678                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 679         } else {
 680                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 681
 682                 if (rtex->flushed_depth_texture)
 683                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 684                 else
 685                         bo = ((struct r600_resource *)transfer->resource)->bo;
 686
 687                 offset = rtransfer->offset +
 688                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 689                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 690         }
 691
 692         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 693                 usage |= PB_USAGE_CPU_WRITE;
 694
 695                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 696                 }
 697
 698                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 699                 }
 700         }
 701
 702         if (transfer->usage & PIPE_TRANSFER_READ) {
 703                 usage |= PB_USAGE_CPU_READ;
 704         }
 705
 706         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 707                 usage |= PB_USAGE_DONTBLOCK;
 708         }
 709
 710         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 711                 usage |= PB_USAGE_UNSYNCHRONIZED;
 712         }
 713
 714         map = r600_bo_map(radeon, bo, usage, ctx);
 715         if (!map) {
 716                 return NULL;
 717         }
 718
 719         return map + offset;
 720 }
 721
 722 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 723                                  struct pipe_transfer* transfer)
 724 {
 725         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 726         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 727         struct r600_bo *bo;
 728
 729         if (rtransfer->staging_texture) {
 730                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 731         } else {
 732                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 733
 734                 if (rtex->flushed_depth_texture) {
 735                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 736                 } else {
 737                         bo = ((struct r600_resource *)transfer->resource)->bo;
 738                 }
 739         }
 740         r600_bo_unmap(radeon, bo);
 741 }
 742
 743 void r600_init_surface_functions(struct r600_pipe_context *r600)
 744 {
 745         r600->context.create_surface = r600_create_surface;
 746         r600->context.surface_destroy = r600_surface_destroy;
 747 }
 748
 749 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 750                 const unsigned char *swizzle_view)
 751 {
 752         unsigned i;
 753         unsigned char swizzle[4];
 754         unsigned result = 0;
 755         const uint32_t swizzle_shift[4] = {
 756                 16, 19, 22, 25,
 757         };
 758         const uint32_t swizzle_bit[4] = {
 759                 0, 1, 2, 3,
 760         };
 761
 762         if (swizzle_view) {
 763                 /* Combine two sets of swizzles. */
 764                 for (i = 0; i < 4; i++) {
 765                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 766                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 767                 }
 768         } else {
 769                 memcpy(swizzle, swizzle_format, 4);
 770         }
 771
 772         /* Get swizzle. */
 773         for (i = 0; i < 4; i++) {
 774                 switch (swizzle[i]) {
 775                 case UTIL_FORMAT_SWIZZLE_Y:
 776                         result |= swizzle_bit[1] << swizzle_shift[i];
 777                         break;
 778                 case UTIL_FORMAT_SWIZZLE_Z:
 779                         result |= swizzle_bit[2] << swizzle_shift[i];
 780                         break;
 781                 case UTIL_FORMAT_SWIZZLE_W:
 782                         result |= swizzle_bit[3] << swizzle_shift[i];
 783                         break;
 784                 case UTIL_FORMAT_SWIZZLE_0:
 785                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 786                         break;
 787                 case UTIL_FORMAT_SWIZZLE_1:
 788                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 789                         break;
 790                 default: /* UTIL_FORMAT_SWIZZLE_X */
 791                         result |= swizzle_bit[0] << swizzle_shift[i];
 792                 }
 793         }
 794         return result;
 795 }
 796
 797 /* texture format translate */
 798 uint32_t r600_translate_texformat(enum pipe_format format,
 799                                   const unsigned char *swizzle_view,
 800                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 801 {
 802         uint32_t result = 0, word4 = 0, yuv_format = 0;
 803         const struct util_format_description *desc;
 804         boolean uniform = TRUE;
 805         int i;
 806         const uint32_t sign_bit[4] = {
 807                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 808                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 809                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 810                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 811         };
 812         desc = util_format_description(format);
 813
 814         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 815
 816         /* Colorspace (return non-RGB formats directly). */
 817         switch (desc->colorspace) {
 818                 /* Depth stencil formats */
 819         case UTIL_FORMAT_COLORSPACE_ZS:
 820                 switch (format) {
 821                 case PIPE_FORMAT_Z16_UNORM:
 822                         result = FMT_16;
 823                         goto out_word4;
 824                 case PIPE_FORMAT_X24S8_USCALED:
 825                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 826                 case PIPE_FORMAT_Z24X8_UNORM:
 827                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 828                         result = FMT_8_24;
 829                         goto out_word4;
 830                 case PIPE_FORMAT_S8X24_USCALED:
 831                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 832                 case PIPE_FORMAT_X8Z24_UNORM:
 833                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 834                         result = FMT_24_8;
 835                         goto out_word4;
 836                 case PIPE_FORMAT_S8_USCALED:
 837                         result = FMT_8;
 838                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 839                         goto out_word4;
 840                 default:
 841                         goto out_unknown;
 842                 }
 843
 844         case UTIL_FORMAT_COLORSPACE_YUV:
 845                 yuv_format |= (1 << 30);
 846                 switch (format) {
 847                 case PIPE_FORMAT_UYVY:
 848                 case PIPE_FORMAT_YUYV:
 849                 default:
 850                         break;
 851                 }
 852                 goto out_unknown; /* TODO */
 853
 854         case UTIL_FORMAT_COLORSPACE_SRGB:
 855                 word4 |= S_038010_FORCE_DEGAMMA(1);
 856                 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
 857                         goto out_unknown; /* fails for some reason - TODO */
 858                 break;
 859
 860         default:
 861                 break;
 862         }
 863
 864         /* S3TC formats. TODO */
 865         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 866                 static int r600_enable_s3tc = -1;
 867
 868                 if (r600_enable_s3tc == -1)
 869                         r600_enable_s3tc =
 870                                 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 871
 872                 if (!r600_enable_s3tc)
 873                         goto out_unknown;
 874
 875                 switch (format) {
 876                 case PIPE_FORMAT_DXT1_RGB:
 877                 case PIPE_FORMAT_DXT1_RGBA:
 878                         result = FMT_BC1;
 879                         goto out_word4;
 880                 case PIPE_FORMAT_DXT3_RGBA:
 881                         result = FMT_BC2;
 882                         goto out_word4;
 883                 case PIPE_FORMAT_DXT5_RGBA:
 884                         result = FMT_BC3;
 885                         goto out_word4;
 886                 default:
 887                         goto out_unknown;
 888                 }
 889         }
 890
 891
 892         for (i = 0; i < desc->nr_channels; i++) {
 893                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 894                         word4 |= sign_bit[i];
 895                 }
 896         }
 897
 898         /* R8G8Bx_SNORM - TODO CxV8U8 */
 899
 900         /* RGTC - TODO */
 901
 902         /* See whether the components are of the same size. */
 903         for (i = 1; i < desc->nr_channels; i++) {
 904                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 905         }
 906
 907         /* Non-uniform formats. */
 908         if (!uniform) {
 909                 switch(desc->nr_channels) {
 910                 case 3:
 911                         if (desc->channel[0].size == 5 &&
 912                             desc->channel[1].size == 6 &&
 913                             desc->channel[2].size == 5) {
 914                                 result = FMT_5_6_5;
 915                                 goto out_word4;
 916                         }
 917                         goto out_unknown;
 918                 case 4:
 919                         if (desc->channel[0].size == 5 &&
 920                             desc->channel[1].size == 5 &&
 921                             desc->channel[2].size == 5 &&
 922                             desc->channel[3].size == 1) {
 923                                 result = FMT_1_5_5_5;
 924                                 goto out_word4;
 925                         }
 926                         if (desc->channel[0].size == 10 &&
 927                             desc->channel[1].size == 10 &&
 928                             desc->channel[2].size == 10 &&
 929                             desc->channel[3].size == 2) {
 930                                 result = FMT_2_10_10_10;
 931                                 goto out_word4;
 932                         }
 933                         goto out_unknown;
 934                 }
 935                 goto out_unknown;
 936         }
 937
 938         /* Find the first non-VOID channel. */
 939         for (i = 0; i < 4; i++) {
 940                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 941                         break;
 942                 }
 943         }
 944
 945         if (i == 4)
 946                 goto out_unknown;
 947
 948         /* uniform formats */
 949         switch (desc->channel[i].type) {
 950         case UTIL_FORMAT_TYPE_UNSIGNED:
 951         case UTIL_FORMAT_TYPE_SIGNED:
 952                 if (!desc->channel[i].normalized &&
 953                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 954                         goto out_unknown;
 955                 }
 956
 957                 switch (desc->channel[i].size) {
 958                 case 4:
 959                         switch (desc->nr_channels) {
 960                         case 2:
 961                                 result = FMT_4_4;
 962                                 goto out_word4;
 963                         case 4:
 964                                 result = FMT_4_4_4_4;
 965                                 goto out_word4;
 966                         }
 967                         goto out_unknown;
 968                 case 8:
 969                         switch (desc->nr_channels) {
 970                         case 1:
 971                                 result = FMT_8;
 972                                 goto out_word4;
 973                         case 2:
 974                                 result = FMT_8_8;
 975                                 goto out_word4;
 976                         case 4:
 977                                 result = FMT_8_8_8_8;
 978                                 goto out_word4;
 979                         }
 980                         goto out_unknown;
 981                 case 16:
 982                         switch (desc->nr_channels) {
 983                         case 1:
 984                                 result = FMT_16;
 985                                 goto out_word4;
 986                         case 2:
 987                                 result = FMT_16_16;
 988                                 goto out_word4;
 989                         case 4:
 990                                 result = FMT_16_16_16_16;
 991                                 goto out_word4;
 992                         }
 993                         goto out_unknown;
 994                 case 32:
 995                         switch (desc->nr_channels) {
 996                         case 1:
 997                                 result = FMT_32;
 998                                 goto out_word4;
 999                         case 2:
1000                                 result = FMT_32_32;
1001                                 goto out_word4;
1002                         case 4:
1003                                 result = FMT_32_32_32_32;
1004                                 goto out_word4;
1005                         }
1006                 }
1007                 goto out_unknown;
1008
1009         case UTIL_FORMAT_TYPE_FLOAT:
1010                 switch (desc->channel[i].size) {
1011                 case 16:
1012                         switch (desc->nr_channels) {
1013                         case 1:
1014                                 result = FMT_16_FLOAT;
1015                                 goto out_word4;
1016                         case 2:
1017                                 result = FMT_16_16_FLOAT;
1018                                 goto out_word4;
1019                         case 4:
1020                                 result = FMT_16_16_16_16_FLOAT;
1021                                 goto out_word4;
1022                         }
1023                         goto out_unknown;
1024                 case 32:
1025                         switch (desc->nr_channels) {
1026                         case 1:
1027                                 result = FMT_32_FLOAT;
1028                                 goto out_word4;
1029                         case 2:
1030                                 result = FMT_32_32_FLOAT;
1031                                 goto out_word4;
1032                         case 4:
1033                                 result = FMT_32_32_32_32_FLOAT;
1034                                 goto out_word4;
1035                         }
1036                 }
1037
1038         }
1039 out_word4:
1040         if (word4_p)
1041                 *word4_p = word4;
1042         if (yuv_format_p)
1043                 *yuv_format_p = yuv_format;
1044         return result;
1045 out_unknown:
1046 //      R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1047         return ~0;
1048 }