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[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <errno.h>
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_math.h>
31 #include <util/u_inlines.h>
32 #include <util/u_memory.h>
33 #include "state_tracker/drm_driver.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
38 #include "r600d.h"
39 #include "r600_formats.h"
40
41 extern struct u_resource_vtbl r600_texture_vtbl;
42
43 /* Copy from a full GPU texture to a transfer's staging one. */
44 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
45 {
46 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
47 struct pipe_resource *texture = transfer->resource;
48
49 ctx->resource_copy_region(ctx, rtransfer->staging_texture,
50 0, 0, 0, 0, texture, transfer->level,
51 &transfer->box);
52 }
53
54
55 /* Copy from a transfer's staging texture to a full GPU one. */
56 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
57 {
58 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
59 struct pipe_resource *texture = transfer->resource;
60 struct pipe_box sbox;
61
62 sbox.x = sbox.y = sbox.z = 0;
63 sbox.width = transfer->box.width;
64 sbox.height = transfer->box.height;
65 /* XXX that might be wrong */
66 sbox.depth = 1;
67 ctx->resource_copy_region(ctx, texture, transfer->level,
68 transfer->box.x, transfer->box.y, transfer->box.z,
69 rtransfer->staging_texture,
70 0, &sbox);
71
72 ctx->flush(ctx, 0, NULL);
73 }
74
75 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
76 unsigned level, unsigned layer)
77 {
78 unsigned offset = rtex->offset[level];
79
80 switch (rtex->resource.base.b.target) {
81 case PIPE_TEXTURE_3D:
82 case PIPE_TEXTURE_CUBE:
83 return offset + layer * rtex->layer_size[level];
84 default:
85 assert(layer == 0);
86 return offset;
87 }
88 }
89
90 static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
91 enum pipe_format format,
92 unsigned array_mode)
93 {
94 struct r600_screen* rscreen = (struct r600_screen *)screen;
95 unsigned pixsize = util_format_get_blocksize(format);
96 int p_align;
97
98 switch(array_mode) {
99 case V_038000_ARRAY_1D_TILED_THIN1:
100 p_align = MAX2(8,
101 ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
102 break;
103 case V_038000_ARRAY_2D_TILED_THIN1:
104 p_align = MAX2(rscreen->tiling_info->num_banks,
105 (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
106 rscreen->tiling_info->num_banks)) * 8;
107 break;
108 case V_038000_ARRAY_LINEAR_GENERAL:
109 default:
110 p_align = rscreen->tiling_info->group_bytes / pixsize;
111 break;
112 }
113 return p_align;
114 }
115
116 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
117 unsigned array_mode)
118 {
119 struct r600_screen* rscreen = (struct r600_screen *)screen;
120 int h_align;
121
122 switch (array_mode) {
123 case V_038000_ARRAY_2D_TILED_THIN1:
124 h_align = rscreen->tiling_info->num_channels * 8;
125 break;
126 case V_038000_ARRAY_1D_TILED_THIN1:
127 h_align = 8;
128 break;
129 default:
130 h_align = 1;
131 break;
132 }
133 return h_align;
134 }
135
136 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
137 enum pipe_format format,
138 unsigned array_mode)
139 {
140 struct r600_screen* rscreen = (struct r600_screen *)screen;
141 unsigned pixsize = util_format_get_blocksize(format);
142 int p_align = r600_get_pixel_alignment(screen, format, array_mode);
143 int h_align = r600_get_height_alignment(screen, array_mode);
144 int b_align;
145
146 switch (array_mode) {
147 case V_038000_ARRAY_2D_TILED_THIN1:
148 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
149 p_align * pixsize * h_align);
150 break;
151 case V_038000_ARRAY_1D_TILED_THIN1:
152 default:
153 b_align = rscreen->tiling_info->group_bytes;
154 break;
155 }
156 return b_align;
157 }
158
159 static unsigned mip_minify(unsigned size, unsigned level)
160 {
161 unsigned val;
162 val = u_minify(size, level);
163 if (level > 0)
164 val = util_next_power_of_two(val);
165 return val;
166 }
167
168 static unsigned r600_texture_get_stride(struct pipe_screen *screen,
169 struct r600_resource_texture *rtex,
170 unsigned level)
171 {
172 struct pipe_resource *ptex = &rtex->resource.base.b;
173 unsigned width, stride, tile_width;
174
175 if (rtex->pitch_override)
176 return rtex->pitch_override;
177
178 width = mip_minify(ptex->width0, level);
179 if (util_format_is_plain(ptex->format)) {
180 tile_width = r600_get_pixel_alignment(screen, ptex->format,
181 rtex->array_mode[level]);
182 width = align(width, tile_width);
183 }
184 stride = util_format_get_stride(ptex->format, width);
185
186 return stride;
187 }
188
189 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
190 struct r600_resource_texture *rtex,
191 unsigned level)
192 {
193 struct pipe_resource *ptex = &rtex->resource.base.b;
194 unsigned height, tile_height;
195
196 height = mip_minify(ptex->height0, level);
197 if (util_format_is_plain(ptex->format)) {
198 tile_height = r600_get_height_alignment(screen,
199 rtex->array_mode[level]);
200 height = align(height, tile_height);
201 }
202 return util_format_get_nblocksy(ptex->format, height);
203 }
204
205 /* Get a width in pixels from a stride in bytes. */
206 static unsigned pitch_to_width(enum pipe_format format, unsigned pitch_in_bytes)
207 {
208 return (pitch_in_bytes / util_format_get_blocksize(format)) *
209 util_format_get_blockwidth(format);
210 }
211
212 static void r600_texture_set_array_mode(struct pipe_screen *screen,
213 struct r600_resource_texture *rtex,
214 unsigned level, unsigned array_mode)
215 {
216 struct pipe_resource *ptex = &rtex->resource.base.b;
217
218 switch (array_mode) {
219 case V_0280A0_ARRAY_LINEAR_GENERAL:
220 case V_0280A0_ARRAY_LINEAR_ALIGNED:
221 case V_0280A0_ARRAY_1D_TILED_THIN1:
222 default:
223 rtex->array_mode[level] = array_mode;
224 break;
225 case V_0280A0_ARRAY_2D_TILED_THIN1:
226 {
227 unsigned w, h, tile_height, tile_width;
228
229 tile_height = r600_get_height_alignment(screen, array_mode);
230 tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode);
231
232 w = mip_minify(ptex->width0, level);
233 h = mip_minify(ptex->height0, level);
234 if (w < tile_width || h < tile_height)
235 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
236 else
237 rtex->array_mode[level] = array_mode;
238 }
239 break;
240 }
241 }
242
243 static void r600_setup_miptree(struct pipe_screen *screen,
244 struct r600_resource_texture *rtex,
245 unsigned array_mode)
246 {
247 struct pipe_resource *ptex = &rtex->resource.base.b;
248 struct radeon *radeon = (struct radeon *)screen->winsys;
249 enum chip_class chipc = r600_get_family_class(radeon);
250 unsigned pitch, size, layer_size, i, offset;
251 unsigned nblocksy;
252
253 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
254 r600_texture_set_array_mode(screen, rtex, i, array_mode);
255
256 pitch = r600_texture_get_stride(screen, rtex, i);
257 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
258
259 layer_size = pitch * nblocksy;
260
261 if (ptex->target == PIPE_TEXTURE_CUBE) {
262 if (chipc >= R700)
263 size = layer_size * 8;
264 else
265 size = layer_size * 6;
266 }
267 else
268 size = layer_size * u_minify(ptex->depth0, i);
269 /* align base image and start of miptree */
270 if ((i == 0) || (i == 1))
271 offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
272 rtex->offset[i] = offset;
273 rtex->layer_size[i] = layer_size;
274 rtex->pitch_in_bytes[i] = pitch;
275 rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
276 offset += size;
277 }
278 rtex->size = offset;
279 }
280
281 static struct r600_resource_texture *
282 r600_texture_create_object(struct pipe_screen *screen,
283 const struct pipe_resource *base,
284 unsigned array_mode,
285 unsigned pitch_in_bytes_override,
286 unsigned max_buffer_size,
287 struct r600_bo *bo)
288 {
289 struct r600_resource_texture *rtex;
290 struct r600_resource *resource;
291 struct radeon *radeon = (struct radeon *)screen->winsys;
292
293 rtex = CALLOC_STRUCT(r600_resource_texture);
294 if (rtex == NULL)
295 return NULL;
296
297 resource = &rtex->resource;
298 resource->base.b = *base;
299 resource->base.vtbl = &r600_texture_vtbl;
300 pipe_reference_init(&resource->base.b.reference, 1);
301 resource->base.b.screen = screen;
302 resource->bo = bo;
303 rtex->pitch_override = pitch_in_bytes_override;
304
305 if (array_mode)
306 rtex->tiled = 1;
307 r600_setup_miptree(screen, rtex, array_mode);
308
309 resource->size = rtex->size;
310
311 if (!resource->bo) {
312 struct pipe_resource *ptex = &rtex->resource.base.b;
313 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
314
315 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
316 if (!resource->bo) {
317 FREE(rtex);
318 return NULL;
319 }
320 }
321 return rtex;
322 }
323
324 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
325 const struct pipe_resource *templ)
326 {
327 unsigned array_mode = 0;
328 static int force_tiling = -1;
329
330 /* Would like some magic "get_bool_option_once" routine.
331 */
332 if (force_tiling == -1)
333 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
334
335 if (force_tiling) {
336 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
337 !(templ->bind & PIPE_BIND_SCANOUT)) {
338 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
339 }
340 }
341
342 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
343 0, 0, NULL);
344
345 }
346
347 static void r600_texture_destroy(struct pipe_screen *screen,
348 struct pipe_resource *ptex)
349 {
350 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
351 struct r600_resource *resource = &rtex->resource;
352 struct radeon *radeon = (struct radeon *)screen->winsys;
353
354 if (rtex->flushed_depth_texture)
355 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
356
357 if (resource->bo) {
358 r600_bo_reference(radeon, &resource->bo, NULL);
359 }
360 FREE(rtex);
361 }
362
363 static boolean r600_texture_get_handle(struct pipe_screen* screen,
364 struct pipe_resource *ptex,
365 struct winsys_handle *whandle)
366 {
367 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
368 struct r600_resource *resource = &rtex->resource;
369 struct radeon *radeon = (struct radeon *)screen->winsys;
370
371 return r600_bo_get_winsys_handle(radeon, resource->bo,
372 rtex->pitch_in_bytes[0], whandle);
373 }
374
375 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
376 struct pipe_resource *texture,
377 const struct pipe_surface *surf_tmpl)
378 {
379 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
380 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
381 unsigned tile_height;
382 unsigned level = surf_tmpl->u.tex.level;
383
384 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
385 if (surface == NULL)
386 return NULL;
387 /* XXX no offset */
388 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
389 pipe_reference_init(&surface->base.reference, 1);
390 pipe_resource_reference(&surface->base.texture, texture);
391 surface->base.context = pipe;
392 surface->base.format = surf_tmpl->format;
393 surface->base.width = mip_minify(texture->width0, level);
394 surface->base.height = mip_minify(texture->height0, level);
395 surface->base.usage = surf_tmpl->usage;
396 surface->base.texture = texture;
397 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
398 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
399 surface->base.u.tex.level = level;
400
401 tile_height = r600_get_height_alignment(pipe->screen, rtex->array_mode[level]);
402 surface->aligned_height = align(surface->base.height, tile_height);
403 return &surface->base;
404 }
405
406 static void r600_surface_destroy(struct pipe_context *pipe,
407 struct pipe_surface *surface)
408 {
409 pipe_resource_reference(&surface->texture, NULL);
410 FREE(surface);
411 }
412
413
414 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
415 const struct pipe_resource *templ,
416 struct winsys_handle *whandle)
417 {
418 struct radeon *rw = (struct radeon*)screen->winsys;
419 struct r600_bo *bo = NULL;
420 unsigned array_mode = 0;
421
422 /* Support only 2D textures without mipmaps */
423 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
424 templ->depth0 != 1 || templ->last_level != 0)
425 return NULL;
426
427 bo = r600_bo_handle(rw, whandle->handle, &array_mode);
428 if (bo == NULL) {
429 return NULL;
430 }
431
432 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
433 whandle->stride,
434 0,
435 bo);
436 }
437
438 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
439 struct pipe_resource *texture,
440 unsigned level, int layer)
441 {
442 /* FIXME */
443 return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
444 }
445
446 int r600_texture_depth_flush(struct pipe_context *ctx,
447 struct pipe_resource *texture)
448 {
449 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
450 struct pipe_resource resource;
451
452 if (rtex->flushed_depth_texture)
453 goto out;
454
455 resource.target = PIPE_TEXTURE_2D;
456 resource.format = texture->format;
457 resource.width0 = texture->width0;
458 resource.height0 = texture->height0;
459 resource.depth0 = 1;
460 resource.last_level = 0;
461 resource.nr_samples = 0;
462 resource.usage = PIPE_USAGE_DYNAMIC;
463 resource.bind = 0;
464 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
465
466 resource.bind |= PIPE_BIND_DEPTH_STENCIL;
467
468 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
469 if (rtex->flushed_depth_texture == NULL) {
470 R600_ERR("failed to create temporary texture to hold untiled copy\n");
471 return -ENOMEM;
472 }
473
474 out:
475 /* XXX: only do this if the depth texture has actually changed:
476 */
477 r600_blit_uncompress_depth(ctx, rtex);
478 return 0;
479 }
480
481 /* Needs adjustment for pixelformat:
482 */
483 static INLINE unsigned u_box_volume( const struct pipe_box *box )
484 {
485 return box->width * box->depth * box->height;
486 };
487
488
489 /* Figure out whether u_blitter will fallback to a transfer operation.
490 * If so, don't use a staging resource.
491 */
492 static boolean permit_hardware_blit(struct pipe_screen *screen,
493 struct pipe_resource *res)
494 {
495 unsigned bind;
496
497 if (util_format_is_depth_or_stencil(res->format))
498 bind = PIPE_BIND_DEPTH_STENCIL;
499 else
500 bind = PIPE_BIND_RENDER_TARGET;
501
502 /* See r600_resource_copy_region: there is something wrong
503 * with depth resource copies at the moment so avoid them for
504 * now.
505 */
506 if (util_format_get_component_bits(res->format,
507 UTIL_FORMAT_COLORSPACE_ZS,
508 0) != 0)
509 return FALSE;
510
511 if (!screen->is_format_supported(screen,
512 res->format,
513 res->target,
514 res->nr_samples,
515 bind, 0))
516 return FALSE;
517
518 if (!screen->is_format_supported(screen,
519 res->format,
520 res->target,
521 res->nr_samples,
522 PIPE_BIND_SAMPLER_VIEW, 0))
523 return FALSE;
524
525 return TRUE;
526 }
527
528 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
529 struct pipe_resource *texture,
530 unsigned level,
531 unsigned usage,
532 const struct pipe_box *box)
533 {
534 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
535 struct pipe_resource resource;
536 struct r600_transfer *trans;
537 int r;
538 boolean use_staging_texture = FALSE;
539
540 /* We cannot map a tiled texture directly because the data is
541 * in a different order, therefore we do detiling using a blit.
542 *
543 * Also, use a temporary in GTT memory for read transfers, as
544 * the CPU is much happier reading out of cached system memory
545 * than uncached VRAM.
546 */
547 if (rtex->tiled)
548 use_staging_texture = TRUE;
549
550 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
551 use_staging_texture = TRUE;
552
553 /* XXX: Use a staging texture for uploads if the underlying BO
554 * is busy. No interface for checking that currently? so do
555 * it eagerly whenever the transfer doesn't require a readback
556 * and might block.
557 */
558 if ((usage & PIPE_TRANSFER_WRITE) &&
559 !(usage & (PIPE_TRANSFER_READ |
560 PIPE_TRANSFER_DONTBLOCK |
561 PIPE_TRANSFER_UNSYNCHRONIZED)))
562 use_staging_texture = TRUE;
563
564 if (!permit_hardware_blit(ctx->screen, texture) ||
565 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
566 use_staging_texture = FALSE;
567
568 trans = CALLOC_STRUCT(r600_transfer);
569 if (trans == NULL)
570 return NULL;
571 pipe_resource_reference(&trans->transfer.resource, texture);
572 trans->transfer.level = level;
573 trans->transfer.usage = usage;
574 trans->transfer.box = *box;
575 if (rtex->depth) {
576 /* XXX: only readback the rectangle which is being mapped?
577 */
578 /* XXX: when discard is true, no need to read back from depth texture
579 */
580 r = r600_texture_depth_flush(ctx, texture);
581 if (r < 0) {
582 R600_ERR("failed to create temporary texture to hold untiled copy\n");
583 pipe_resource_reference(&trans->transfer.resource, NULL);
584 FREE(trans);
585 return NULL;
586 }
587 } else if (use_staging_texture) {
588 resource.target = PIPE_TEXTURE_2D;
589 resource.format = texture->format;
590 resource.width0 = box->width;
591 resource.height0 = box->height;
592 resource.depth0 = 1;
593 resource.array_size = 1;
594 resource.last_level = 0;
595 resource.nr_samples = 0;
596 resource.usage = PIPE_USAGE_STAGING;
597 resource.bind = 0;
598 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
599 /* For texture reading, the temporary (detiled) texture is used as
600 * a render target when blitting from a tiled texture. */
601 if (usage & PIPE_TRANSFER_READ) {
602 resource.bind |= PIPE_BIND_RENDER_TARGET;
603 }
604 /* For texture writing, the temporary texture is used as a sampler
605 * when blitting into a tiled texture. */
606 if (usage & PIPE_TRANSFER_WRITE) {
607 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
608 }
609 /* Create the temporary texture. */
610 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
611 if (trans->staging_texture == NULL) {
612 R600_ERR("failed to create temporary texture to hold untiled copy\n");
613 pipe_resource_reference(&trans->transfer.resource, NULL);
614 FREE(trans);
615 return NULL;
616 }
617
618 trans->transfer.stride =
619 ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
620 if (usage & PIPE_TRANSFER_READ) {
621 r600_copy_to_staging_texture(ctx, trans);
622 /* Always referenced in the blit. */
623 ctx->flush(ctx, 0, NULL);
624 }
625 return &trans->transfer;
626 }
627 trans->transfer.stride = rtex->pitch_in_bytes[level];
628 trans->offset = r600_texture_get_offset(rtex, level, box->z);
629 return &trans->transfer;
630 }
631
632 void r600_texture_transfer_destroy(struct pipe_context *ctx,
633 struct pipe_transfer *transfer)
634 {
635 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
636 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
637
638 if (rtransfer->staging_texture) {
639 if (transfer->usage & PIPE_TRANSFER_WRITE) {
640 r600_copy_from_staging_texture(ctx, rtransfer);
641 }
642 pipe_resource_reference(&rtransfer->staging_texture, NULL);
643 }
644 if (rtex->flushed_depth_texture) {
645 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
646 }
647 pipe_resource_reference(&transfer->resource, NULL);
648 FREE(transfer);
649 }
650
651 void* r600_texture_transfer_map(struct pipe_context *ctx,
652 struct pipe_transfer* transfer)
653 {
654 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
655 struct r600_bo *bo;
656 enum pipe_format format = transfer->resource->format;
657 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
658 unsigned offset = 0;
659 unsigned usage = 0;
660 char *map;
661
662 if (rtransfer->staging_texture) {
663 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
664 } else {
665 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
666
667 if (rtex->flushed_depth_texture)
668 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
669 else
670 bo = ((struct r600_resource *)transfer->resource)->bo;
671
672 offset = rtransfer->offset +
673 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
674 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
675 }
676
677 if (transfer->usage & PIPE_TRANSFER_WRITE) {
678 usage |= PB_USAGE_CPU_WRITE;
679
680 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
681 }
682
683 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
684 }
685 }
686
687 if (transfer->usage & PIPE_TRANSFER_READ) {
688 usage |= PB_USAGE_CPU_READ;
689 }
690
691 if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
692 usage |= PB_USAGE_DONTBLOCK;
693 }
694
695 if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
696 usage |= PB_USAGE_UNSYNCHRONIZED;
697 }
698
699 map = r600_bo_map(radeon, bo, usage, ctx);
700 if (!map) {
701 return NULL;
702 }
703
704 return map + offset;
705 }
706
707 void r600_texture_transfer_unmap(struct pipe_context *ctx,
708 struct pipe_transfer* transfer)
709 {
710 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
711 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
712 struct r600_bo *bo;
713
714 if (rtransfer->staging_texture) {
715 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
716 } else {
717 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
718
719 if (rtex->flushed_depth_texture) {
720 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
721 } else {
722 bo = ((struct r600_resource *)transfer->resource)->bo;
723 }
724 }
725 r600_bo_unmap(radeon, bo);
726 }
727
728 struct u_resource_vtbl r600_texture_vtbl =
729 {
730 r600_texture_get_handle, /* get_handle */
731 r600_texture_destroy, /* resource_destroy */
732 r600_texture_is_referenced, /* is_resource_referenced */
733 r600_texture_get_transfer, /* get_transfer */
734 r600_texture_transfer_destroy, /* transfer_destroy */
735 r600_texture_transfer_map, /* transfer_map */
736 u_default_transfer_flush_region,/* transfer_flush_region */
737 r600_texture_transfer_unmap, /* transfer_unmap */
738 u_default_transfer_inline_write /* transfer_inline_write */
739 };
740
741 void r600_init_surface_functions(struct r600_pipe_context *r600)
742 {
743 r600->context.create_surface = r600_create_surface;
744 r600->context.surface_destroy = r600_surface_destroy;
745 }
746
747 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
748 const unsigned char *swizzle_view)
749 {
750 unsigned i;
751 unsigned char swizzle[4];
752 unsigned result = 0;
753 const uint32_t swizzle_shift[4] = {
754 16, 19, 22, 25,
755 };
756 const uint32_t swizzle_bit[4] = {
757 0, 1, 2, 3,
758 };
759
760 if (swizzle_view) {
761 /* Combine two sets of swizzles. */
762 for (i = 0; i < 4; i++) {
763 swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
764 swizzle_format[swizzle_view[i]] : swizzle_view[i];
765 }
766 } else {
767 memcpy(swizzle, swizzle_format, 4);
768 }
769
770 /* Get swizzle. */
771 for (i = 0; i < 4; i++) {
772 switch (swizzle[i]) {
773 case UTIL_FORMAT_SWIZZLE_Y:
774 result |= swizzle_bit[1] << swizzle_shift[i];
775 break;
776 case UTIL_FORMAT_SWIZZLE_Z:
777 result |= swizzle_bit[2] << swizzle_shift[i];
778 break;
779 case UTIL_FORMAT_SWIZZLE_W:
780 result |= swizzle_bit[3] << swizzle_shift[i];
781 break;
782 case UTIL_FORMAT_SWIZZLE_0:
783 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
784 break;
785 case UTIL_FORMAT_SWIZZLE_1:
786 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
787 break;
788 default: /* UTIL_FORMAT_SWIZZLE_X */
789 result |= swizzle_bit[0] << swizzle_shift[i];
790 }
791 }
792 return result;
793 }
794
795 /* texture format translate */
796 uint32_t r600_translate_texformat(enum pipe_format format,
797 const unsigned char *swizzle_view,
798 uint32_t *word4_p, uint32_t *yuv_format_p)
799 {
800 uint32_t result = 0, word4 = 0, yuv_format = 0;
801 const struct util_format_description *desc;
802 boolean uniform = TRUE;
803 int i;
804 const uint32_t sign_bit[4] = {
805 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
806 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
807 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
808 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
809 };
810 desc = util_format_description(format);
811
812 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
813
814 /* Colorspace (return non-RGB formats directly). */
815 switch (desc->colorspace) {
816 /* Depth stencil formats */
817 case UTIL_FORMAT_COLORSPACE_ZS:
818 switch (format) {
819 case PIPE_FORMAT_Z16_UNORM:
820 result = FMT_16;
821 goto out_word4;
822 case PIPE_FORMAT_X24S8_USCALED:
823 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
824 case PIPE_FORMAT_Z24X8_UNORM:
825 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
826 result = FMT_8_24;
827 goto out_word4;
828 case PIPE_FORMAT_S8X24_USCALED:
829 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
830 case PIPE_FORMAT_X8Z24_UNORM:
831 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
832 result = FMT_24_8;
833 goto out_word4;
834 case PIPE_FORMAT_S8_USCALED:
835 result = FMT_8;
836 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
837 goto out_word4;
838 default:
839 goto out_unknown;
840 }
841
842 case UTIL_FORMAT_COLORSPACE_YUV:
843 yuv_format |= (1 << 30);
844 switch (format) {
845 case PIPE_FORMAT_UYVY:
846 case PIPE_FORMAT_YUYV:
847 default:
848 break;
849 }
850 goto out_unknown; /* TODO */
851
852 case UTIL_FORMAT_COLORSPACE_SRGB:
853 word4 |= S_038010_FORCE_DEGAMMA(1);
854 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
855 goto out_unknown; /* fails for some reason - TODO */
856 break;
857
858 default:
859 break;
860 }
861
862 /* S3TC formats. TODO */
863 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
864 static int r600_enable_s3tc = -1;
865
866 if (r600_enable_s3tc == -1)
867 r600_enable_s3tc =
868 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
869
870 if (!r600_enable_s3tc)
871 goto out_unknown;
872
873 switch (format) {
874 case PIPE_FORMAT_DXT1_RGB:
875 case PIPE_FORMAT_DXT1_RGBA:
876 result = FMT_BC1;
877 goto out_word4;
878 case PIPE_FORMAT_DXT3_RGBA:
879 result = FMT_BC2;
880 goto out_word4;
881 case PIPE_FORMAT_DXT5_RGBA:
882 result = FMT_BC3;
883 goto out_word4;
884 default:
885 goto out_unknown;
886 }
887 }
888
889
890 for (i = 0; i < desc->nr_channels; i++) {
891 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
892 word4 |= sign_bit[i];
893 }
894 }
895
896 /* R8G8Bx_SNORM - TODO CxV8U8 */
897
898 /* RGTC - TODO */
899
900 /* See whether the components are of the same size. */
901 for (i = 1; i < desc->nr_channels; i++) {
902 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
903 }
904
905 /* Non-uniform formats. */
906 if (!uniform) {
907 switch(desc->nr_channels) {
908 case 3:
909 if (desc->channel[0].size == 5 &&
910 desc->channel[1].size == 6 &&
911 desc->channel[2].size == 5) {
912 result = FMT_5_6_5;
913 goto out_word4;
914 }
915 goto out_unknown;
916 case 4:
917 if (desc->channel[0].size == 5 &&
918 desc->channel[1].size == 5 &&
919 desc->channel[2].size == 5 &&
920 desc->channel[3].size == 1) {
921 result = FMT_1_5_5_5;
922 goto out_word4;
923 }
924 if (desc->channel[0].size == 10 &&
925 desc->channel[1].size == 10 &&
926 desc->channel[2].size == 10 &&
927 desc->channel[3].size == 2) {
928 result = FMT_10_10_10_2;
929 goto out_word4;
930 }
931 goto out_unknown;
932 }
933 goto out_unknown;
934 }
935
936 /* Find the first non-VOID channel. */
937 for (i = 0; i < 4; i++) {
938 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
939 break;
940 }
941 }
942
943 if (i == 4)
944 goto out_unknown;
945
946 /* uniform formats */
947 switch (desc->channel[i].type) {
948 case UTIL_FORMAT_TYPE_UNSIGNED:
949 case UTIL_FORMAT_TYPE_SIGNED:
950 if (!desc->channel[i].normalized &&
951 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
952 goto out_unknown;
953 }
954
955 switch (desc->channel[i].size) {
956 case 4:
957 switch (desc->nr_channels) {
958 case 2:
959 result = FMT_4_4;
960 goto out_word4;
961 case 4:
962 result = FMT_4_4_4_4;
963 goto out_word4;
964 }
965 goto out_unknown;
966 case 8:
967 switch (desc->nr_channels) {
968 case 1:
969 result = FMT_8;
970 goto out_word4;
971 case 2:
972 result = FMT_8_8;
973 goto out_word4;
974 case 4:
975 result = FMT_8_8_8_8;
976 goto out_word4;
977 }
978 goto out_unknown;
979 case 16:
980 switch (desc->nr_channels) {
981 case 1:
982 result = FMT_16;
983 goto out_word4;
984 case 2:
985 result = FMT_16_16;
986 goto out_word4;
987 case 4:
988 result = FMT_16_16_16_16;
989 goto out_word4;
990 }
991 }
992 goto out_unknown;
993
994 case UTIL_FORMAT_TYPE_FLOAT:
995 switch (desc->channel[i].size) {
996 case 16:
997 switch (desc->nr_channels) {
998 case 1:
999 result = FMT_16_FLOAT;
1000 goto out_word4;
1001 case 2:
1002 result = FMT_16_16_FLOAT;
1003 goto out_word4;
1004 case 4:
1005 result = FMT_16_16_16_16_FLOAT;
1006 goto out_word4;
1007 }
1008 goto out_unknown;
1009 case 32:
1010 switch (desc->nr_channels) {
1011 case 1:
1012 result = FMT_32_FLOAT;
1013 goto out_word4;
1014 case 2:
1015 result = FMT_32_32_FLOAT;
1016 goto out_word4;
1017 case 4:
1018 result = FMT_32_32_32_32_FLOAT;
1019 goto out_word4;
1020 }
1021 }
1022
1023 }
1024 out_word4:
1025 if (word4_p)
1026 *word4_p = word4;
1027 if (yuv_format_p)
1028 *yuv_format_p = yuv_format;
1029 return result;
1030 out_unknown:
1031 // R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1032 return ~0;
1033 }