2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_math.h>
31 #include <util/u_inlines.h>
32 #include <util/u_memory.h>
33 #include "state_tracker/drm_driver.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
39 #include "r600_formats.h"
41 extern struct u_resource_vtbl r600_texture_vtbl
;
43 /* Copy from a full GPU texture to a transfer's staging one. */
44 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
46 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
47 struct pipe_resource
*texture
= transfer
->resource
;
49 ctx
->resource_copy_region(ctx
, rtransfer
->staging_texture
,
50 0, 0, 0, 0, texture
, transfer
->level
,
55 /* Copy from a transfer's staging texture to a full GPU one. */
56 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
58 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
59 struct pipe_resource
*texture
= transfer
->resource
;
62 sbox
.x
= sbox
.y
= sbox
.z
= 0;
63 sbox
.width
= transfer
->box
.width
;
64 sbox
.height
= transfer
->box
.height
;
65 /* XXX that might be wrong */
67 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
68 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
69 rtransfer
->staging_texture
,
72 ctx
->flush(ctx
, 0, NULL
);
75 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
76 unsigned level
, unsigned layer
)
78 unsigned offset
= rtex
->offset
[level
];
80 switch (rtex
->resource
.base
.b
.target
) {
82 case PIPE_TEXTURE_CUBE
:
83 return offset
+ layer
* rtex
->layer_size
[level
];
90 static unsigned r600_get_pixel_alignment(struct pipe_screen
*screen
,
91 enum pipe_format format
,
94 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
95 unsigned pixsize
= util_format_get_blocksize(format
);
99 case V_038000_ARRAY_1D_TILED_THIN1
:
101 ((rscreen
->tiling_info
->group_bytes
/ 8 / pixsize
)));
103 case V_038000_ARRAY_2D_TILED_THIN1
:
104 p_align
= MAX2(rscreen
->tiling_info
->num_banks
,
105 (((rscreen
->tiling_info
->group_bytes
/ 8 / pixsize
)) *
106 rscreen
->tiling_info
->num_banks
)) * 8;
108 case V_038000_ARRAY_LINEAR_GENERAL
:
110 p_align
= rscreen
->tiling_info
->group_bytes
/ pixsize
;
116 static unsigned r600_get_height_alignment(struct pipe_screen
*screen
,
119 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
122 switch (array_mode
) {
123 case V_038000_ARRAY_2D_TILED_THIN1
:
124 h_align
= rscreen
->tiling_info
->num_channels
* 8;
126 case V_038000_ARRAY_1D_TILED_THIN1
:
136 static unsigned r600_get_base_alignment(struct pipe_screen
*screen
,
137 enum pipe_format format
,
140 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
141 unsigned pixsize
= util_format_get_blocksize(format
);
142 int p_align
= r600_get_pixel_alignment(screen
, format
, array_mode
);
143 int h_align
= r600_get_height_alignment(screen
, array_mode
);
146 switch (array_mode
) {
147 case V_038000_ARRAY_2D_TILED_THIN1
:
148 b_align
= MAX2(rscreen
->tiling_info
->num_banks
* rscreen
->tiling_info
->num_channels
* 8 * 8 * pixsize
,
149 p_align
* pixsize
* h_align
);
151 case V_038000_ARRAY_1D_TILED_THIN1
:
153 b_align
= rscreen
->tiling_info
->group_bytes
;
159 static unsigned mip_minify(unsigned size
, unsigned level
)
162 val
= u_minify(size
, level
);
164 val
= util_next_power_of_two(val
);
168 static unsigned r600_texture_get_stride(struct pipe_screen
*screen
,
169 struct r600_resource_texture
*rtex
,
172 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
173 unsigned width
, stride
, tile_width
;
175 if (rtex
->pitch_override
)
176 return rtex
->pitch_override
;
178 width
= mip_minify(ptex
->width0
, level
);
179 if (util_format_is_plain(ptex
->format
)) {
180 tile_width
= r600_get_pixel_alignment(screen
, ptex
->format
,
181 rtex
->array_mode
[level
]);
182 width
= align(width
, tile_width
);
184 stride
= util_format_get_stride(ptex
->format
, width
);
189 static unsigned r600_texture_get_nblocksy(struct pipe_screen
*screen
,
190 struct r600_resource_texture
*rtex
,
193 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
194 unsigned height
, tile_height
;
196 height
= mip_minify(ptex
->height0
, level
);
197 if (util_format_is_plain(ptex
->format
)) {
198 tile_height
= r600_get_height_alignment(screen
,
199 rtex
->array_mode
[level
]);
200 height
= align(height
, tile_height
);
202 return util_format_get_nblocksy(ptex
->format
, height
);
205 /* Get a width in pixels from a stride in bytes. */
206 static unsigned pitch_to_width(enum pipe_format format
, unsigned pitch_in_bytes
)
208 return (pitch_in_bytes
/ util_format_get_blocksize(format
)) *
209 util_format_get_blockwidth(format
);
212 static void r600_texture_set_array_mode(struct pipe_screen
*screen
,
213 struct r600_resource_texture
*rtex
,
214 unsigned level
, unsigned array_mode
)
216 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
218 switch (array_mode
) {
219 case V_0280A0_ARRAY_LINEAR_GENERAL
:
220 case V_0280A0_ARRAY_LINEAR_ALIGNED
:
221 case V_0280A0_ARRAY_1D_TILED_THIN1
:
223 rtex
->array_mode
[level
] = array_mode
;
225 case V_0280A0_ARRAY_2D_TILED_THIN1
:
227 unsigned w
, h
, tile_height
, tile_width
;
229 tile_height
= r600_get_height_alignment(screen
, array_mode
);
230 tile_width
= r600_get_pixel_alignment(screen
, ptex
->format
, array_mode
);
232 w
= mip_minify(ptex
->width0
, level
);
233 h
= mip_minify(ptex
->height0
, level
);
234 if (w
< tile_width
|| h
< tile_height
)
235 rtex
->array_mode
[level
] = V_0280A0_ARRAY_1D_TILED_THIN1
;
237 rtex
->array_mode
[level
] = array_mode
;
243 static void r600_setup_miptree(struct pipe_screen
*screen
,
244 struct r600_resource_texture
*rtex
,
247 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
248 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
249 enum chip_class chipc
= r600_get_family_class(radeon
);
250 unsigned pitch
, size
, layer_size
, i
, offset
;
253 for (i
= 0, offset
= 0; i
<= ptex
->last_level
; i
++) {
254 r600_texture_set_array_mode(screen
, rtex
, i
, array_mode
);
256 pitch
= r600_texture_get_stride(screen
, rtex
, i
);
257 nblocksy
= r600_texture_get_nblocksy(screen
, rtex
, i
);
259 layer_size
= pitch
* nblocksy
;
261 if (ptex
->target
== PIPE_TEXTURE_CUBE
) {
263 size
= layer_size
* 8;
265 size
= layer_size
* 6;
268 size
= layer_size
* u_minify(ptex
->depth0
, i
);
269 /* align base image and start of miptree */
270 if ((i
== 0) || (i
== 1))
271 offset
= align(offset
, r600_get_base_alignment(screen
, ptex
->format
, array_mode
));
272 rtex
->offset
[i
] = offset
;
273 rtex
->layer_size
[i
] = layer_size
;
274 rtex
->pitch_in_bytes
[i
] = pitch
;
275 rtex
->pitch_in_pixels
[i
] = pitch_to_width(ptex
->format
, pitch
);
281 /* Figure out whether u_blitter will fallback to a transfer operation.
282 * If so, don't use a staging resource.
284 static boolean
permit_hardware_blit(struct pipe_screen
*screen
,
285 const struct pipe_resource
*res
)
289 if (util_format_is_depth_or_stencil(res
->format
))
290 bind
= PIPE_BIND_DEPTH_STENCIL
;
292 bind
= PIPE_BIND_RENDER_TARGET
;
294 if (!screen
->is_format_supported(screen
,
301 if (!screen
->is_format_supported(screen
,
305 PIPE_BIND_SAMPLER_VIEW
, 0))
311 static struct r600_resource_texture
*
312 r600_texture_create_object(struct pipe_screen
*screen
,
313 const struct pipe_resource
*base
,
315 unsigned pitch_in_bytes_override
,
316 unsigned max_buffer_size
,
319 struct r600_resource_texture
*rtex
;
320 struct r600_resource
*resource
;
321 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
323 rtex
= CALLOC_STRUCT(r600_resource_texture
);
327 resource
= &rtex
->resource
;
328 resource
->base
.b
= *base
;
329 resource
->base
.vtbl
= &r600_texture_vtbl
;
330 pipe_reference_init(&resource
->base
.b
.reference
, 1);
331 resource
->base
.b
.screen
= screen
;
333 rtex
->pitch_override
= pitch_in_bytes_override
;
334 /* only mark depth textures the HW can hit as depth textures */
335 if (util_format_is_depth_or_stencil(base
->format
) && permit_hardware_blit(screen
, base
))
340 r600_setup_miptree(screen
, rtex
, array_mode
);
342 resource
->size
= rtex
->size
;
345 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
346 int base_align
= r600_get_base_alignment(screen
, ptex
->format
, array_mode
);
348 resource
->bo
= r600_bo(radeon
, rtex
->size
, base_align
, base
->bind
, base
->usage
);
357 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
358 const struct pipe_resource
*templ
)
360 unsigned array_mode
= 0;
361 static int force_tiling
= -1;
363 /* Would like some magic "get_bool_option_once" routine.
365 if (force_tiling
== -1)
366 force_tiling
= debug_get_bool_option("R600_FORCE_TILING", FALSE
);
368 if (force_tiling
&& permit_hardware_blit(screen
, templ
)) {
369 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
370 !(templ
->bind
& PIPE_BIND_SCANOUT
)) {
371 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
375 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
380 static void r600_texture_destroy(struct pipe_screen
*screen
,
381 struct pipe_resource
*ptex
)
383 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
384 struct r600_resource
*resource
= &rtex
->resource
;
385 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
387 if (rtex
->flushed_depth_texture
)
388 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
391 r600_bo_reference(radeon
, &resource
->bo
, NULL
);
396 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
397 struct pipe_resource
*ptex
,
398 struct winsys_handle
*whandle
)
400 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
401 struct r600_resource
*resource
= &rtex
->resource
;
402 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
404 return r600_bo_get_winsys_handle(radeon
, resource
->bo
,
405 rtex
->pitch_in_bytes
[0], whandle
);
408 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
409 struct pipe_resource
*texture
,
410 const struct pipe_surface
*surf_tmpl
)
412 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
413 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
414 unsigned tile_height
;
415 unsigned level
= surf_tmpl
->u
.tex
.level
;
417 assert(surf_tmpl
->u
.tex
.first_layer
== surf_tmpl
->u
.tex
.last_layer
);
421 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
422 pipe_reference_init(&surface
->base
.reference
, 1);
423 pipe_resource_reference(&surface
->base
.texture
, texture
);
424 surface
->base
.context
= pipe
;
425 surface
->base
.format
= surf_tmpl
->format
;
426 surface
->base
.width
= mip_minify(texture
->width0
, level
);
427 surface
->base
.height
= mip_minify(texture
->height0
, level
);
428 surface
->base
.usage
= surf_tmpl
->usage
;
429 surface
->base
.texture
= texture
;
430 surface
->base
.u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
431 surface
->base
.u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
432 surface
->base
.u
.tex
.level
= level
;
434 tile_height
= r600_get_height_alignment(pipe
->screen
, rtex
->array_mode
[level
]);
435 surface
->aligned_height
= align(surface
->base
.height
, tile_height
);
436 return &surface
->base
;
439 static void r600_surface_destroy(struct pipe_context
*pipe
,
440 struct pipe_surface
*surface
)
442 pipe_resource_reference(&surface
->texture
, NULL
);
447 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
448 const struct pipe_resource
*templ
,
449 struct winsys_handle
*whandle
)
451 struct radeon
*rw
= (struct radeon
*)screen
->winsys
;
452 struct r600_bo
*bo
= NULL
;
453 unsigned array_mode
= 0;
455 /* Support only 2D textures without mipmaps */
456 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
457 templ
->depth0
!= 1 || templ
->last_level
!= 0)
460 bo
= r600_bo_handle(rw
, whandle
->handle
, &array_mode
);
465 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
471 static unsigned int r600_texture_is_referenced(struct pipe_context
*context
,
472 struct pipe_resource
*texture
,
473 unsigned level
, int layer
)
476 return PIPE_REFERENCED_FOR_READ
| PIPE_REFERENCED_FOR_WRITE
;
479 int r600_texture_depth_flush(struct pipe_context
*ctx
,
480 struct pipe_resource
*texture
)
482 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
483 struct pipe_resource resource
;
485 if (rtex
->flushed_depth_texture
)
488 resource
.target
= PIPE_TEXTURE_2D
;
489 resource
.format
= texture
->format
;
490 resource
.width0
= texture
->width0
;
491 resource
.height0
= texture
->height0
;
493 resource
.last_level
= 0;
494 resource
.nr_samples
= 0;
495 resource
.usage
= PIPE_USAGE_DYNAMIC
;
497 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
499 resource
.bind
|= PIPE_BIND_DEPTH_STENCIL
;
501 rtex
->flushed_depth_texture
= (struct r600_resource_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
502 if (rtex
->flushed_depth_texture
== NULL
) {
503 R600_ERR("failed to create temporary texture to hold untiled copy\n");
507 ((struct r600_resource_texture
*)rtex
->flushed_depth_texture
)->is_flushing_texture
= TRUE
;
509 /* XXX: only do this if the depth texture has actually changed:
511 r600_blit_uncompress_depth(ctx
, rtex
);
515 /* Needs adjustment for pixelformat:
517 static INLINE
unsigned u_box_volume( const struct pipe_box
*box
)
519 return box
->width
* box
->depth
* box
->height
;
522 struct pipe_transfer
* r600_texture_get_transfer(struct pipe_context
*ctx
,
523 struct pipe_resource
*texture
,
526 const struct pipe_box
*box
)
528 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
529 struct pipe_resource resource
;
530 struct r600_transfer
*trans
;
532 boolean use_staging_texture
= FALSE
;
534 /* We cannot map a tiled texture directly because the data is
535 * in a different order, therefore we do detiling using a blit.
537 * Also, use a temporary in GTT memory for read transfers, as
538 * the CPU is much happier reading out of cached system memory
539 * than uncached VRAM.
542 use_staging_texture
= TRUE
;
544 if ((usage
& PIPE_TRANSFER_READ
) && u_box_volume(box
) > 1024)
545 use_staging_texture
= TRUE
;
547 /* XXX: Use a staging texture for uploads if the underlying BO
548 * is busy. No interface for checking that currently? so do
549 * it eagerly whenever the transfer doesn't require a readback
552 if ((usage
& PIPE_TRANSFER_WRITE
) &&
553 !(usage
& (PIPE_TRANSFER_READ
|
554 PIPE_TRANSFER_DONTBLOCK
|
555 PIPE_TRANSFER_UNSYNCHRONIZED
)))
556 use_staging_texture
= TRUE
;
558 if (!permit_hardware_blit(ctx
->screen
, texture
) ||
559 (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
))
560 use_staging_texture
= FALSE
;
562 trans
= CALLOC_STRUCT(r600_transfer
);
565 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
566 trans
->transfer
.level
= level
;
567 trans
->transfer
.usage
= usage
;
568 trans
->transfer
.box
= *box
;
570 /* XXX: only readback the rectangle which is being mapped?
572 /* XXX: when discard is true, no need to read back from depth texture
574 r
= r600_texture_depth_flush(ctx
, texture
);
576 R600_ERR("failed to create temporary texture to hold untiled copy\n");
577 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
581 trans
->transfer
.stride
= rtex
->flushed_depth_texture
->pitch_in_bytes
[level
];
582 trans
->offset
= r600_texture_get_offset(rtex
->flushed_depth_texture
, level
, box
->z
);
583 return &trans
->transfer
;
584 } else if (use_staging_texture
) {
585 resource
.target
= PIPE_TEXTURE_2D
;
586 resource
.format
= texture
->format
;
587 resource
.width0
= box
->width
;
588 resource
.height0
= box
->height
;
590 resource
.array_size
= 1;
591 resource
.last_level
= 0;
592 resource
.nr_samples
= 0;
593 resource
.usage
= PIPE_USAGE_STAGING
;
595 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
596 /* For texture reading, the temporary (detiled) texture is used as
597 * a render target when blitting from a tiled texture. */
598 if (usage
& PIPE_TRANSFER_READ
) {
599 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
601 /* For texture writing, the temporary texture is used as a sampler
602 * when blitting into a tiled texture. */
603 if (usage
& PIPE_TRANSFER_WRITE
) {
604 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
606 /* Create the temporary texture. */
607 trans
->staging_texture
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
608 if (trans
->staging_texture
== NULL
) {
609 R600_ERR("failed to create temporary texture to hold untiled copy\n");
610 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
615 trans
->transfer
.stride
=
616 ((struct r600_resource_texture
*)trans
->staging_texture
)->pitch_in_bytes
[0];
617 if (usage
& PIPE_TRANSFER_READ
) {
618 r600_copy_to_staging_texture(ctx
, trans
);
619 /* Always referenced in the blit. */
620 ctx
->flush(ctx
, 0, NULL
);
622 return &trans
->transfer
;
624 trans
->transfer
.stride
= rtex
->pitch_in_bytes
[level
];
625 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
626 return &trans
->transfer
;
629 void r600_texture_transfer_destroy(struct pipe_context
*ctx
,
630 struct pipe_transfer
*transfer
)
632 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
633 struct pipe_resource
*texture
= transfer
->resource
;
634 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
636 if (rtransfer
->staging_texture
) {
637 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
638 r600_copy_from_staging_texture(ctx
, rtransfer
);
640 pipe_resource_reference(&rtransfer
->staging_texture
, NULL
);
643 if (rtex
->depth
&& !rtex
->is_flushing_texture
) {
644 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtex
->flushed_depth_texture
)
645 r600_blit_push_depth(ctx
, rtex
);
648 pipe_resource_reference(&transfer
->resource
, NULL
);
652 void* r600_texture_transfer_map(struct pipe_context
*ctx
,
653 struct pipe_transfer
* transfer
)
655 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
657 enum pipe_format format
= transfer
->resource
->format
;
658 struct radeon
*radeon
= (struct radeon
*)ctx
->screen
->winsys
;
663 if (rtransfer
->staging_texture
) {
664 bo
= ((struct r600_resource
*)rtransfer
->staging_texture
)->bo
;
666 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
668 if (rtex
->flushed_depth_texture
)
669 bo
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->bo
;
671 bo
= ((struct r600_resource
*)transfer
->resource
)->bo
;
673 offset
= rtransfer
->offset
+
674 transfer
->box
.y
/ util_format_get_blockheight(format
) * transfer
->stride
+
675 transfer
->box
.x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
678 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
679 usage
|= PB_USAGE_CPU_WRITE
;
681 if (transfer
->usage
& PIPE_TRANSFER_DISCARD
) {
684 if (transfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
) {
688 if (transfer
->usage
& PIPE_TRANSFER_READ
) {
689 usage
|= PB_USAGE_CPU_READ
;
692 if (transfer
->usage
& PIPE_TRANSFER_DONTBLOCK
) {
693 usage
|= PB_USAGE_DONTBLOCK
;
696 if (transfer
->usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
697 usage
|= PB_USAGE_UNSYNCHRONIZED
;
700 map
= r600_bo_map(radeon
, bo
, usage
, ctx
);
708 void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
709 struct pipe_transfer
* transfer
)
711 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
712 struct radeon
*radeon
= (struct radeon
*)ctx
->screen
->winsys
;
715 if (rtransfer
->staging_texture
) {
716 bo
= ((struct r600_resource
*)rtransfer
->staging_texture
)->bo
;
718 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
720 if (rtex
->flushed_depth_texture
) {
721 bo
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->bo
;
723 bo
= ((struct r600_resource
*)transfer
->resource
)->bo
;
726 r600_bo_unmap(radeon
, bo
);
729 struct u_resource_vtbl r600_texture_vtbl
=
731 r600_texture_get_handle
, /* get_handle */
732 r600_texture_destroy
, /* resource_destroy */
733 r600_texture_is_referenced
, /* is_resource_referenced */
734 r600_texture_get_transfer
, /* get_transfer */
735 r600_texture_transfer_destroy
, /* transfer_destroy */
736 r600_texture_transfer_map
, /* transfer_map */
737 u_default_transfer_flush_region
,/* transfer_flush_region */
738 r600_texture_transfer_unmap
, /* transfer_unmap */
739 u_default_transfer_inline_write
/* transfer_inline_write */
742 void r600_init_surface_functions(struct r600_pipe_context
*r600
)
744 r600
->context
.create_surface
= r600_create_surface
;
745 r600
->context
.surface_destroy
= r600_surface_destroy
;
748 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
749 const unsigned char *swizzle_view
)
752 unsigned char swizzle
[4];
754 const uint32_t swizzle_shift
[4] = {
757 const uint32_t swizzle_bit
[4] = {
762 /* Combine two sets of swizzles. */
763 for (i
= 0; i
< 4; i
++) {
764 swizzle
[i
] = swizzle_view
[i
] <= UTIL_FORMAT_SWIZZLE_W
?
765 swizzle_format
[swizzle_view
[i
]] : swizzle_view
[i
];
768 memcpy(swizzle
, swizzle_format
, 4);
772 for (i
= 0; i
< 4; i
++) {
773 switch (swizzle
[i
]) {
774 case UTIL_FORMAT_SWIZZLE_Y
:
775 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
777 case UTIL_FORMAT_SWIZZLE_Z
:
778 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
780 case UTIL_FORMAT_SWIZZLE_W
:
781 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
783 case UTIL_FORMAT_SWIZZLE_0
:
784 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
786 case UTIL_FORMAT_SWIZZLE_1
:
787 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
789 default: /* UTIL_FORMAT_SWIZZLE_X */
790 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
796 /* texture format translate */
797 uint32_t r600_translate_texformat(enum pipe_format format
,
798 const unsigned char *swizzle_view
,
799 uint32_t *word4_p
, uint32_t *yuv_format_p
)
801 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
802 const struct util_format_description
*desc
;
803 boolean uniform
= TRUE
;
805 const uint32_t sign_bit
[4] = {
806 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
807 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
808 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
809 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
811 desc
= util_format_description(format
);
813 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
815 /* Colorspace (return non-RGB formats directly). */
816 switch (desc
->colorspace
) {
817 /* Depth stencil formats */
818 case UTIL_FORMAT_COLORSPACE_ZS
:
820 case PIPE_FORMAT_Z16_UNORM
:
823 case PIPE_FORMAT_X24S8_USCALED
:
824 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
825 case PIPE_FORMAT_Z24X8_UNORM
:
826 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
829 case PIPE_FORMAT_S8X24_USCALED
:
830 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
831 case PIPE_FORMAT_X8Z24_UNORM
:
832 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
835 case PIPE_FORMAT_S8_USCALED
:
837 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
843 case UTIL_FORMAT_COLORSPACE_YUV
:
844 yuv_format
|= (1 << 30);
846 case PIPE_FORMAT_UYVY
:
847 case PIPE_FORMAT_YUYV
:
851 goto out_unknown
; /* TODO */
853 case UTIL_FORMAT_COLORSPACE_SRGB
:
854 word4
|= S_038010_FORCE_DEGAMMA(1);
855 if (format
== PIPE_FORMAT_L8A8_SRGB
|| format
== PIPE_FORMAT_L8_SRGB
)
856 goto out_unknown
; /* fails for some reason - TODO */
863 /* S3TC formats. TODO */
864 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
865 static int r600_enable_s3tc
= -1;
867 if (r600_enable_s3tc
== -1)
869 debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
871 if (!r600_enable_s3tc
)
875 case PIPE_FORMAT_DXT1_RGB
:
876 case PIPE_FORMAT_DXT1_RGBA
:
879 case PIPE_FORMAT_DXT3_RGBA
:
882 case PIPE_FORMAT_DXT5_RGBA
:
891 for (i
= 0; i
< desc
->nr_channels
; i
++) {
892 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
893 word4
|= sign_bit
[i
];
897 /* R8G8Bx_SNORM - TODO CxV8U8 */
901 /* See whether the components are of the same size. */
902 for (i
= 1; i
< desc
->nr_channels
; i
++) {
903 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
906 /* Non-uniform formats. */
908 switch(desc
->nr_channels
) {
910 if (desc
->channel
[0].size
== 5 &&
911 desc
->channel
[1].size
== 6 &&
912 desc
->channel
[2].size
== 5) {
918 if (desc
->channel
[0].size
== 5 &&
919 desc
->channel
[1].size
== 5 &&
920 desc
->channel
[2].size
== 5 &&
921 desc
->channel
[3].size
== 1) {
922 result
= FMT_1_5_5_5
;
925 if (desc
->channel
[0].size
== 10 &&
926 desc
->channel
[1].size
== 10 &&
927 desc
->channel
[2].size
== 10 &&
928 desc
->channel
[3].size
== 2) {
929 result
= FMT_2_10_10_10
;
937 /* Find the first non-VOID channel. */
938 for (i
= 0; i
< 4; i
++) {
939 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
947 /* uniform formats */
948 switch (desc
->channel
[i
].type
) {
949 case UTIL_FORMAT_TYPE_UNSIGNED
:
950 case UTIL_FORMAT_TYPE_SIGNED
:
951 if (!desc
->channel
[i
].normalized
&&
952 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
956 switch (desc
->channel
[i
].size
) {
958 switch (desc
->nr_channels
) {
963 result
= FMT_4_4_4_4
;
968 switch (desc
->nr_channels
) {
976 result
= FMT_8_8_8_8
;
981 switch (desc
->nr_channels
) {
989 result
= FMT_16_16_16_16
;
995 case UTIL_FORMAT_TYPE_FLOAT
:
996 switch (desc
->channel
[i
].size
) {
998 switch (desc
->nr_channels
) {
1000 result
= FMT_16_FLOAT
;
1003 result
= FMT_16_16_FLOAT
;
1006 result
= FMT_16_16_16_16_FLOAT
;
1011 switch (desc
->nr_channels
) {
1013 result
= FMT_32_FLOAT
;
1016 result
= FMT_32_32_FLOAT
;
1019 result
= FMT_32_32_32_32_FLOAT
;
1029 *yuv_format_p
= yuv_format
;
1032 // R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));