projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: fix stencil texturing with Z32_FLOAT_S8X24_UINT
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
36 {
37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
38 struct pipe_resource *texture = transfer->resource;
39
40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b,
41 0, 0, 0, 0, texture, transfer->level,
42 &transfer->box);
43 }
44
45
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
48 {
49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
50 struct pipe_resource *texture = transfer->resource;
51 struct pipe_box sbox;
52
53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
54
55 ctx->resource_copy_region(ctx, texture, transfer->level,
56 transfer->box.x, transfer->box.y, transfer->box.z,
57 &rtransfer->staging->b.b,
58 0, &sbox);
59 }
60
61 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
62 unsigned level, unsigned layer)
63 {
64 unsigned offset = rtex->offset[level];
65
66 switch (rtex->resource.b.b.target) {
67 case PIPE_TEXTURE_3D:
68 case PIPE_TEXTURE_CUBE:
69 default:
70 return offset + layer * rtex->layer_size[level];
71 }
72 }
73
74 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
75 enum pipe_format format,
76 unsigned array_mode)
77 {
78 struct r600_screen* rscreen = (struct r600_screen *)screen;
79 unsigned pixsize = util_format_get_blocksize(format);
80 int p_align;
81
82 switch(array_mode) {
83 case V_038000_ARRAY_1D_TILED_THIN1:
84 p_align = MAX2(8,
85 ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
86 break;
87 case V_038000_ARRAY_2D_TILED_THIN1:
88 p_align = MAX2(rscreen->tiling_info.num_banks,
89 (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
90 rscreen->tiling_info.num_banks)) * 8;
91 break;
92 case V_038000_ARRAY_LINEAR_ALIGNED:
93 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
94 break;
95 case V_038000_ARRAY_LINEAR_GENERAL:
96 default:
97 p_align = rscreen->tiling_info.group_bytes / pixsize;
98 break;
99 }
100 return p_align;
101 }
102
103 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
104 unsigned array_mode)
105 {
106 struct r600_screen* rscreen = (struct r600_screen *)screen;
107 int h_align;
108
109 switch (array_mode) {
110 case V_038000_ARRAY_2D_TILED_THIN1:
111 h_align = rscreen->tiling_info.num_channels * 8;
112 break;
113 case V_038000_ARRAY_1D_TILED_THIN1:
114 case V_038000_ARRAY_LINEAR_ALIGNED:
115 h_align = 8;
116 break;
117 case V_038000_ARRAY_LINEAR_GENERAL:
118 default:
119 h_align = 1;
120 break;
121 }
122 return h_align;
123 }
124
125 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
126 enum pipe_format format,
127 unsigned array_mode)
128 {
129 struct r600_screen* rscreen = (struct r600_screen *)screen;
130 unsigned pixsize = util_format_get_blocksize(format);
131 int p_align = r600_get_block_alignment(screen, format, array_mode);
132 int h_align = r600_get_height_alignment(screen, array_mode);
133 int b_align;
134
135 switch (array_mode) {
136 case V_038000_ARRAY_2D_TILED_THIN1:
137 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
138 p_align * pixsize * h_align);
139 break;
140 case V_038000_ARRAY_1D_TILED_THIN1:
141 case V_038000_ARRAY_LINEAR_ALIGNED:
142 case V_038000_ARRAY_LINEAR_GENERAL:
143 default:
144 b_align = rscreen->tiling_info.group_bytes;
145 break;
146 }
147 return b_align;
148 }
149
150 static unsigned mip_minify(unsigned size, unsigned level)
151 {
152 unsigned val;
153 val = u_minify(size, level);
154 if (level > 0)
155 val = util_next_power_of_two(val);
156 return val;
157 }
158
159 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
160 struct r600_resource_texture *rtex,
161 unsigned level)
162 {
163 struct pipe_resource *ptex = &rtex->resource.b.b;
164 unsigned nblocksx, block_align, width;
165 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
166
167 if (rtex->pitch_override)
168 return rtex->pitch_override / blocksize;
169
170 width = mip_minify(ptex->width0, level);
171 nblocksx = util_format_get_nblocksx(rtex->real_format, width);
172
173 block_align = r600_get_block_alignment(screen, rtex->real_format,
174 rtex->array_mode[level]);
175 nblocksx = align(nblocksx, block_align);
176 return nblocksx;
177 }
178
179 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
180 struct r600_resource_texture *rtex,
181 unsigned level)
182 {
183 struct pipe_resource *ptex = &rtex->resource.b.b;
184 unsigned height, tile_height;
185
186 height = mip_minify(ptex->height0, level);
187 height = util_format_get_nblocksy(rtex->real_format, height);
188 tile_height = r600_get_height_alignment(screen,
189 rtex->array_mode[level]);
190
191 /* XXX Hack around an alignment issue. Less tests fail with this.
192 *
193 * The thing is depth-stencil buffers should be tiled, i.e.
194 * the alignment should be >=8. If I make them tiled, stencil starts
195 * working because it no longer overlaps with the depth buffer
196 * in memory, but texturing like drawpix-stencil breaks. */
197 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
198 tile_height = 8;
199
200 height = align(height, tile_height);
201 return height;
202 }
203
204 static void r600_texture_set_array_mode(struct pipe_screen *screen,
205 struct r600_resource_texture *rtex,
206 unsigned level, unsigned array_mode)
207 {
208 struct pipe_resource *ptex = &rtex->resource.b.b;
209
210 switch (array_mode) {
211 case V_0280A0_ARRAY_LINEAR_GENERAL:
212 case V_0280A0_ARRAY_LINEAR_ALIGNED:
213 case V_0280A0_ARRAY_1D_TILED_THIN1:
214 default:
215 rtex->array_mode[level] = array_mode;
216 break;
217 case V_0280A0_ARRAY_2D_TILED_THIN1:
218 {
219 unsigned w, h, tile_height, tile_width;
220
221 tile_height = r600_get_height_alignment(screen, array_mode);
222 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
223
224 w = mip_minify(ptex->width0, level);
225 h = mip_minify(ptex->height0, level);
226 if (w <= tile_width || h <= tile_height)
227 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
228 else
229 rtex->array_mode[level] = array_mode;
230 }
231 break;
232 }
233 }
234
235 static int r600_init_surface(struct radeon_surface *surface,
236 const struct pipe_resource *ptex,
237 unsigned array_mode, bool is_transfer)
238 {
239 surface->npix_x = ptex->width0;
240 surface->npix_y = ptex->height0;
241 surface->npix_z = ptex->depth0;
242 surface->blk_w = util_format_get_blockwidth(ptex->format);
243 surface->blk_h = util_format_get_blockheight(ptex->format);
244 surface->blk_d = 1;
245 surface->array_size = 1;
246 surface->last_level = ptex->last_level;
247 surface->bpe = util_format_get_blocksize(ptex->format);
248 /* align byte per element on dword */
249 if (surface->bpe == 3) {
250 surface->bpe = 4;
251 }
252 surface->nsamples = 1;
253 surface->flags = 0;
254 switch (array_mode) {
255 case V_038000_ARRAY_1D_TILED_THIN1:
256 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
257 break;
258 case V_038000_ARRAY_2D_TILED_THIN1:
259 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
260 break;
261 case V_038000_ARRAY_LINEAR_ALIGNED:
262 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
263 break;
264 case V_038000_ARRAY_LINEAR_GENERAL:
265 default:
266 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
267 break;
268 }
269 switch (ptex->target) {
270 case PIPE_TEXTURE_1D:
271 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
272 break;
273 case PIPE_TEXTURE_RECT:
274 case PIPE_TEXTURE_2D:
275 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
276 break;
277 case PIPE_TEXTURE_3D:
278 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
279 break;
280 case PIPE_TEXTURE_1D_ARRAY:
281 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
282 surface->array_size = ptex->array_size;
283 break;
284 case PIPE_TEXTURE_2D_ARRAY:
285 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
286 surface->array_size = ptex->array_size;
287 break;
288 case PIPE_TEXTURE_CUBE:
289 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
290 break;
291 case PIPE_BUFFER:
292 default:
293 return -EINVAL;
294 }
295 if (ptex->bind & PIPE_BIND_SCANOUT) {
296 surface->flags |= RADEON_SURF_SCANOUT;
297 }
298 if (util_format_is_depth_and_stencil(ptex->format) && !is_transfer) {
299 surface->flags |= RADEON_SURF_ZBUFFER;
300 surface->flags |= RADEON_SURF_SBUFFER;
301 }
302
303 return 0;
304 }
305
306 static int r600_setup_surface(struct pipe_screen *screen,
307 struct r600_resource_texture *rtex,
308 unsigned array_mode,
309 unsigned pitch_in_bytes_override)
310 {
311 struct pipe_resource *ptex = &rtex->resource.b.b;
312 struct r600_screen *rscreen = (struct r600_screen*)screen;
313 unsigned i;
314 int r;
315
316 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
317 if (r) {
318 return r;
319 }
320 rtex->size = rtex->surface.bo_size;
321 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
322 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
323 * for those
324 */
325 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
326 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
327 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
328 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
329 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
330 }
331 }
332 for (i = 0; i <= ptex->last_level; i++) {
333 rtex->offset[i] = rtex->surface.level[i].offset;
334 rtex->layer_size[i] = rtex->surface.level[i].slice_size;
335 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
336 switch (rtex->surface.level[i].mode) {
337 case RADEON_SURF_MODE_LINEAR_ALIGNED:
338 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
339 break;
340 case RADEON_SURF_MODE_1D:
341 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
342 break;
343 case RADEON_SURF_MODE_2D:
344 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
345 break;
346 default:
347 case RADEON_SURF_MODE_LINEAR:
348 rtex->array_mode[i] = 0;
349 break;
350 }
351 }
352 return 0;
353 }
354
355 static void r600_setup_miptree(struct pipe_screen *screen,
356 struct r600_resource_texture *rtex,
357 unsigned array_mode)
358 {
359 struct pipe_resource *ptex = &rtex->resource.b.b;
360 enum chip_class chipc = ((struct r600_screen*)screen)->chip_class;
361 unsigned size, layer_size, i, offset;
362 unsigned nblocksx, nblocksy;
363
364 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
365 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
366 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
367
368 r600_texture_set_array_mode(screen, rtex, i, array_mode);
369
370 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
371 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
372
373 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL)
374 layer_size = align(nblocksx, 64) * nblocksy * blocksize;
375 else
376 layer_size = nblocksx * nblocksy * blocksize;
377
378 if (ptex->target == PIPE_TEXTURE_CUBE) {
379 if (chipc >= R700)
380 size = layer_size * 8;
381 else
382 size = layer_size * 6;
383 }
384 else if (ptex->target == PIPE_TEXTURE_3D)
385 size = layer_size * u_minify(ptex->depth0, i);
386 else
387 size = layer_size * ptex->array_size;
388
389 /* align base image and start of miptree */
390 if ((i == 0) || (i == 1))
391 offset = align(offset, base_align);
392 rtex->offset[i] = offset;
393 rtex->layer_size[i] = layer_size;
394 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
395 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
396
397 offset += size;
398 }
399 rtex->size = offset;
400 }
401
402 /* Figure out whether u_blitter will fallback to a transfer operation.
403 * If so, don't use a staging resource.
404 */
405 static boolean permit_hardware_blit(struct pipe_screen *screen,
406 const struct pipe_resource *res)
407 {
408 unsigned bind;
409
410 if (util_format_is_depth_or_stencil(res->format))
411 bind = PIPE_BIND_DEPTH_STENCIL;
412 else
413 bind = PIPE_BIND_RENDER_TARGET;
414
415 /* hackaround for S3TC */
416 if (util_format_is_compressed(res->format))
417 return TRUE;
418
419 if (!screen->is_format_supported(screen,
420 res->format,
421 res->target,
422 res->nr_samples,
423 bind))
424 return FALSE;
425
426 if (!screen->is_format_supported(screen,
427 res->format,
428 res->target,
429 res->nr_samples,
430 PIPE_BIND_SAMPLER_VIEW))
431 return FALSE;
432
433 return TRUE;
434 }
435
436 static boolean r600_texture_get_handle(struct pipe_screen* screen,
437 struct pipe_resource *ptex,
438 struct winsys_handle *whandle)
439 {
440 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
441 struct r600_resource *resource = &rtex->resource;
442 struct radeon_surface *surface = &rtex->surface;
443 struct r600_screen *rscreen = (struct r600_screen*)screen;
444
445 rscreen->ws->buffer_set_tiling(resource->buf,
446 NULL,
447 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
448 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
449 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
450 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
451 surface->bankw, surface->bankh,
452 surface->tile_split,
453 surface->stencil_tile_split,
454 surface->mtilea,
455 rtex->pitch_in_bytes[0]);
456
457 return rscreen->ws->buffer_get_handle(resource->buf,
458 rtex->pitch_in_bytes[0], whandle);
459 }
460
461 static void r600_texture_destroy(struct pipe_screen *screen,
462 struct pipe_resource *ptex)
463 {
464 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
465 struct r600_resource *resource = &rtex->resource;
466
467 if (rtex->flushed_depth_texture)
468 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
469
470 if (rtex->stencil)
471 pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL);
472
473 pb_reference(&resource->buf, NULL);
474 FREE(rtex);
475 }
476
477 static const struct u_resource_vtbl r600_texture_vtbl =
478 {
479 r600_texture_get_handle, /* get_handle */
480 r600_texture_destroy, /* resource_destroy */
481 r600_texture_get_transfer, /* get_transfer */
482 r600_texture_transfer_destroy, /* transfer_destroy */
483 r600_texture_transfer_map, /* transfer_map */
484 NULL, /* transfer_flush_region */
485 r600_texture_transfer_unmap, /* transfer_unmap */
486 NULL /* transfer_inline_write */
487 };
488
489 static struct r600_resource_texture *
490 r600_texture_create_object(struct pipe_screen *screen,
491 const struct pipe_resource *base,
492 unsigned array_mode,
493 unsigned pitch_in_bytes_override,
494 unsigned max_buffer_size,
495 struct pb_buffer *buf,
496 boolean alloc_bo,
497 struct radeon_surface *surface)
498 {
499 struct r600_resource_texture *rtex;
500 struct r600_resource *resource;
501 struct r600_screen *rscreen = (struct r600_screen*)screen;
502 int r;
503
504 rtex = CALLOC_STRUCT(r600_resource_texture);
505 if (rtex == NULL)
506 return NULL;
507
508 resource = &rtex->resource;
509 resource->b.b = *base;
510 resource->b.vtbl = &r600_texture_vtbl;
511 pipe_reference_init(&resource->b.b.reference, 1);
512 resource->b.b.screen = screen;
513 rtex->pitch_override = pitch_in_bytes_override;
514 rtex->real_format = base->format;
515
516 /* We must split depth and stencil into two separate buffers on Evergreen. */
517 if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) &&
518 ((struct r600_screen*)screen)->chip_class >= EVERGREEN &&
519 util_format_is_depth_and_stencil(base->format) &&
520 !rscreen->use_surface_alloc) {
521 struct pipe_resource stencil;
522 unsigned stencil_pitch_override = 0;
523
524 switch (base->format) {
525 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
526 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
527 break;
528 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
529 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
530 break;
531 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
532 rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
533 break;
534 default:
535 assert(0);
536 FREE(rtex);
537 return NULL;
538 }
539
540 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
541 if (pitch_in_bytes_override) {
542 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT ||
543 base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
544 stencil_pitch_override = pitch_in_bytes_override / 4;
545 }
546
547 /* Allocate the stencil buffer. */
548 stencil = *base;
549 stencil.format = PIPE_FORMAT_S8_UINT;
550 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
551 stencil_pitch_override,
552 max_buffer_size, NULL, FALSE, surface);
553 if (!rtex->stencil) {
554 FREE(rtex);
555 return NULL;
556 }
557 /* Proceed in creating the depth buffer. */
558 }
559
560 /* only mark depth textures the HW can hit as depth textures */
561 if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
562 rtex->is_depth = true;
563
564 r600_setup_miptree(screen, rtex, array_mode);
565 if (rscreen->use_surface_alloc) {
566 rtex->surface = *surface;
567 r = r600_setup_surface(screen, rtex, array_mode,
568 pitch_in_bytes_override);
569 if (r) {
570 FREE(rtex);
571 return NULL;
572 }
573 }
574
575 /* If we initialized separate stencil for Evergreen. place it after depth. */
576 if (rtex->stencil) {
577 unsigned stencil_align, stencil_offset;
578
579 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
580 stencil_offset = align(rtex->size, stencil_align);
581
582 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.last_level; i++)
583 rtex->stencil->offset[i] += stencil_offset;
584
585 rtex->size = stencil_offset + rtex->stencil->size;
586 }
587
588 /* Now create the backing buffer. */
589 if (!buf && alloc_bo) {
590 struct pipe_resource *ptex = &rtex->resource.b.b;
591 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
592
593 if (rscreen->use_surface_alloc) {
594 base_align = rtex->surface.bo_alignment;
595 } else if (util_format_is_depth_or_stencil(rtex->real_format)) {
596 /* ugly work around depth buffer need stencil room at end of bo */
597 rtex->size += ptex->width0 * ptex->height0;
598 }
599 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
600 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
601 FREE(rtex);
602 return NULL;
603 }
604 } else if (buf) {
605 resource->buf = buf;
606 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
607 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
608 }
609
610 if (rtex->stencil) {
611 pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf);
612 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf;
613 rtex->stencil->resource.domains = rtex->resource.domains;
614 }
615 return rtex;
616 }
617
618 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
619 const struct pipe_resource *templ)
620 {
621 struct r600_screen *rscreen = (struct r600_screen*)screen;
622 struct radeon_surface surface;
623 unsigned array_mode = 0;
624 int r;
625
626 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) {
627 if (rscreen->use_surface_alloc &&
628 !(templ->bind & PIPE_BIND_SCANOUT) &&
629 templ->usage != PIPE_USAGE_STAGING &&
630 templ->usage != PIPE_USAGE_STREAM &&
631 permit_hardware_blit(screen, templ)) {
632 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
633 } else if (util_format_is_compressed(templ->format)) {
634 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
635 }
636 }
637
638 r = r600_init_surface(&surface, templ, array_mode,
639 templ->flags & R600_RESOURCE_FLAG_TRANSFER);
640 if (r) {
641 return NULL;
642 }
643 r = rscreen->ws->surface_best(rscreen->ws, &surface);
644 if (r) {
645 return NULL;
646 }
647 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
648 0, 0, NULL, TRUE, &surface);
649 }
650
651 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
652 struct pipe_resource *texture,
653 const struct pipe_surface *surf_tmpl)
654 {
655 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
656 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
657 unsigned level = surf_tmpl->u.tex.level;
658
659 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
660 if (surface == NULL)
661 return NULL;
662 pipe_reference_init(&surface->base.reference, 1);
663 pipe_resource_reference(&surface->base.texture, texture);
664 surface->base.context = pipe;
665 surface->base.format = surf_tmpl->format;
666 surface->base.width = mip_minify(texture->width0, level);
667 surface->base.height = mip_minify(texture->height0, level);
668 surface->base.usage = surf_tmpl->usage;
669 surface->base.texture = texture;
670 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
671 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
672 surface->base.u.tex.level = level;
673
674 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
675 rtex, level);
676 return &surface->base;
677 }
678
679 static void r600_surface_destroy(struct pipe_context *pipe,
680 struct pipe_surface *surface)
681 {
682 pipe_resource_reference(&surface->texture, NULL);
683 FREE(surface);
684 }
685
686 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
687 const struct pipe_resource *templ,
688 struct winsys_handle *whandle)
689 {
690 struct r600_screen *rscreen = (struct r600_screen*)screen;
691 struct pb_buffer *buf = NULL;
692 unsigned stride = 0;
693 unsigned array_mode = 0;
694 enum radeon_bo_layout micro, macro;
695 struct radeon_surface surface;
696 int r;
697
698 /* Support only 2D textures without mipmaps */
699 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
700 templ->depth0 != 1 || templ->last_level != 0)
701 return NULL;
702
703 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
704 if (!buf)
705 return NULL;
706
707 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
708 &surface.bankw, &surface.bankh,
709 &surface.tile_split,
710 &surface.stencil_tile_split,
711 &surface.mtilea);
712
713 if (macro == RADEON_LAYOUT_TILED)
714 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
715 else if (micro == RADEON_LAYOUT_TILED)
716 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
717 else
718 array_mode = 0;
719
720 r = r600_init_surface(&surface, templ, array_mode, 0);
721 if (r) {
722 return NULL;
723 }
724 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
725 stride, 0, buf, FALSE, &surface);
726 }
727
728 void r600_init_flushed_depth_texture(struct pipe_context *ctx,
729 struct pipe_resource *texture)
730 {
731 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
732 struct pipe_resource resource;
733
734 if (rtex->flushed_depth_texture)
735 return; /* it's ready */
736
737 resource.target = texture->target;
738 resource.format = texture->format;
739 resource.width0 = texture->width0;
740 resource.height0 = texture->height0;
741 resource.depth0 = texture->depth0;
742 resource.array_size = texture->array_size;
743 resource.last_level = texture->last_level;
744 resource.nr_samples = texture->nr_samples;
745 resource.usage = PIPE_USAGE_DYNAMIC;
746 resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL;
747 resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags;
748
749 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
750 if (rtex->flushed_depth_texture == NULL) {
751 R600_ERR("failed to create temporary texture to hold untiled copy\n");
752 return;
753 }
754
755 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
756 }
757
758 void r600_texture_depth_flush(struct pipe_context *ctx,
759 struct pipe_resource *texture)
760 {
761 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
762
763 r600_init_flushed_depth_texture(ctx, texture);
764
765 if (!rtex->flushed_depth_texture)
766 return; /* error */
767
768 /* XXX: only do this if the depth texture has actually changed:
769 */
770 r600_blit_uncompress_depth(ctx, rtex);
771 }
772
773 /* Needs adjustment for pixelformat:
774 */
775 static INLINE unsigned u_box_volume( const struct pipe_box *box )
776 {
777 return box->width * box->depth * box->height;
778 }
779
780 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
781 struct pipe_resource *texture,
782 unsigned level,
783 unsigned usage,
784 const struct pipe_box *box)
785 {
786 struct r600_context *rctx = (struct r600_context*)ctx;
787 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
788 struct pipe_resource resource;
789 struct r600_transfer *trans;
790 boolean use_staging_texture = FALSE;
791
792 /* We cannot map a tiled texture directly because the data is
793 * in a different order, therefore we do detiling using a blit.
794 *
795 * Also, use a temporary in GTT memory for read transfers, as
796 * the CPU is much happier reading out of cached system memory
797 * than uncached VRAM.
798 */
799 if (R600_TEX_IS_TILED(rtex, level)) {
800 use_staging_texture = TRUE;
801 }
802
803 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
804 use_staging_texture = TRUE;
805
806 /* Use a staging texture for uploads if the underlying BO is busy. */
807 if (!(usage & PIPE_TRANSFER_READ) &&
808 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
809 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
810 use_staging_texture = TRUE;
811 }
812
813 if (!permit_hardware_blit(ctx->screen, texture) ||
814 (texture->flags & R600_RESOURCE_FLAG_TRANSFER)) {
815 use_staging_texture = FALSE;
816 }
817
818 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
819 return NULL;
820 }
821
822 trans = CALLOC_STRUCT(r600_transfer);
823 if (trans == NULL)
824 return NULL;
825 pipe_resource_reference(&trans->transfer.resource, texture);
826 trans->transfer.level = level;
827 trans->transfer.usage = usage;
828 trans->transfer.box = *box;
829 if (rtex->is_depth) {
830 /* XXX: only readback the rectangle which is being mapped?
831 */
832 /* XXX: when discard is true, no need to read back from depth texture
833 */
834 r600_texture_depth_flush(ctx, texture);
835 if (!rtex->flushed_depth_texture) {
836 R600_ERR("failed to create temporary texture to hold untiled copy\n");
837 pipe_resource_reference(&trans->transfer.resource, NULL);
838 FREE(trans);
839 return NULL;
840 }
841 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
842 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
843 return &trans->transfer;
844 } else if (use_staging_texture) {
845 resource.target = PIPE_TEXTURE_2D;
846 resource.format = texture->format;
847 resource.width0 = box->width;
848 resource.height0 = box->height;
849 resource.depth0 = 1;
850 resource.array_size = 1;
851 resource.last_level = 0;
852 resource.nr_samples = 0;
853 resource.usage = PIPE_USAGE_STAGING;
854 resource.bind = 0;
855 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
856 /* For texture reading, the temporary (detiled) texture is used as
857 * a render target when blitting from a tiled texture. */
858 if (usage & PIPE_TRANSFER_READ) {
859 resource.bind |= PIPE_BIND_RENDER_TARGET;
860 }
861 /* For texture writing, the temporary texture is used as a sampler
862 * when blitting into a tiled texture. */
863 if (usage & PIPE_TRANSFER_WRITE) {
864 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
865 }
866 /* Create the temporary texture. */
867 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
868 if (trans->staging == NULL) {
869 R600_ERR("failed to create temporary texture to hold untiled copy\n");
870 pipe_resource_reference(&trans->transfer.resource, NULL);
871 FREE(trans);
872 return NULL;
873 }
874
875 trans->transfer.stride =
876 ((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0];
877 if (usage & PIPE_TRANSFER_READ) {
878 r600_copy_to_staging_texture(ctx, trans);
879 /* Always referenced in the blit. */
880 r600_flush(ctx, NULL, 0);
881 }
882 return &trans->transfer;
883 }
884 trans->transfer.stride = rtex->pitch_in_bytes[level];
885 trans->transfer.layer_stride = rtex->layer_size[level];
886 trans->offset = r600_texture_get_offset(rtex, level, box->z);
887 return &trans->transfer;
888 }
889
890 void r600_texture_transfer_destroy(struct pipe_context *ctx,
891 struct pipe_transfer *transfer)
892 {
893 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
894 struct pipe_resource *texture = transfer->resource;
895 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
896
897 if (rtransfer->staging) {
898 if (transfer->usage & PIPE_TRANSFER_WRITE) {
899 r600_copy_from_staging_texture(ctx, rtransfer);
900 }
901 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
902 }
903
904 if (rtex->is_depth && !rtex->is_flushing_texture) {
905 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture) {
906 struct pipe_box sbox;
907
908 u_box_origin_2d(texture->width0, texture->height0, &sbox);
909
910 ctx->resource_copy_region(ctx, texture, 0, 0, 0, 0,
911 &rtex->flushed_depth_texture->resource.b.b, 0,
912 &sbox);
913 }
914 }
915
916 pipe_resource_reference(&transfer->resource, NULL);
917 FREE(transfer);
918 }
919
920 void* r600_texture_transfer_map(struct pipe_context *ctx,
921 struct pipe_transfer* transfer)
922 {
923 struct r600_context *rctx = (struct r600_context *)ctx;
924 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
925 struct radeon_winsys_cs_handle *buf;
926 enum pipe_format format = transfer->resource->format;
927 unsigned offset = 0;
928 char *map;
929
930 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
931 return r600_compute_global_transfer_map(ctx, transfer);
932 }
933
934 if (rtransfer->staging) {
935 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
936 } else {
937 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
938
939 if (rtex->flushed_depth_texture)
940 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->cs_buf;
941 else
942 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
943
944 offset = rtransfer->offset +
945 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
946 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
947 }
948
949 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
950 return NULL;
951 }
952
953 return map + offset;
954 }
955
956 void r600_texture_transfer_unmap(struct pipe_context *ctx,
957 struct pipe_transfer* transfer)
958 {
959 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
960 struct r600_context *rctx = (struct r600_context*)ctx;
961 struct radeon_winsys_cs_handle *buf;
962
963 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
964 return r600_compute_global_transfer_unmap(ctx, transfer);
965 }
966
967 if (rtransfer->staging) {
968 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
969 } else {
970 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
971
972 if (rtex->flushed_depth_texture) {
973 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->cs_buf;
974 } else {
975 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
976 }
977 }
978 rctx->ws->buffer_unmap(buf);
979 }
980
981 void r600_init_surface_functions(struct r600_context *r600)
982 {
983 r600->context.create_surface = r600_create_surface;
984 r600->context.surface_destroy = r600_surface_destroy;
985 }
986
987 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
988 const unsigned char *swizzle_view)
989 {
990 unsigned i;
991 unsigned char swizzle[4];
992 unsigned result = 0;
993 const uint32_t swizzle_shift[4] = {
994 16, 19, 22, 25,
995 };
996 const uint32_t swizzle_bit[4] = {
997 0, 1, 2, 3,
998 };
999
1000 if (swizzle_view) {
1001 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1002 } else {
1003 memcpy(swizzle, swizzle_format, 4);
1004 }
1005
1006 /* Get swizzle. */
1007 for (i = 0; i < 4; i++) {
1008 switch (swizzle[i]) {
1009 case UTIL_FORMAT_SWIZZLE_Y:
1010 result |= swizzle_bit[1] << swizzle_shift[i];
1011 break;
1012 case UTIL_FORMAT_SWIZZLE_Z:
1013 result |= swizzle_bit[2] << swizzle_shift[i];
1014 break;
1015 case UTIL_FORMAT_SWIZZLE_W:
1016 result |= swizzle_bit[3] << swizzle_shift[i];
1017 break;
1018 case UTIL_FORMAT_SWIZZLE_0:
1019 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1020 break;
1021 case UTIL_FORMAT_SWIZZLE_1:
1022 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1023 break;
1024 default: /* UTIL_FORMAT_SWIZZLE_X */
1025 result |= swizzle_bit[0] << swizzle_shift[i];
1026 }
1027 }
1028 return result;
1029 }
1030
1031 /* texture format translate */
1032 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1033 enum pipe_format format,
1034 const unsigned char *swizzle_view,
1035 uint32_t *word4_p, uint32_t *yuv_format_p)
1036 {
1037 uint32_t result = 0, word4 = 0, yuv_format = 0;
1038 const struct util_format_description *desc;
1039 boolean uniform = TRUE;
1040 static int r600_enable_s3tc = -1;
1041 bool is_srgb_valid = FALSE;
1042
1043 int i;
1044 const uint32_t sign_bit[4] = {
1045 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1046 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1047 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1048 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1049 };
1050 desc = util_format_description(format);
1051
1052 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
1053
1054 /* Colorspace (return non-RGB formats directly). */
1055 switch (desc->colorspace) {
1056 /* Depth stencil formats */
1057 case UTIL_FORMAT_COLORSPACE_ZS:
1058 switch (format) {
1059 case PIPE_FORMAT_Z16_UNORM:
1060 result = FMT_16;
1061 goto out_word4;
1062 case PIPE_FORMAT_X24S8_UINT:
1063 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1064 case PIPE_FORMAT_Z24X8_UNORM:
1065 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1066 result = FMT_8_24;
1067 goto out_word4;
1068 case PIPE_FORMAT_S8X24_UINT:
1069 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1070 case PIPE_FORMAT_X8Z24_UNORM:
1071 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1072 result = FMT_24_8;
1073 goto out_word4;
1074 case PIPE_FORMAT_S8_UINT:
1075 result = FMT_8;
1076 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1077 goto out_word4;
1078 case PIPE_FORMAT_Z32_FLOAT:
1079 result = FMT_32_FLOAT;
1080 goto out_word4;
1081 case PIPE_FORMAT_X32_S8X24_UINT:
1082 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1083 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1084 result = FMT_X24_8_32_FLOAT;
1085 goto out_word4;
1086 default:
1087 goto out_unknown;
1088 }
1089
1090 case UTIL_FORMAT_COLORSPACE_YUV:
1091 yuv_format |= (1 << 30);
1092 switch (format) {
1093 case PIPE_FORMAT_UYVY:
1094 case PIPE_FORMAT_YUYV:
1095 default:
1096 break;
1097 }
1098 goto out_unknown; /* XXX */
1099
1100 case UTIL_FORMAT_COLORSPACE_SRGB:
1101 word4 |= S_038010_FORCE_DEGAMMA(1);
1102 break;
1103
1104 default:
1105 break;
1106 }
1107
1108 if (r600_enable_s3tc == -1) {
1109 struct r600_screen *rscreen = (struct r600_screen *)screen;
1110 if (rscreen->info.drm_minor >= 9)
1111 r600_enable_s3tc = 1;
1112 else
1113 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
1114 }
1115
1116 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1117 if (!r600_enable_s3tc)
1118 goto out_unknown;
1119
1120 switch (format) {
1121 case PIPE_FORMAT_RGTC1_SNORM:
1122 case PIPE_FORMAT_LATC1_SNORM:
1123 word4 |= sign_bit[0];
1124 case PIPE_FORMAT_RGTC1_UNORM:
1125 case PIPE_FORMAT_LATC1_UNORM:
1126 result = FMT_BC4;
1127 goto out_word4;
1128 case PIPE_FORMAT_RGTC2_SNORM:
1129 case PIPE_FORMAT_LATC2_SNORM:
1130 word4 |= sign_bit[0] | sign_bit[1];
1131 case PIPE_FORMAT_RGTC2_UNORM:
1132 case PIPE_FORMAT_LATC2_UNORM:
1133 result = FMT_BC5;
1134 goto out_word4;
1135 default:
1136 goto out_unknown;
1137 }
1138 }
1139
1140 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1141
1142 if (!r600_enable_s3tc)
1143 goto out_unknown;
1144
1145 if (!util_format_s3tc_enabled) {
1146 goto out_unknown;
1147 }
1148
1149 switch (format) {
1150 case PIPE_FORMAT_DXT1_RGB:
1151 case PIPE_FORMAT_DXT1_RGBA:
1152 case PIPE_FORMAT_DXT1_SRGB:
1153 case PIPE_FORMAT_DXT1_SRGBA:
1154 result = FMT_BC1;
1155 is_srgb_valid = TRUE;
1156 goto out_word4;
1157 case PIPE_FORMAT_DXT3_RGBA:
1158 case PIPE_FORMAT_DXT3_SRGBA:
1159 result = FMT_BC2;
1160 is_srgb_valid = TRUE;
1161 goto out_word4;
1162 case PIPE_FORMAT_DXT5_RGBA:
1163 case PIPE_FORMAT_DXT5_SRGBA:
1164 result = FMT_BC3;
1165 is_srgb_valid = TRUE;
1166 goto out_word4;
1167 default:
1168 goto out_unknown;
1169 }
1170 }
1171
1172 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1173 switch (format) {
1174 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1175 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1176 result = FMT_GB_GR;
1177 goto out_word4;
1178 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1179 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1180 result = FMT_BG_RG;
1181 goto out_word4;
1182 default:
1183 goto out_unknown;
1184 }
1185 }
1186
1187 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1188 result = FMT_5_9_9_9_SHAREDEXP;
1189 goto out_word4;
1190 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1191 result = FMT_10_11_11_FLOAT;
1192 goto out_word4;
1193 }
1194
1195
1196 for (i = 0; i < desc->nr_channels; i++) {
1197 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1198 word4 |= sign_bit[i];
1199 }
1200 }
1201
1202 /* R8G8Bx_SNORM - XXX CxV8U8 */
1203
1204 /* See whether the components are of the same size. */
1205 for (i = 1; i < desc->nr_channels; i++) {
1206 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1207 }
1208
1209 /* Non-uniform formats. */
1210 if (!uniform) {
1211 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1212 desc->channel[0].pure_integer)
1213 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1214 switch(desc->nr_channels) {
1215 case 3:
1216 if (desc->channel[0].size == 5 &&
1217 desc->channel[1].size == 6 &&
1218 desc->channel[2].size == 5) {
1219 result = FMT_5_6_5;
1220 goto out_word4;
1221 }
1222 goto out_unknown;
1223 case 4:
1224 if (desc->channel[0].size == 5 &&
1225 desc->channel[1].size == 5 &&
1226 desc->channel[2].size == 5 &&
1227 desc->channel[3].size == 1) {
1228 result = FMT_1_5_5_5;
1229 goto out_word4;
1230 }
1231 if (desc->channel[0].size == 10 &&
1232 desc->channel[1].size == 10 &&
1233 desc->channel[2].size == 10 &&
1234 desc->channel[3].size == 2) {
1235 result = FMT_2_10_10_10;
1236 goto out_word4;
1237 }
1238 goto out_unknown;
1239 }
1240 goto out_unknown;
1241 }
1242
1243 /* Find the first non-VOID channel. */
1244 for (i = 0; i < 4; i++) {
1245 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1246 break;
1247 }
1248 }
1249
1250 if (i == 4)
1251 goto out_unknown;
1252
1253 /* uniform formats */
1254 switch (desc->channel[i].type) {
1255 case UTIL_FORMAT_TYPE_UNSIGNED:
1256 case UTIL_FORMAT_TYPE_SIGNED:
1257 #if 0
1258 if (!desc->channel[i].normalized &&
1259 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1260 goto out_unknown;
1261 }
1262 #endif
1263 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1264 desc->channel[i].pure_integer)
1265 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1266
1267 switch (desc->channel[i].size) {
1268 case 4:
1269 switch (desc->nr_channels) {
1270 case 2:
1271 result = FMT_4_4;
1272 goto out_word4;
1273 case 4:
1274 result = FMT_4_4_4_4;
1275 goto out_word4;
1276 }
1277 goto out_unknown;
1278 case 8:
1279 switch (desc->nr_channels) {
1280 case 1:
1281 result = FMT_8;
1282 goto out_word4;
1283 case 2:
1284 result = FMT_8_8;
1285 goto out_word4;
1286 case 4:
1287 result = FMT_8_8_8_8;
1288 is_srgb_valid = TRUE;
1289 goto out_word4;
1290 }
1291 goto out_unknown;
1292 case 16:
1293 switch (desc->nr_channels) {
1294 case 1:
1295 result = FMT_16;
1296 goto out_word4;
1297 case 2:
1298 result = FMT_16_16;
1299 goto out_word4;
1300 case 4:
1301 result = FMT_16_16_16_16;
1302 goto out_word4;
1303 }
1304 goto out_unknown;
1305 case 32:
1306 switch (desc->nr_channels) {
1307 case 1:
1308 result = FMT_32;
1309 goto out_word4;
1310 case 2:
1311 result = FMT_32_32;
1312 goto out_word4;
1313 case 4:
1314 result = FMT_32_32_32_32;
1315 goto out_word4;
1316 }
1317 }
1318 goto out_unknown;
1319
1320 case UTIL_FORMAT_TYPE_FLOAT:
1321 switch (desc->channel[i].size) {
1322 case 16:
1323 switch (desc->nr_channels) {
1324 case 1:
1325 result = FMT_16_FLOAT;
1326 goto out_word4;
1327 case 2:
1328 result = FMT_16_16_FLOAT;
1329 goto out_word4;
1330 case 4:
1331 result = FMT_16_16_16_16_FLOAT;
1332 goto out_word4;
1333 }
1334 goto out_unknown;
1335 case 32:
1336 switch (desc->nr_channels) {
1337 case 1:
1338 result = FMT_32_FLOAT;
1339 goto out_word4;
1340 case 2:
1341 result = FMT_32_32_FLOAT;
1342 goto out_word4;
1343 case 4:
1344 result = FMT_32_32_32_32_FLOAT;
1345 goto out_word4;
1346 }
1347 }
1348 goto out_unknown;
1349 }
1350
1351 out_word4:
1352
1353 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1354 return ~0;
1355 if (word4_p)
1356 *word4_p = word4;
1357 if (yuv_format_p)
1358 *yuv_format_p = yuv_format;
1359 return result;
1360 out_unknown:
1361 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1362 return ~0;
1363 }