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gallium: switch boolean -> bool at the interface definitions
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_pack_color.h"
34 #include "util/u_surface.h"
35 #include "util/os_time.h"
36 #include <errno.h>
37 #include <inttypes.h>
38
39 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
40 struct r600_texture *rtex);
41 static enum radeon_surf_mode
42 r600_choose_tiling(struct r600_common_screen *rscreen,
43 const struct pipe_resource *templ);
44
45
46 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
47 struct r600_texture *rdst,
48 unsigned dst_level, unsigned dstx,
49 unsigned dsty, unsigned dstz,
50 struct r600_texture *rsrc,
51 unsigned src_level,
52 const struct pipe_box *src_box)
53 {
54 if (!rctx->dma.cs)
55 return false;
56
57 if (rdst->surface.bpe != rsrc->surface.bpe)
58 return false;
59
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc->resource.b.b.nr_samples > 1 ||
62 rdst->resource.b.b.nr_samples > 1)
63 return false;
64
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
68 */
69 if (rsrc->is_depth || rdst->is_depth)
70 return false;
71
72 /* CMASK as:
73 * src: Both texture and SDMA paths need decompression. Use SDMA.
74 * dst: If overwriting the whole texture, discard CMASK and use
75 * SDMA. Otherwise, use the 3D path.
76 */
77 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
78 /* The CMASK clear is only enabled for the first level. */
79 assert(dst_level == 0);
80 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
81 dstx, dsty, dstz, src_box->width,
82 src_box->height, src_box->depth))
83 return false;
84
85 r600_texture_discard_cmask(rctx->screen, rdst);
86 }
87
88 /* All requirements are met. Prepare textures for SDMA. */
89 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
90 rctx->b.flush_resource(&rctx->b, &rsrc->resource.b.b);
91
92 assert(!(rsrc->dirty_level_mask & (1 << src_level)));
93 assert(!(rdst->dirty_level_mask & (1 << dst_level)));
94
95 return true;
96 }
97
98 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
99 static void r600_copy_region_with_blit(struct pipe_context *pipe,
100 struct pipe_resource *dst,
101 unsigned dst_level,
102 unsigned dstx, unsigned dsty, unsigned dstz,
103 struct pipe_resource *src,
104 unsigned src_level,
105 const struct pipe_box *src_box)
106 {
107 struct pipe_blit_info blit;
108
109 memset(&blit, 0, sizeof(blit));
110 blit.src.resource = src;
111 blit.src.format = src->format;
112 blit.src.level = src_level;
113 blit.src.box = *src_box;
114 blit.dst.resource = dst;
115 blit.dst.format = dst->format;
116 blit.dst.level = dst_level;
117 blit.dst.box.x = dstx;
118 blit.dst.box.y = dsty;
119 blit.dst.box.z = dstz;
120 blit.dst.box.width = src_box->width;
121 blit.dst.box.height = src_box->height;
122 blit.dst.box.depth = src_box->depth;
123 blit.mask = util_format_get_mask(src->format) &
124 util_format_get_mask(dst->format);
125 blit.filter = PIPE_TEX_FILTER_NEAREST;
126
127 if (blit.mask) {
128 pipe->blit(pipe, &blit);
129 }
130 }
131
132 /* Copy from a full GPU texture to a transfer's staging one. */
133 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
134 {
135 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
136 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
137 struct pipe_resource *dst = &rtransfer->staging->b.b;
138 struct pipe_resource *src = transfer->resource;
139
140 if (src->nr_samples > 1) {
141 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
142 src, transfer->level, &transfer->box);
143 return;
144 }
145
146 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
147 &transfer->box);
148 }
149
150 /* Copy from a transfer's staging texture to a full GPU one. */
151 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
152 {
153 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
154 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
155 struct pipe_resource *dst = transfer->resource;
156 struct pipe_resource *src = &rtransfer->staging->b.b;
157 struct pipe_box sbox;
158
159 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
160
161 if (dst->nr_samples > 1) {
162 r600_copy_region_with_blit(ctx, dst, transfer->level,
163 transfer->box.x, transfer->box.y, transfer->box.z,
164 src, 0, &sbox);
165 return;
166 }
167
168 rctx->dma_copy(ctx, dst, transfer->level,
169 transfer->box.x, transfer->box.y, transfer->box.z,
170 src, 0, &sbox);
171 }
172
173 static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
174 struct r600_texture *rtex, unsigned level,
175 const struct pipe_box *box,
176 unsigned *stride,
177 unsigned *layer_stride)
178 {
179 *stride = rtex->surface.u.legacy.level[level].nblk_x *
180 rtex->surface.bpe;
181 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
182 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
183
184 if (!box)
185 return rtex->surface.u.legacy.level[level].offset;
186
187 /* Each texture is an array of mipmap levels. Each level is
188 * an array of slices. */
189 return rtex->surface.u.legacy.level[level].offset +
190 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
191 (box->y / rtex->surface.blk_h *
192 rtex->surface.u.legacy.level[level].nblk_x +
193 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
194 }
195
196 static int r600_init_surface(struct r600_common_screen *rscreen,
197 struct radeon_surf *surface,
198 const struct pipe_resource *ptex,
199 enum radeon_surf_mode array_mode,
200 unsigned pitch_in_bytes_override,
201 unsigned offset,
202 bool is_imported,
203 bool is_scanout,
204 bool is_flushed_depth)
205 {
206 const struct util_format_description *desc =
207 util_format_description(ptex->format);
208 bool is_depth, is_stencil;
209 int r;
210 unsigned i, bpe, flags = 0;
211
212 is_depth = util_format_has_depth(desc);
213 is_stencil = util_format_has_stencil(desc);
214
215 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
216 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
217 bpe = 4; /* stencil is allocated separately on evergreen */
218 } else {
219 bpe = util_format_get_blocksize(ptex->format);
220 assert(util_is_power_of_two_or_zero(bpe));
221 }
222
223 if (!is_flushed_depth && is_depth) {
224 flags |= RADEON_SURF_ZBUFFER;
225
226 if (is_stencil)
227 flags |= RADEON_SURF_SBUFFER;
228 }
229
230 if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
231 /* This should catch bugs in gallium users setting incorrect flags. */
232 assert(ptex->nr_samples <= 1 &&
233 ptex->array_size == 1 &&
234 ptex->depth0 == 1 &&
235 ptex->last_level == 0 &&
236 !(flags & RADEON_SURF_Z_OR_SBUFFER));
237
238 flags |= RADEON_SURF_SCANOUT;
239 }
240
241 if (ptex->bind & PIPE_BIND_SHARED)
242 flags |= RADEON_SURF_SHAREABLE;
243 if (is_imported)
244 flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
245 if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
246 flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
247
248 r = rscreen->ws->surface_init(rscreen->ws, ptex,
249 flags, bpe, array_mode, surface);
250 if (r) {
251 return r;
252 }
253
254 if (pitch_in_bytes_override &&
255 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
256 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
257 * for those
258 */
259 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe;
260 surface->u.legacy.level[0].slice_size_dw =
261 ((uint64_t)pitch_in_bytes_override * surface->u.legacy.level[0].nblk_y) / 4;
262 }
263
264 if (offset) {
265 for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
266 surface->u.legacy.level[i].offset += offset;
267 }
268
269 return 0;
270 }
271
272 static void r600_texture_init_metadata(struct r600_common_screen *rscreen,
273 struct r600_texture *rtex,
274 struct radeon_bo_metadata *metadata)
275 {
276 struct radeon_surf *surface = &rtex->surface;
277
278 memset(metadata, 0, sizeof(*metadata));
279
280 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
281 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
282 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
283 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
284 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
285 metadata->u.legacy.bankw = surface->u.legacy.bankw;
286 metadata->u.legacy.bankh = surface->u.legacy.bankh;
287 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
288 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
289 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
290 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
291 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
292 }
293
294 static void r600_surface_import_metadata(struct r600_common_screen *rscreen,
295 struct radeon_surf *surf,
296 struct radeon_bo_metadata *metadata,
297 enum radeon_surf_mode *array_mode,
298 bool *is_scanout)
299 {
300 surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config;
301 surf->u.legacy.bankw = metadata->u.legacy.bankw;
302 surf->u.legacy.bankh = metadata->u.legacy.bankh;
303 surf->u.legacy.tile_split = metadata->u.legacy.tile_split;
304 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
305 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
306
307 if (metadata->u.legacy.macrotile == RADEON_LAYOUT_TILED)
308 *array_mode = RADEON_SURF_MODE_2D;
309 else if (metadata->u.legacy.microtile == RADEON_LAYOUT_TILED)
310 *array_mode = RADEON_SURF_MODE_1D;
311 else
312 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
313
314 *is_scanout = metadata->u.legacy.scanout;
315 }
316
317 static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
318 struct r600_texture *rtex)
319 {
320 struct r600_common_screen *rscreen = rctx->screen;
321 struct pipe_context *ctx = &rctx->b;
322
323 if (ctx == rscreen->aux_context)
324 mtx_lock(&rscreen->aux_context_lock);
325
326 ctx->flush_resource(ctx, &rtex->resource.b.b);
327 ctx->flush(ctx, NULL, 0);
328
329 if (ctx == rscreen->aux_context)
330 mtx_unlock(&rscreen->aux_context_lock);
331 }
332
333 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
334 struct r600_texture *rtex)
335 {
336 if (!rtex->cmask.size)
337 return;
338
339 assert(rtex->resource.b.b.nr_samples <= 1);
340
341 /* Disable CMASK. */
342 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
343 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
344 rtex->dirty_level_mask = 0;
345
346 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
347
348 if (rtex->cmask_buffer != &rtex->resource)
349 r600_resource_reference(&rtex->cmask_buffer, NULL);
350
351 /* Notify all contexts about the change. */
352 p_atomic_inc(&rscreen->dirty_tex_counter);
353 p_atomic_inc(&rscreen->compressed_colortex_counter);
354 }
355
356 static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
357 struct r600_texture *rtex,
358 unsigned new_bind_flag,
359 bool invalidate_storage)
360 {
361 struct pipe_screen *screen = rctx->b.screen;
362 struct r600_texture *new_tex;
363 struct pipe_resource templ = rtex->resource.b.b;
364 unsigned i;
365
366 templ.bind |= new_bind_flag;
367
368 /* r600g doesn't react to dirty_tex_descriptor_counter */
369 if (rctx->chip_class < GFX6)
370 return;
371
372 if (rtex->resource.b.is_shared)
373 return;
374
375 if (new_bind_flag == PIPE_BIND_LINEAR) {
376 if (rtex->surface.is_linear)
377 return;
378
379 /* This fails with MSAA, depth, and compressed textures. */
380 if (r600_choose_tiling(rctx->screen, &templ) !=
381 RADEON_SURF_MODE_LINEAR_ALIGNED)
382 return;
383 }
384
385 new_tex = (struct r600_texture*)screen->resource_create(screen, &templ);
386 if (!new_tex)
387 return;
388
389 /* Copy the pixels to the new texture. */
390 if (!invalidate_storage) {
391 for (i = 0; i <= templ.last_level; i++) {
392 struct pipe_box box;
393
394 u_box_3d(0, 0, 0,
395 u_minify(templ.width0, i), u_minify(templ.height0, i),
396 util_num_layers(&templ, i), &box);
397
398 rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
399 &rtex->resource.b.b, i, &box);
400 }
401 }
402
403 if (new_bind_flag == PIPE_BIND_LINEAR) {
404 r600_texture_discard_cmask(rctx->screen, rtex);
405 }
406
407 /* Replace the structure fields of rtex. */
408 rtex->resource.b.b.bind = templ.bind;
409 pb_reference(&rtex->resource.buf, new_tex->resource.buf);
410 rtex->resource.gpu_address = new_tex->resource.gpu_address;
411 rtex->resource.vram_usage = new_tex->resource.vram_usage;
412 rtex->resource.gart_usage = new_tex->resource.gart_usage;
413 rtex->resource.bo_size = new_tex->resource.bo_size;
414 rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
415 rtex->resource.domains = new_tex->resource.domains;
416 rtex->resource.flags = new_tex->resource.flags;
417 rtex->size = new_tex->size;
418 rtex->db_render_format = new_tex->db_render_format;
419 rtex->db_compatible = new_tex->db_compatible;
420 rtex->can_sample_z = new_tex->can_sample_z;
421 rtex->can_sample_s = new_tex->can_sample_s;
422 rtex->surface = new_tex->surface;
423 rtex->fmask = new_tex->fmask;
424 rtex->cmask = new_tex->cmask;
425 rtex->cb_color_info = new_tex->cb_color_info;
426 rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
427 rtex->htile_offset = new_tex->htile_offset;
428 rtex->depth_cleared = new_tex->depth_cleared;
429 rtex->stencil_cleared = new_tex->stencil_cleared;
430 rtex->non_disp_tiling = new_tex->non_disp_tiling;
431 rtex->framebuffers_bound = new_tex->framebuffers_bound;
432
433 if (new_bind_flag == PIPE_BIND_LINEAR) {
434 assert(!rtex->htile_offset);
435 assert(!rtex->cmask.size);
436 assert(!rtex->fmask.size);
437 assert(!rtex->is_depth);
438 }
439
440 r600_texture_reference(&new_tex, NULL);
441
442 p_atomic_inc(&rctx->screen->dirty_tex_counter);
443 }
444
445 static void r600_texture_get_info(struct pipe_screen* screen,
446 struct pipe_resource *resource,
447 unsigned *pstride,
448 unsigned *poffset)
449 {
450 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
451 struct r600_texture *rtex = (struct r600_texture*)resource;
452 unsigned stride = 0;
453 unsigned offset = 0;
454
455 if (!rscreen || !rtex)
456 return;
457
458 if (resource->target != PIPE_BUFFER) {
459 offset = rtex->surface.u.legacy.level[0].offset;
460 stride = rtex->surface.u.legacy.level[0].nblk_x *
461 rtex->surface.bpe;
462 }
463
464 if (pstride)
465 *pstride = stride;
466
467 if (poffset)
468 *poffset = offset;
469 }
470
471 static bool r600_texture_get_handle(struct pipe_screen* screen,
472 struct pipe_context *ctx,
473 struct pipe_resource *resource,
474 struct winsys_handle *whandle,
475 unsigned usage)
476 {
477 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
478 struct r600_common_context *rctx;
479 struct r600_resource *res = (struct r600_resource*)resource;
480 struct r600_texture *rtex = (struct r600_texture*)resource;
481 struct radeon_bo_metadata metadata;
482 bool update_metadata = false;
483 unsigned stride, offset, slice_size;
484
485 ctx = threaded_context_unwrap_sync(ctx);
486 rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
487
488 if (resource->target != PIPE_BUFFER) {
489 /* This is not supported now, but it might be required for OpenCL
490 * interop in the future.
491 */
492 if (resource->nr_samples > 1 || rtex->is_depth)
493 return false;
494
495 /* Move a suballocated texture into a non-suballocated allocation. */
496 if (rscreen->ws->buffer_is_suballocated(res->buf) ||
497 rtex->surface.tile_swizzle) {
498 assert(!res->b.is_shared);
499 r600_reallocate_texture_inplace(rctx, rtex,
500 PIPE_BIND_SHARED, false);
501 rctx->b.flush(&rctx->b, NULL, 0);
502 assert(res->b.b.bind & PIPE_BIND_SHARED);
503 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
504 assert(rtex->surface.tile_swizzle == 0);
505 }
506
507 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
508 rtex->cmask.size) {
509 /* Eliminate fast clear (CMASK) */
510 r600_eliminate_fast_color_clear(rctx, rtex);
511
512 /* Disable CMASK if flush_resource isn't going
513 * to be called.
514 */
515 if (rtex->cmask.size)
516 r600_texture_discard_cmask(rscreen, rtex);
517 }
518
519 /* Set metadata. */
520 if (!res->b.is_shared || update_metadata) {
521 r600_texture_init_metadata(rscreen, rtex, &metadata);
522
523 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
524 }
525
526 slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4;
527 } else {
528 /* Move a suballocated buffer into a non-suballocated allocation. */
529 if (rscreen->ws->buffer_is_suballocated(res->buf)) {
530 assert(!res->b.is_shared);
531
532 /* Allocate a new buffer with PIPE_BIND_SHARED. */
533 struct pipe_resource templ = res->b.b;
534 templ.bind |= PIPE_BIND_SHARED;
535
536 struct pipe_resource *newb =
537 screen->resource_create(screen, &templ);
538 if (!newb)
539 return false;
540
541 /* Copy the old buffer contents to the new one. */
542 struct pipe_box box;
543 u_box_1d(0, newb->width0, &box);
544 rctx->b.resource_copy_region(&rctx->b, newb, 0, 0, 0, 0,
545 &res->b.b, 0, &box);
546 /* Move the new buffer storage to the old pipe_resource. */
547 r600_replace_buffer_storage(&rctx->b, &res->b.b, newb);
548 pipe_resource_reference(&newb, NULL);
549
550 assert(res->b.b.bind & PIPE_BIND_SHARED);
551 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
552 }
553
554 /* Buffers */
555 slice_size = 0;
556 }
557
558 r600_texture_get_info(screen, resource, &stride, &offset);
559
560 if (res->b.is_shared) {
561 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
562 * doesn't set it.
563 */
564 res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
565 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
566 res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
567 } else {
568 res->b.is_shared = true;
569 res->external_usage = usage;
570 }
571
572 return rscreen->ws->buffer_get_handle(rscreen->ws, res->buf, stride,
573 offset, slice_size, whandle);
574 }
575
576 static void r600_texture_destroy(struct pipe_screen *screen,
577 struct pipe_resource *ptex)
578 {
579 struct r600_texture *rtex = (struct r600_texture*)ptex;
580 struct r600_resource *resource = &rtex->resource;
581
582 r600_texture_reference(&rtex->flushed_depth_texture, NULL);
583 pipe_resource_reference((struct pipe_resource**)&resource->immed_buffer, NULL);
584
585 if (rtex->cmask_buffer != &rtex->resource) {
586 r600_resource_reference(&rtex->cmask_buffer, NULL);
587 }
588 pb_reference(&resource->buf, NULL);
589 FREE(rtex);
590 }
591
592 static const struct u_resource_vtbl r600_texture_vtbl;
593
594 /* The number of samples can be specified independently of the texture. */
595 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
596 struct r600_texture *rtex,
597 unsigned nr_samples,
598 struct r600_fmask_info *out)
599 {
600 /* FMASK is allocated like an ordinary texture. */
601 struct pipe_resource templ = rtex->resource.b.b;
602 struct radeon_surf fmask = {};
603 unsigned flags, bpe;
604
605 memset(out, 0, sizeof(*out));
606
607 templ.nr_samples = 1;
608 flags = rtex->surface.flags | RADEON_SURF_FMASK;
609
610 /* Use the same parameters and tile mode. */
611 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
612 fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh;
613 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
614 fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split;
615
616 if (nr_samples <= 4)
617 fmask.u.legacy.bankh = 4;
618
619 switch (nr_samples) {
620 case 2:
621 case 4:
622 bpe = 1;
623 break;
624 case 8:
625 bpe = 4;
626 break;
627 default:
628 R600_ERR("Invalid sample count for FMASK allocation.\n");
629 return;
630 }
631
632 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
633 * This can be fixed by writing a separate FMASK allocator specifically
634 * for R600-R700 asics. */
635 if (rscreen->chip_class <= R700) {
636 bpe *= 2;
637 }
638
639 if (rscreen->ws->surface_init(rscreen->ws, &templ,
640 flags, bpe, RADEON_SURF_MODE_2D, &fmask)) {
641 R600_ERR("Got error in surface_init while allocating FMASK.\n");
642 return;
643 }
644
645 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
646
647 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
648 if (out->slice_tile_max)
649 out->slice_tile_max -= 1;
650
651 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
652 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
653 out->bank_height = fmask.u.legacy.bankh;
654 out->tile_swizzle = fmask.tile_swizzle;
655 out->alignment = MAX2(256, fmask.surf_alignment);
656 out->size = fmask.surf_size;
657 }
658
659 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
660 struct r600_texture *rtex)
661 {
662 r600_texture_get_fmask_info(rscreen, rtex,
663 rtex->resource.b.b.nr_samples, &rtex->fmask);
664
665 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
666 rtex->size = rtex->fmask.offset + rtex->fmask.size;
667 }
668
669 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
670 struct r600_texture *rtex,
671 struct r600_cmask_info *out)
672 {
673 unsigned cmask_tile_width = 8;
674 unsigned cmask_tile_height = 8;
675 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
676 unsigned element_bits = 4;
677 unsigned cmask_cache_bits = 1024;
678 unsigned num_pipes = rscreen->info.num_tile_pipes;
679 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
680
681 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
682 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
683 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
684 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
685 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
686
687 unsigned pitch_elements = align(rtex->resource.b.b.width0, macro_tile_width);
688 unsigned height = align(rtex->resource.b.b.height0, macro_tile_height);
689
690 unsigned base_align = num_pipes * pipe_interleave_bytes;
691 unsigned slice_bytes =
692 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
693
694 assert(macro_tile_width % 128 == 0);
695 assert(macro_tile_height % 128 == 0);
696
697 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
698 out->alignment = MAX2(256, base_align);
699 out->size = util_num_layers(&rtex->resource.b.b, 0) *
700 align(slice_bytes, base_align);
701 }
702
703 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
704 struct r600_texture *rtex)
705 {
706 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
707
708 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
709 rtex->size = rtex->cmask.offset + rtex->cmask.size;
710
711 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
712 }
713
714 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
715 struct r600_texture *rtex)
716 {
717 if (rtex->cmask_buffer)
718 return;
719
720 assert(rtex->cmask.size == 0);
721
722 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
723
724 rtex->cmask_buffer = (struct r600_resource *)
725 r600_aligned_buffer_create(&rscreen->b,
726 R600_RESOURCE_FLAG_UNMAPPABLE,
727 PIPE_USAGE_DEFAULT,
728 rtex->cmask.size,
729 rtex->cmask.alignment);
730 if (rtex->cmask_buffer == NULL) {
731 rtex->cmask.size = 0;
732 return;
733 }
734
735 /* update colorbuffer state bits */
736 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
737
738 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
739
740 p_atomic_inc(&rscreen->compressed_colortex_counter);
741 }
742
743 void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
744 struct r600_resource *res,
745 unsigned immed_size)
746 {
747 res->immed_buffer = (struct r600_resource *)
748 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
749 PIPE_USAGE_DEFAULT, immed_size);
750 }
751
752 static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
753 struct r600_texture *rtex)
754 {
755 unsigned cl_width, cl_height, width, height;
756 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
757 unsigned num_pipes = rscreen->info.num_tile_pipes;
758
759 rtex->surface.htile_size = 0;
760
761 if (rscreen->chip_class <= EVERGREEN &&
762 rscreen->info.drm_minor < 26)
763 return;
764
765 /* HW bug on R6xx. */
766 if (rscreen->chip_class == R600 &&
767 (rtex->resource.b.b.width0 > 7680 ||
768 rtex->resource.b.b.height0 > 7680))
769 return;
770
771 switch (num_pipes) {
772 case 1:
773 cl_width = 32;
774 cl_height = 16;
775 break;
776 case 2:
777 cl_width = 32;
778 cl_height = 32;
779 break;
780 case 4:
781 cl_width = 64;
782 cl_height = 32;
783 break;
784 case 8:
785 cl_width = 64;
786 cl_height = 64;
787 break;
788 case 16:
789 cl_width = 128;
790 cl_height = 64;
791 break;
792 default:
793 assert(0);
794 return;
795 }
796
797 width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
798 height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8);
799
800 slice_elements = (width * height) / (8 * 8);
801 slice_bytes = slice_elements * 4;
802
803 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
804 base_align = num_pipes * pipe_interleave_bytes;
805
806 rtex->surface.htile_alignment = base_align;
807 rtex->surface.htile_size =
808 util_num_layers(&rtex->resource.b.b, 0) *
809 align(slice_bytes, base_align);
810 }
811
812 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
813 struct r600_texture *rtex)
814 {
815 r600_texture_get_htile_size(rscreen, rtex);
816
817 if (!rtex->surface.htile_size)
818 return;
819
820 rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment);
821 rtex->size = rtex->htile_offset + rtex->surface.htile_size;
822 }
823
824 void r600_print_texture_info(struct r600_common_screen *rscreen,
825 struct r600_texture *rtex, struct u_log_context *log)
826 {
827 int i;
828
829 /* Common parameters. */
830 u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
831 "blk_h=%u, array_size=%u, last_level=%u, "
832 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
833 rtex->resource.b.b.width0, rtex->resource.b.b.height0,
834 rtex->resource.b.b.depth0, rtex->surface.blk_w,
835 rtex->surface.blk_h,
836 rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
837 rtex->surface.bpe, rtex->resource.b.b.nr_samples,
838 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
839
840 u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
841 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
842 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw,
843 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
844 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
845 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
846
847 if (rtex->fmask.size)
848 u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
849 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
850 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
851 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
852 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
853
854 if (rtex->cmask.size)
855 u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
856 "slice_tile_max=%u\n",
857 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
858 rtex->cmask.slice_tile_max);
859
860 if (rtex->htile_offset)
861 u_log_printf(log, " HTile: offset=%"PRIu64", size=%u "
862 "alignment=%u\n",
863 rtex->htile_offset, rtex->surface.htile_size,
864 rtex->surface.htile_alignment);
865
866 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
867 u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
868 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
869 "mode=%u, tiling_index = %u\n",
870 i, rtex->surface.u.legacy.level[i].offset,
871 (uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4,
872 u_minify(rtex->resource.b.b.width0, i),
873 u_minify(rtex->resource.b.b.height0, i),
874 u_minify(rtex->resource.b.b.depth0, i),
875 rtex->surface.u.legacy.level[i].nblk_x,
876 rtex->surface.u.legacy.level[i].nblk_y,
877 rtex->surface.u.legacy.level[i].mode,
878 rtex->surface.u.legacy.tiling_index[i]);
879
880 if (rtex->surface.has_stencil) {
881 u_log_printf(log, " StencilLayout: tilesplit=%u\n",
882 rtex->surface.u.legacy.stencil_tile_split);
883 for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
884 u_log_printf(log, " StencilLevel[%i]: offset=%"PRIu64", "
885 "slice_size=%"PRIu64", npix_x=%u, "
886 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
887 "mode=%u, tiling_index = %u\n",
888 i, rtex->surface.u.legacy.stencil_level[i].offset,
889 (uint64_t)rtex->surface.u.legacy.stencil_level[i].slice_size_dw * 4,
890 u_minify(rtex->resource.b.b.width0, i),
891 u_minify(rtex->resource.b.b.height0, i),
892 u_minify(rtex->resource.b.b.depth0, i),
893 rtex->surface.u.legacy.stencil_level[i].nblk_x,
894 rtex->surface.u.legacy.stencil_level[i].nblk_y,
895 rtex->surface.u.legacy.stencil_level[i].mode,
896 rtex->surface.u.legacy.stencil_tiling_index[i]);
897 }
898 }
899 }
900
901 /* Common processing for r600_texture_create and r600_texture_from_handle */
902 static struct r600_texture *
903 r600_texture_create_object(struct pipe_screen *screen,
904 const struct pipe_resource *base,
905 struct pb_buffer *buf,
906 struct radeon_surf *surface)
907 {
908 struct r600_texture *rtex;
909 struct r600_resource *resource;
910 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
911
912 rtex = CALLOC_STRUCT(r600_texture);
913 if (!rtex)
914 return NULL;
915
916 resource = &rtex->resource;
917 resource->b.b = *base;
918 resource->b.b.next = NULL;
919 resource->b.vtbl = &r600_texture_vtbl;
920 pipe_reference_init(&resource->b.b.reference, 1);
921 resource->b.b.screen = screen;
922
923 /* don't include stencil-only formats which we don't support for rendering */
924 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
925
926 rtex->surface = *surface;
927 rtex->size = rtex->surface.surf_size;
928 rtex->db_render_format = base->format;
929
930 /* Tiled depth textures utilize the non-displayable tile order.
931 * This must be done after r600_setup_surface.
932 * Applies to R600-Cayman. */
933 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.u.legacy.level[0].mode >= RADEON_SURF_MODE_1D;
934 /* Applies to GCN. */
935 rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
936
937 if (rtex->is_depth) {
938 if (base->flags & (R600_RESOURCE_FLAG_TRANSFER |
939 R600_RESOURCE_FLAG_FLUSHED_DEPTH) ||
940 rscreen->chip_class >= EVERGREEN) {
941 rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
942 rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
943 } else {
944 if (rtex->resource.b.b.nr_samples <= 1 &&
945 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
946 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT))
947 rtex->can_sample_z = true;
948 }
949
950 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
951 R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
952 rtex->db_compatible = true;
953
954 if (!(rscreen->debug_flags & DBG_NO_HYPERZ))
955 r600_texture_allocate_htile(rscreen, rtex);
956 }
957 } else {
958 if (base->nr_samples > 1) {
959 if (!buf) {
960 r600_texture_allocate_fmask(rscreen, rtex);
961 r600_texture_allocate_cmask(rscreen, rtex);
962 rtex->cmask_buffer = &rtex->resource;
963 }
964 if (!rtex->fmask.size || !rtex->cmask.size) {
965 FREE(rtex);
966 return NULL;
967 }
968 }
969 }
970
971 /* Now create the backing buffer. */
972 if (!buf) {
973 r600_init_resource_fields(rscreen, resource, rtex->size,
974 rtex->surface.surf_alignment);
975
976 if (!r600_alloc_resource(rscreen, resource)) {
977 FREE(rtex);
978 return NULL;
979 }
980 } else {
981 resource->buf = buf;
982 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
983 resource->bo_size = buf->size;
984 resource->bo_alignment = buf->alignment;
985 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
986 if (resource->domains & RADEON_DOMAIN_VRAM)
987 resource->vram_usage = buf->size;
988 else if (resource->domains & RADEON_DOMAIN_GTT)
989 resource->gart_usage = buf->size;
990 }
991
992 if (rtex->cmask.size) {
993 /* Initialize the cmask to 0xCC (= compressed state). */
994 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
995 rtex->cmask.offset, rtex->cmask.size,
996 0xCCCCCCCC);
997 }
998 if (rtex->htile_offset) {
999 uint32_t clear_value = 0;
1000
1001 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
1002 rtex->htile_offset,
1003 rtex->surface.htile_size,
1004 clear_value);
1005 }
1006
1007 /* Initialize the CMASK base register value. */
1008 rtex->cmask.base_address_reg =
1009 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1010
1011 if (rscreen->debug_flags & DBG_VM) {
1012 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1013 rtex->resource.gpu_address,
1014 rtex->resource.gpu_address + rtex->resource.buf->size,
1015 base->width0, base->height0, util_num_layers(base, 0), base->last_level+1,
1016 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
1017 }
1018
1019 if (rscreen->debug_flags & DBG_TEX) {
1020 puts("Texture:");
1021 struct u_log_context log;
1022 u_log_context_init(&log);
1023 r600_print_texture_info(rscreen, rtex, &log);
1024 u_log_new_page_print(&log, stdout);
1025 fflush(stdout);
1026 u_log_context_destroy(&log);
1027 }
1028
1029 return rtex;
1030 }
1031
1032 static enum radeon_surf_mode
1033 r600_choose_tiling(struct r600_common_screen *rscreen,
1034 const struct pipe_resource *templ)
1035 {
1036 const struct util_format_description *desc = util_format_description(templ->format);
1037 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
1038 bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
1039 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
1040
1041 /* MSAA resources must be 2D tiled. */
1042 if (templ->nr_samples > 1)
1043 return RADEON_SURF_MODE_2D;
1044
1045 /* Transfer resources should be linear. */
1046 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
1047 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1048
1049 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1050 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
1051 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
1052 (templ->target == PIPE_TEXTURE_2D ||
1053 templ->target == PIPE_TEXTURE_3D))
1054 force_tiling = true;
1055
1056 /* Handle common candidates for the linear mode.
1057 * Compressed textures and DB surfaces must always be tiled.
1058 */
1059 if (!force_tiling &&
1060 !is_depth_stencil &&
1061 !util_format_is_compressed(templ->format)) {
1062 if (rscreen->debug_flags & DBG_NO_TILING)
1063 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1064
1065 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1066 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
1067 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1068
1069 if (templ->bind & PIPE_BIND_LINEAR)
1070 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1071
1072 /* 1D textures should be linear - fixes image operations on 1d */
1073 if (templ->target == PIPE_TEXTURE_1D ||
1074 templ->target == PIPE_TEXTURE_1D_ARRAY)
1075 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1076
1077 /* Textures likely to be mapped often. */
1078 if (templ->usage == PIPE_USAGE_STAGING ||
1079 templ->usage == PIPE_USAGE_STREAM)
1080 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1081 }
1082
1083 /* Make small textures 1D tiled. */
1084 if (templ->width0 <= 16 || templ->height0 <= 16 ||
1085 (rscreen->debug_flags & DBG_NO_2D_TILING))
1086 return RADEON_SURF_MODE_1D;
1087
1088 /* The allocator will switch to 1D if needed. */
1089 return RADEON_SURF_MODE_2D;
1090 }
1091
1092 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
1093 const struct pipe_resource *templ)
1094 {
1095 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1096 struct radeon_surf surface = {0};
1097 bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1098 int r;
1099
1100 r = r600_init_surface(rscreen, &surface, templ,
1101 r600_choose_tiling(rscreen, templ), 0, 0,
1102 false, false, is_flushed_depth);
1103 if (r) {
1104 return NULL;
1105 }
1106
1107 return (struct pipe_resource *)
1108 r600_texture_create_object(screen, templ, NULL, &surface);
1109 }
1110
1111 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1112 const struct pipe_resource *templ,
1113 struct winsys_handle *whandle,
1114 unsigned usage)
1115 {
1116 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1117 struct pb_buffer *buf = NULL;
1118 unsigned stride = 0, offset = 0;
1119 enum radeon_surf_mode array_mode;
1120 struct radeon_surf surface = {};
1121 int r;
1122 struct radeon_bo_metadata metadata = {};
1123 struct r600_texture *rtex;
1124 bool is_scanout;
1125
1126 /* Support only 2D textures without mipmaps */
1127 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1128 templ->depth0 != 1 || templ->last_level != 0)
1129 return NULL;
1130
1131 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1132 rscreen->info.max_alignment,
1133 &stride, &offset);
1134 if (!buf)
1135 return NULL;
1136
1137 rscreen->ws->buffer_get_metadata(buf, &metadata);
1138 r600_surface_import_metadata(rscreen, &surface, &metadata,
1139 &array_mode, &is_scanout);
1140
1141 r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
1142 offset, true, is_scanout, false);
1143 if (r) {
1144 return NULL;
1145 }
1146
1147 rtex = r600_texture_create_object(screen, templ, buf, &surface);
1148 if (!rtex)
1149 return NULL;
1150
1151 rtex->resource.b.is_shared = true;
1152 rtex->resource.external_usage = usage;
1153
1154 assert(rtex->surface.tile_swizzle == 0);
1155 return &rtex->resource.b.b;
1156 }
1157
1158 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1159 struct pipe_resource *texture,
1160 struct r600_texture **staging)
1161 {
1162 struct r600_texture *rtex = (struct r600_texture*)texture;
1163 struct pipe_resource resource;
1164 struct r600_texture **flushed_depth_texture = staging ?
1165 staging : &rtex->flushed_depth_texture;
1166 enum pipe_format pipe_format = texture->format;
1167
1168 if (!staging) {
1169 if (rtex->flushed_depth_texture)
1170 return true; /* it's ready */
1171
1172 if (!rtex->can_sample_z && rtex->can_sample_s) {
1173 switch (pipe_format) {
1174 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1175 /* Save memory by not allocating the S plane. */
1176 pipe_format = PIPE_FORMAT_Z32_FLOAT;
1177 break;
1178 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1179 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1180 /* Save memory bandwidth by not copying the
1181 * stencil part during flush.
1182 *
1183 * This potentially increases memory bandwidth
1184 * if an application uses both Z and S texturing
1185 * simultaneously (a flushed Z24S8 texture
1186 * would be stored compactly), but how often
1187 * does that really happen?
1188 */
1189 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
1190 break;
1191 default:;
1192 }
1193 } else if (!rtex->can_sample_s && rtex->can_sample_z) {
1194 assert(util_format_has_stencil(util_format_description(pipe_format)));
1195
1196 /* DB->CB copies to an 8bpp surface don't work. */
1197 pipe_format = PIPE_FORMAT_X24S8_UINT;
1198 }
1199 }
1200
1201 memset(&resource, 0, sizeof(resource));
1202 resource.target = texture->target;
1203 resource.format = pipe_format;
1204 resource.width0 = texture->width0;
1205 resource.height0 = texture->height0;
1206 resource.depth0 = texture->depth0;
1207 resource.array_size = texture->array_size;
1208 resource.last_level = texture->last_level;
1209 resource.nr_samples = texture->nr_samples;
1210 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1211 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1212 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1213
1214 if (staging)
1215 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1216
1217 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1218 if (*flushed_depth_texture == NULL) {
1219 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1220 return false;
1221 }
1222
1223 (*flushed_depth_texture)->non_disp_tiling = false;
1224 return true;
1225 }
1226
1227 /**
1228 * Initialize the pipe_resource descriptor to be of the same size as the box,
1229 * which is supposed to hold a subregion of the texture "orig" at the given
1230 * mipmap level.
1231 */
1232 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1233 struct pipe_resource *orig,
1234 const struct pipe_box *box,
1235 unsigned level, unsigned flags)
1236 {
1237 memset(res, 0, sizeof(*res));
1238 res->format = orig->format;
1239 res->width0 = box->width;
1240 res->height0 = box->height;
1241 res->depth0 = 1;
1242 res->array_size = 1;
1243 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1244 res->flags = flags;
1245
1246 /* We must set the correct texture target and dimensions for a 3D box. */
1247 if (box->depth > 1 && util_max_layer(orig, level) > 0) {
1248 res->target = PIPE_TEXTURE_2D_ARRAY;
1249 res->array_size = box->depth;
1250 } else {
1251 res->target = PIPE_TEXTURE_2D;
1252 }
1253 }
1254
1255 static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen,
1256 struct r600_texture *rtex,
1257 unsigned transfer_usage,
1258 const struct pipe_box *box)
1259 {
1260 /* r600g doesn't react to dirty_tex_descriptor_counter */
1261 return rscreen->chip_class >= GFX6 &&
1262 !rtex->resource.b.is_shared &&
1263 !(transfer_usage & PIPE_TRANSFER_READ) &&
1264 rtex->resource.b.b.last_level == 0 &&
1265 util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
1266 box->x, box->y, box->z,
1267 box->width, box->height,
1268 box->depth);
1269 }
1270
1271 static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
1272 struct r600_texture *rtex)
1273 {
1274 struct r600_common_screen *rscreen = rctx->screen;
1275
1276 /* There is no point in discarding depth and tiled buffers. */
1277 assert(!rtex->is_depth);
1278 assert(rtex->surface.is_linear);
1279
1280 /* Reallocate the buffer in the same pipe_resource. */
1281 r600_alloc_resource(rscreen, &rtex->resource);
1282
1283 /* Initialize the CMASK base address (needed even without CMASK). */
1284 rtex->cmask.base_address_reg =
1285 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1286
1287 p_atomic_inc(&rscreen->dirty_tex_counter);
1288
1289 rctx->num_alloc_tex_transfer_bytes += rtex->size;
1290 }
1291
1292 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1293 struct pipe_resource *texture,
1294 unsigned level,
1295 unsigned usage,
1296 const struct pipe_box *box,
1297 struct pipe_transfer **ptransfer)
1298 {
1299 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1300 struct r600_texture *rtex = (struct r600_texture*)texture;
1301 struct r600_transfer *trans;
1302 struct r600_resource *buf;
1303 unsigned offset = 0;
1304 char *map;
1305 bool use_staging_texture = false;
1306
1307 assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
1308 assert(box->width && box->height && box->depth);
1309
1310 /* Depth textures use staging unconditionally. */
1311 if (!rtex->is_depth) {
1312 /* Degrade the tile mode if we get too many transfers on APUs.
1313 * On dGPUs, the staging texture is always faster.
1314 * Only count uploads that are at least 4x4 pixels large.
1315 */
1316 if (!rctx->screen->info.has_dedicated_vram &&
1317 level == 0 &&
1318 box->width >= 4 && box->height >= 4 &&
1319 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
1320 bool can_invalidate =
1321 r600_can_invalidate_texture(rctx->screen, rtex,
1322 usage, box);
1323
1324 r600_reallocate_texture_inplace(rctx, rtex,
1325 PIPE_BIND_LINEAR,
1326 can_invalidate);
1327 }
1328
1329 /* Tiled textures need to be converted into a linear texture for CPU
1330 * access. The staging texture is always linear and is placed in GART.
1331 *
1332 * Reading from VRAM or GTT WC is slow, always use the staging
1333 * texture in this case.
1334 *
1335 * Use the staging texture for uploads if the underlying BO
1336 * is busy.
1337 */
1338 if (!rtex->surface.is_linear)
1339 use_staging_texture = true;
1340 else if (usage & PIPE_TRANSFER_READ)
1341 use_staging_texture =
1342 rtex->resource.domains & RADEON_DOMAIN_VRAM ||
1343 rtex->resource.flags & RADEON_FLAG_GTT_WC;
1344 /* Write & linear only: */
1345 else if (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf,
1346 RADEON_USAGE_READWRITE) ||
1347 !rctx->ws->buffer_wait(rtex->resource.buf, 0,
1348 RADEON_USAGE_READWRITE)) {
1349 /* It's busy. */
1350 if (r600_can_invalidate_texture(rctx->screen, rtex,
1351 usage, box))
1352 r600_texture_invalidate_storage(rctx, rtex);
1353 else
1354 use_staging_texture = true;
1355 }
1356 }
1357
1358 trans = CALLOC_STRUCT(r600_transfer);
1359 if (!trans)
1360 return NULL;
1361 pipe_resource_reference(&trans->b.b.resource, texture);
1362 trans->b.b.level = level;
1363 trans->b.b.usage = usage;
1364 trans->b.b.box = *box;
1365
1366 if (rtex->is_depth) {
1367 struct r600_texture *staging_depth;
1368
1369 if (rtex->resource.b.b.nr_samples > 1) {
1370 /* MSAA depth buffers need to be converted to single sample buffers.
1371 *
1372 * Mapping MSAA depth buffers can occur if ReadPixels is called
1373 * with a multisample GLX visual.
1374 *
1375 * First downsample the depth buffer to a temporary texture,
1376 * then decompress the temporary one to staging.
1377 *
1378 * Only the region being mapped is transfered.
1379 */
1380 struct pipe_resource resource;
1381
1382 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1383
1384 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1385 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1386 FREE(trans);
1387 return NULL;
1388 }
1389
1390 if (usage & PIPE_TRANSFER_READ) {
1391 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1392 if (!temp) {
1393 R600_ERR("failed to create a temporary depth texture\n");
1394 FREE(trans);
1395 return NULL;
1396 }
1397
1398 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1399 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1400 0, 0, 0, box->depth, 0, 0);
1401 pipe_resource_reference(&temp, NULL);
1402 }
1403
1404 /* Just get the strides. */
1405 r600_texture_get_offset(rctx->screen, staging_depth, level, NULL,
1406 &trans->b.b.stride,
1407 &trans->b.b.layer_stride);
1408 } else {
1409 /* XXX: only readback the rectangle which is being mapped? */
1410 /* XXX: when discard is true, no need to read back from depth texture */
1411 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1412 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1413 FREE(trans);
1414 return NULL;
1415 }
1416
1417 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1418 level, level,
1419 box->z, box->z + box->depth - 1,
1420 0, 0);
1421
1422 offset = r600_texture_get_offset(rctx->screen, staging_depth,
1423 level, box,
1424 &trans->b.b.stride,
1425 &trans->b.b.layer_stride);
1426 }
1427
1428 trans->staging = (struct r600_resource*)staging_depth;
1429 buf = trans->staging;
1430 } else if (use_staging_texture) {
1431 struct pipe_resource resource;
1432 struct r600_texture *staging;
1433
1434 r600_init_temp_resource_from_box(&resource, texture, box, level,
1435 R600_RESOURCE_FLAG_TRANSFER);
1436 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1437 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1438
1439 /* Create the temporary texture. */
1440 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1441 if (!staging) {
1442 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1443 FREE(trans);
1444 return NULL;
1445 }
1446 trans->staging = &staging->resource;
1447
1448 /* Just get the strides. */
1449 r600_texture_get_offset(rctx->screen, staging, 0, NULL,
1450 &trans->b.b.stride,
1451 &trans->b.b.layer_stride);
1452
1453 if (usage & PIPE_TRANSFER_READ)
1454 r600_copy_to_staging_texture(ctx, trans);
1455 else
1456 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1457
1458 buf = trans->staging;
1459 } else {
1460 /* the resource is mapped directly */
1461 offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
1462 &trans->b.b.stride,
1463 &trans->b.b.layer_stride);
1464 buf = &rtex->resource;
1465 }
1466
1467 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1468 r600_resource_reference(&trans->staging, NULL);
1469 FREE(trans);
1470 return NULL;
1471 }
1472
1473 *ptransfer = &trans->b.b;
1474 return map + offset;
1475 }
1476
1477 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1478 struct pipe_transfer* transfer)
1479 {
1480 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1481 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1482 struct pipe_resource *texture = transfer->resource;
1483 struct r600_texture *rtex = (struct r600_texture*)texture;
1484
1485 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1486 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1487 ctx->resource_copy_region(ctx, texture, transfer->level,
1488 transfer->box.x, transfer->box.y, transfer->box.z,
1489 &rtransfer->staging->b.b, transfer->level,
1490 &transfer->box);
1491 } else {
1492 r600_copy_from_staging_texture(ctx, rtransfer);
1493 }
1494 }
1495
1496 if (rtransfer->staging) {
1497 rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
1498 r600_resource_reference(&rtransfer->staging, NULL);
1499 }
1500
1501 /* Heuristic for {upload, draw, upload, draw, ..}:
1502 *
1503 * Flush the gfx IB if we've allocated too much texture storage.
1504 *
1505 * The idea is that we don't want to build IBs that use too much
1506 * memory and put pressure on the kernel memory manager and we also
1507 * want to make temporary and invalidated buffers go idle ASAP to
1508 * decrease the total memory usage or make them reusable. The memory
1509 * usage will be slightly higher than given here because of the buffer
1510 * cache in the winsys.
1511 *
1512 * The result is that the kernel memory manager is never a bottleneck.
1513 */
1514 if (rctx->num_alloc_tex_transfer_bytes > rctx->screen->info.gart_size / 4) {
1515 rctx->gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
1516 rctx->num_alloc_tex_transfer_bytes = 0;
1517 }
1518
1519 pipe_resource_reference(&transfer->resource, NULL);
1520 FREE(transfer);
1521 }
1522
1523 static const struct u_resource_vtbl r600_texture_vtbl =
1524 {
1525 NULL, /* get_handle */
1526 r600_texture_destroy, /* resource_destroy */
1527 r600_texture_transfer_map, /* transfer_map */
1528 u_default_transfer_flush_region, /* transfer_flush_region */
1529 r600_texture_transfer_unmap, /* transfer_unmap */
1530 };
1531
1532 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1533 struct pipe_resource *texture,
1534 const struct pipe_surface *templ,
1535 unsigned width0, unsigned height0,
1536 unsigned width, unsigned height)
1537 {
1538 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1539
1540 if (!surface)
1541 return NULL;
1542
1543 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1544 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1545
1546 pipe_reference_init(&surface->base.reference, 1);
1547 pipe_resource_reference(&surface->base.texture, texture);
1548 surface->base.context = pipe;
1549 surface->base.format = templ->format;
1550 surface->base.width = width;
1551 surface->base.height = height;
1552 surface->base.u = templ->u;
1553
1554 surface->width0 = width0;
1555 surface->height0 = height0;
1556
1557 return &surface->base;
1558 }
1559
1560 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1561 struct pipe_resource *tex,
1562 const struct pipe_surface *templ)
1563 {
1564 unsigned level = templ->u.tex.level;
1565 unsigned width = u_minify(tex->width0, level);
1566 unsigned height = u_minify(tex->height0, level);
1567 unsigned width0 = tex->width0;
1568 unsigned height0 = tex->height0;
1569
1570 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1571 const struct util_format_description *tex_desc
1572 = util_format_description(tex->format);
1573 const struct util_format_description *templ_desc
1574 = util_format_description(templ->format);
1575
1576 assert(tex_desc->block.bits == templ_desc->block.bits);
1577
1578 /* Adjust size of surface if and only if the block width or
1579 * height is changed. */
1580 if (tex_desc->block.width != templ_desc->block.width ||
1581 tex_desc->block.height != templ_desc->block.height) {
1582 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1583 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1584
1585 width = nblks_x * templ_desc->block.width;
1586 height = nblks_y * templ_desc->block.height;
1587
1588 width0 = util_format_get_nblocksx(tex->format, width0);
1589 height0 = util_format_get_nblocksy(tex->format, height0);
1590 }
1591 }
1592
1593 return r600_create_surface_custom(pipe, tex, templ,
1594 width0, height0,
1595 width, height);
1596 }
1597
1598 static void r600_surface_destroy(struct pipe_context *pipe,
1599 struct pipe_surface *surface)
1600 {
1601 struct r600_surface *surf = (struct r600_surface*)surface;
1602 r600_resource_reference(&surf->cb_buffer_fmask, NULL);
1603 r600_resource_reference(&surf->cb_buffer_cmask, NULL);
1604 pipe_resource_reference(&surface->texture, NULL);
1605 FREE(surface);
1606 }
1607
1608 static void r600_clear_texture(struct pipe_context *pipe,
1609 struct pipe_resource *tex,
1610 unsigned level,
1611 const struct pipe_box *box,
1612 const void *data)
1613 {
1614 struct pipe_screen *screen = pipe->screen;
1615 struct r600_texture *rtex = (struct r600_texture*)tex;
1616 struct pipe_surface tmpl = {{0}};
1617 struct pipe_surface *sf;
1618 const struct util_format_description *desc =
1619 util_format_description(tex->format);
1620
1621 tmpl.format = tex->format;
1622 tmpl.u.tex.first_layer = box->z;
1623 tmpl.u.tex.last_layer = box->z + box->depth - 1;
1624 tmpl.u.tex.level = level;
1625 sf = pipe->create_surface(pipe, tex, &tmpl);
1626 if (!sf)
1627 return;
1628
1629 if (rtex->is_depth) {
1630 unsigned clear;
1631 float depth;
1632 uint8_t stencil = 0;
1633
1634 /* Depth is always present. */
1635 clear = PIPE_CLEAR_DEPTH;
1636 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
1637
1638 if (rtex->surface.has_stencil) {
1639 clear |= PIPE_CLEAR_STENCIL;
1640 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
1641 }
1642
1643 pipe->clear_depth_stencil(pipe, sf, clear, depth, stencil,
1644 box->x, box->y,
1645 box->width, box->height, false);
1646 } else {
1647 union pipe_color_union color;
1648
1649 /* pipe_color_union requires the full vec4 representation. */
1650 if (util_format_is_pure_uint(tex->format))
1651 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
1652 else if (util_format_is_pure_sint(tex->format))
1653 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
1654 else
1655 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
1656
1657 if (screen->is_format_supported(screen, tex->format,
1658 tex->target, 0, 0,
1659 PIPE_BIND_RENDER_TARGET)) {
1660 pipe->clear_render_target(pipe, sf, &color,
1661 box->x, box->y,
1662 box->width, box->height, false);
1663 } else {
1664 /* Software fallback - just for R9G9B9E5_FLOAT */
1665 util_clear_render_target(pipe, sf, &color,
1666 box->x, box->y,
1667 box->width, box->height);
1668 }
1669 }
1670 pipe_surface_reference(&sf, NULL);
1671 }
1672
1673 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap)
1674 {
1675 const struct util_format_description *desc = util_format_description(format);
1676
1677 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1678
1679 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1680 return V_0280A0_SWAP_STD;
1681
1682 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1683 return ~0U;
1684
1685 switch (desc->nr_channels) {
1686 case 1:
1687 if (HAS_SWIZZLE(0,X))
1688 return V_0280A0_SWAP_STD; /* X___ */
1689 else if (HAS_SWIZZLE(3,X))
1690 return V_0280A0_SWAP_ALT_REV; /* ___X */
1691 break;
1692 case 2:
1693 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1694 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1695 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1696 return V_0280A0_SWAP_STD; /* XY__ */
1697 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1698 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1699 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1700 /* YX__ */
1701 return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV);
1702 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1703 return V_0280A0_SWAP_ALT; /* X__Y */
1704 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1705 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1706 break;
1707 case 3:
1708 if (HAS_SWIZZLE(0,X))
1709 return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD);
1710 else if (HAS_SWIZZLE(0,Z))
1711 return V_0280A0_SWAP_STD_REV; /* ZYX */
1712 break;
1713 case 4:
1714 /* check the middle channels, the 1st and 4th channel can be NONE */
1715 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
1716 return V_0280A0_SWAP_STD; /* XYZW */
1717 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
1718 return V_0280A0_SWAP_STD_REV; /* WZYX */
1719 } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
1720 return V_0280A0_SWAP_ALT; /* ZYXW */
1721 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
1722 /* YZWX */
1723 if (desc->is_array)
1724 return V_0280A0_SWAP_ALT_REV;
1725 else
1726 return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV);
1727 }
1728 break;
1729 }
1730 return ~0U;
1731 }
1732
1733 /* FAST COLOR CLEAR */
1734
1735 static void evergreen_set_clear_color(struct r600_texture *rtex,
1736 enum pipe_format surface_format,
1737 const union pipe_color_union *color)
1738 {
1739 union util_color uc;
1740
1741 memset(&uc, 0, sizeof(uc));
1742
1743 if (rtex->surface.bpe == 16) {
1744 /* DCC fast clear only:
1745 * CLEAR_WORD0 = R = G = B
1746 * CLEAR_WORD1 = A
1747 */
1748 assert(color->ui[0] == color->ui[1] &&
1749 color->ui[0] == color->ui[2]);
1750 uc.ui[0] = color->ui[0];
1751 uc.ui[1] = color->ui[3];
1752 } else if (util_format_is_pure_uint(surface_format)) {
1753 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1754 } else if (util_format_is_pure_sint(surface_format)) {
1755 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1756 } else {
1757 util_pack_color(color->f, surface_format, &uc);
1758 }
1759
1760 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1761 }
1762
1763 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1764 struct pipe_framebuffer_state *fb,
1765 struct r600_atom *fb_state,
1766 unsigned *buffers, ubyte *dirty_cbufs,
1767 const union pipe_color_union *color)
1768 {
1769 int i;
1770
1771 /* This function is broken in BE, so just disable this path for now */
1772 #ifdef PIPE_ARCH_BIG_ENDIAN
1773 return;
1774 #endif
1775
1776 if (rctx->render_cond)
1777 return;
1778
1779 for (i = 0; i < fb->nr_cbufs; i++) {
1780 struct r600_texture *tex;
1781 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1782
1783 if (!fb->cbufs[i])
1784 continue;
1785
1786 /* if this colorbuffer is not being cleared */
1787 if (!(*buffers & clear_bit))
1788 continue;
1789
1790 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1791
1792 /* the clear is allowed if all layers are bound */
1793 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1794 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1795 continue;
1796 }
1797
1798 /* cannot clear mipmapped textures */
1799 if (fb->cbufs[i]->texture->last_level != 0) {
1800 continue;
1801 }
1802
1803 /* only supported on tiled surfaces */
1804 if (tex->surface.is_linear) {
1805 continue;
1806 }
1807
1808 /* shared textures can't use fast clear without an explicit flush,
1809 * because there is no way to communicate the clear color among
1810 * all clients
1811 */
1812 if (tex->resource.b.is_shared &&
1813 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1814 continue;
1815
1816 /* Use a slow clear for small surfaces where the cost of
1817 * the eliminate pass can be higher than the benefit of fast
1818 * clear. AMDGPU-pro does this, but the numbers may differ.
1819 *
1820 * This helps on both dGPUs and APUs, even small ones.
1821 */
1822 if (tex->resource.b.b.nr_samples <= 1 &&
1823 tex->resource.b.b.width0 * tex->resource.b.b.height0 <= 300 * 300)
1824 continue;
1825
1826 {
1827 /* 128-bit formats are unusupported */
1828 if (tex->surface.bpe > 8) {
1829 continue;
1830 }
1831
1832 /* ensure CMASK is enabled */
1833 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1834 if (tex->cmask.size == 0) {
1835 continue;
1836 }
1837
1838 /* Do the fast clear. */
1839 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1840 tex->cmask.offset, tex->cmask.size, 0,
1841 R600_COHERENCY_CB_META);
1842
1843 bool need_compressed_update = !tex->dirty_level_mask;
1844
1845 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1846
1847 if (need_compressed_update)
1848 p_atomic_inc(&rctx->screen->compressed_colortex_counter);
1849 }
1850
1851 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1852
1853 if (dirty_cbufs)
1854 *dirty_cbufs |= 1 << i;
1855 rctx->set_atom_dirty(rctx, fb_state, true);
1856 *buffers &= ~clear_bit;
1857 }
1858 }
1859
1860 static struct pipe_memory_object *
1861 r600_memobj_from_handle(struct pipe_screen *screen,
1862 struct winsys_handle *whandle,
1863 bool dedicated)
1864 {
1865 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1866 struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
1867 struct pb_buffer *buf = NULL;
1868 uint32_t stride, offset;
1869
1870 if (!memobj)
1871 return NULL;
1872
1873 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1874 rscreen->info.max_alignment,
1875 &stride, &offset);
1876 if (!buf) {
1877 free(memobj);
1878 return NULL;
1879 }
1880
1881 memobj->b.dedicated = dedicated;
1882 memobj->buf = buf;
1883 memobj->stride = stride;
1884 memobj->offset = offset;
1885
1886 return (struct pipe_memory_object *)memobj;
1887
1888 }
1889
1890 static void
1891 r600_memobj_destroy(struct pipe_screen *screen,
1892 struct pipe_memory_object *_memobj)
1893 {
1894 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1895
1896 pb_reference(&memobj->buf, NULL);
1897 free(memobj);
1898 }
1899
1900 static struct pipe_resource *
1901 r600_texture_from_memobj(struct pipe_screen *screen,
1902 const struct pipe_resource *templ,
1903 struct pipe_memory_object *_memobj,
1904 uint64_t offset)
1905 {
1906 int r;
1907 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1908 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1909 struct r600_texture *rtex;
1910 struct radeon_surf surface = {};
1911 struct radeon_bo_metadata metadata = {};
1912 enum radeon_surf_mode array_mode;
1913 bool is_scanout;
1914 struct pb_buffer *buf = NULL;
1915
1916 if (memobj->b.dedicated) {
1917 rscreen->ws->buffer_get_metadata(memobj->buf, &metadata);
1918 r600_surface_import_metadata(rscreen, &surface, &metadata,
1919 &array_mode, &is_scanout);
1920 } else {
1921 /**
1922 * The bo metadata is unset for un-dedicated images. So we fall
1923 * back to linear. See answer to question 5 of the
1924 * VK_KHX_external_memory spec for some details.
1925 *
1926 * It is possible that this case isn't going to work if the
1927 * surface pitch isn't correctly aligned by default.
1928 *
1929 * In order to support it correctly we require multi-image
1930 * metadata to be syncrhonized between radv and radeonsi. The
1931 * semantics of associating multiple image metadata to a memory
1932 * object on the vulkan export side are not concretely defined
1933 * either.
1934 *
1935 * All the use cases we are aware of at the moment for memory
1936 * objects use dedicated allocations. So lets keep the initial
1937 * implementation simple.
1938 *
1939 * A possible alternative is to attempt to reconstruct the
1940 * tiling information when the TexParameter TEXTURE_TILING_EXT
1941 * is set.
1942 */
1943 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1944 is_scanout = false;
1945
1946 }
1947
1948 r = r600_init_surface(rscreen, &surface, templ,
1949 array_mode, memobj->stride,
1950 offset, true, is_scanout,
1951 false);
1952 if (r)
1953 return NULL;
1954
1955 rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface);
1956 if (!rtex)
1957 return NULL;
1958
1959 /* r600_texture_create_object doesn't increment refcount of
1960 * memobj->buf, so increment it here.
1961 */
1962 pb_reference(&buf, memobj->buf);
1963
1964 rtex->resource.b.is_shared = true;
1965 rtex->resource.external_usage = PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE;
1966
1967 return &rtex->resource.b.b;
1968 }
1969
1970 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1971 {
1972 rscreen->b.resource_from_handle = r600_texture_from_handle;
1973 rscreen->b.resource_get_handle = r600_texture_get_handle;
1974 rscreen->b.resource_get_info = r600_texture_get_info;
1975 rscreen->b.resource_from_memobj = r600_texture_from_memobj;
1976 rscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
1977 rscreen->b.memobj_destroy = r600_memobj_destroy;
1978 }
1979
1980 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1981 {
1982 rctx->b.create_surface = r600_create_surface;
1983 rctx->b.surface_destroy = r600_surface_destroy;
1984 rctx->b.clear_texture = r600_clear_texture;
1985 }