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Revert "r600g: precompute some of the hw state"
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <errno.h>
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_math.h>
31 #include <util/u_inlines.h>
32 #include <util/u_memory.h>
33 #include "state_tracker/drm_driver.h"
34 #include "r600_screen.h"
35 #include "r600_context.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
38 #include "r600d.h"
39
40 extern struct u_resource_vtbl r600_texture_vtbl;
41
42 /* Copy from a tiled texture to a detiled one. */
43 static void r600_copy_from_tiled_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
44 {
45 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
46 struct pipe_resource *texture = transfer->resource;
47 struct pipe_subresource subdst;
48
49 subdst.face = 0;
50 subdst.level = 0;
51 ctx->resource_copy_region(ctx, rtransfer->linear_texture,
52 subdst, 0, 0, 0, texture, transfer->sr,
53 transfer->box.x, transfer->box.y, transfer->box.z,
54 transfer->box.width, transfer->box.height);
55 }
56
57 static unsigned long r600_texture_get_offset(struct r600_resource_texture *rtex,
58 unsigned level, unsigned zslice,
59 unsigned face)
60 {
61 unsigned long offset = rtex->offset[level];
62
63 switch (rtex->resource.base.b.target) {
64 case PIPE_TEXTURE_3D:
65 assert(face == 0);
66 return offset + zslice * rtex->layer_size[level];
67 case PIPE_TEXTURE_CUBE:
68 assert(zslice == 0);
69 return offset + face * rtex->layer_size[level];
70 default:
71 assert(zslice == 0 && face == 0);
72 return offset;
73 }
74 }
75
76 static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_resource_texture *rtex)
77 {
78 struct pipe_resource *ptex = &rtex->resource.base.b;
79 unsigned long w, h, pitch, size, layer_size, i, offset;
80
81 rtex->bpt = util_format_get_blocksize(ptex->format);
82 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
83 w = u_minify(ptex->width0, i);
84 h = u_minify(ptex->height0, i);
85 h = util_next_power_of_two(h);
86 pitch = util_format_get_stride(ptex->format, align(w, 64));
87 pitch = align(pitch, 256);
88 layer_size = pitch * h;
89 if (ptex->target == PIPE_TEXTURE_CUBE)
90 size = layer_size * 6;
91 else
92 size = layer_size * u_minify(ptex->depth0, i);
93 rtex->offset[i] = offset;
94 rtex->layer_size[i] = layer_size;
95 rtex->pitch[i] = pitch;
96 rtex->width[i] = w;
97 rtex->height[i] = h;
98 offset += size;
99 }
100 rtex->size = offset;
101 }
102
103 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
104 const struct pipe_resource *templ)
105 {
106 struct r600_resource_texture *rtex;
107 struct r600_resource *resource;
108 struct r600_screen *rscreen = r600_screen(screen);
109
110 rtex = CALLOC_STRUCT(r600_resource_texture);
111 if (!rtex) {
112 return NULL;
113 }
114 resource = &rtex->resource;
115 resource->base.b = *templ;
116 resource->base.vtbl = &r600_texture_vtbl;
117 pipe_reference_init(&resource->base.b.reference, 1);
118 resource->base.b.screen = screen;
119 r600_setup_miptree(rscreen, rtex);
120
121 /* FIXME alignment 4096 enought ? too much ? */
122 resource->domain = r600_domain_from_usage(resource->base.b.bind);
123 resource->bo = radeon_bo(rscreen->rw, 0, rtex->size, 4096, NULL);
124 if (resource->bo == NULL) {
125 FREE(rtex);
126 return NULL;
127 }
128 return &resource->base.b;
129 }
130
131 static void r600_texture_destroy(struct pipe_screen *screen,
132 struct pipe_resource *ptex)
133 {
134 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
135 struct r600_resource *resource = &rtex->resource;
136 struct r600_screen *rscreen = r600_screen(screen);
137 unsigned i;
138
139 if (resource->bo) {
140 radeon_bo_decref(rscreen->rw, resource->bo);
141 }
142 if (rtex->uncompressed) {
143 radeon_bo_decref(rscreen->rw, rtex->uncompressed);
144 }
145 for (i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
146 radeon_state_decref(rtex->scissor[i]);
147 radeon_state_decref(rtex->cb0[i]);
148 radeon_state_decref(rtex->db[i]);
149 }
150 FREE(rtex);
151 }
152
153 static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen,
154 struct pipe_resource *texture,
155 unsigned face, unsigned level,
156 unsigned zslice, unsigned flags)
157 {
158 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
159 struct pipe_surface *surface = CALLOC_STRUCT(pipe_surface);
160 unsigned long offset;
161
162 if (surface == NULL)
163 return NULL;
164 offset = r600_texture_get_offset(rtex, level, zslice, face);
165 pipe_reference_init(&surface->reference, 1);
166 pipe_resource_reference(&surface->texture, texture);
167 surface->format = texture->format;
168 surface->width = u_minify(texture->width0, level);
169 surface->height = u_minify(texture->height0, level);
170 surface->offset = offset;
171 surface->usage = flags;
172 surface->zslice = zslice;
173 surface->texture = texture;
174 surface->face = face;
175 surface->level = level;
176 return surface;
177 }
178
179 static void r600_tex_surface_destroy(struct pipe_surface *surface)
180 {
181 pipe_resource_reference(&surface->texture, NULL);
182 FREE(surface);
183 }
184
185 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
186 const struct pipe_resource *templ,
187 struct winsys_handle *whandle)
188 {
189 struct radeon *rw = (struct radeon*)screen->winsys;
190 struct r600_resource_texture *rtex;
191 struct r600_resource *resource;
192 struct radeon_bo *bo = NULL;
193
194 bo = radeon_bo(rw, whandle->handle, 0, 0, NULL);
195 if (bo == NULL) {
196 return NULL;
197 }
198
199 /* Support only 2D textures without mipmaps */
200 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
201 templ->depth0 != 1 || templ->last_level != 0)
202 return NULL;
203
204 rtex = CALLOC_STRUCT(r600_resource_texture);
205 if (rtex == NULL)
206 return NULL;
207
208 resource = &rtex->resource;
209 resource->base.b = *templ;
210 resource->base.vtbl = &r600_texture_vtbl;
211 pipe_reference_init(&resource->base.b.reference, 1);
212 resource->base.b.screen = screen;
213 resource->bo = bo;
214 rtex->pitch_override = whandle->stride;
215 rtex->bpt = util_format_get_blocksize(templ->format);
216 rtex->pitch[0] = whandle->stride;
217 rtex->offset[0] = 0;
218 rtex->size = align(rtex->pitch[0] * templ->height0, 64);
219
220 return &resource->base.b;
221 }
222
223 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
224 struct pipe_resource *texture,
225 unsigned face, unsigned level)
226 {
227 /* FIXME */
228 return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
229 }
230
231 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
232 struct pipe_resource *texture,
233 struct pipe_subresource sr,
234 unsigned usage,
235 const struct pipe_box *box)
236 {
237 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
238 struct pipe_resource resource;
239 struct r600_transfer *trans;
240
241 trans = CALLOC_STRUCT(r600_transfer);
242 if (trans == NULL)
243 return NULL;
244 pipe_resource_reference(&trans->transfer.resource, texture);
245 trans->transfer.sr = sr;
246 trans->transfer.usage = usage;
247 trans->transfer.box = *box;
248 trans->transfer.stride = rtex->pitch[sr.level];
249 trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
250 if (rtex->tilled && !rtex->depth) {
251 resource.target = PIPE_TEXTURE_2D;
252 resource.format = texture->format;
253 resource.width0 = box->width;
254 resource.height0 = box->height;
255 resource.depth0 = 0;
256 resource.last_level = 0;
257 resource.nr_samples = 0;
258 resource.usage = PIPE_USAGE_DYNAMIC;
259 resource.bind = 0;
260 resource.flags = 0;
261 /* For texture reading, the temporary (detiled) texture is used as
262 * a render target when blitting from a tiled texture. */
263 if (usage & PIPE_TRANSFER_READ) {
264 resource.bind |= PIPE_BIND_RENDER_TARGET;
265 }
266 /* For texture writing, the temporary texture is used as a sampler
267 * when blitting into a tiled texture. */
268 if (usage & PIPE_TRANSFER_WRITE) {
269 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
270 }
271 /* Create the temporary texture. */
272 trans->linear_texture = ctx->screen->resource_create(ctx->screen, &resource);
273 if (trans->linear_texture == NULL) {
274 R600_ERR("failed to create temporary texture to hold untiled copy\n");
275 pipe_resource_reference(&trans->transfer.resource, NULL);
276 FREE(trans);
277 return NULL;
278 }
279 if (usage & PIPE_TRANSFER_READ) {
280 /* We cannot map a tiled texture directly because the data is
281 * in a different order, therefore we do detiling using a blit. */
282 r600_copy_from_tiled_texture(ctx, trans);
283 /* Always referenced in the blit. */
284 ctx->flush(ctx, 0, NULL);
285 }
286 }
287 return &trans->transfer;
288 }
289
290 void r600_texture_transfer_destroy(struct pipe_context *ctx,
291 struct pipe_transfer *transfer)
292 {
293 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
294
295 if (rtransfer->linear_texture) {
296 pipe_resource_reference(&rtransfer->linear_texture, NULL);
297 }
298 pipe_resource_reference(&transfer->resource, NULL);
299 FREE(transfer);
300 }
301
302 void* r600_texture_transfer_map(struct pipe_context *ctx,
303 struct pipe_transfer* transfer)
304 {
305 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
306 struct radeon_bo *bo;
307 enum pipe_format format = transfer->resource->format;
308 struct r600_screen *rscreen = r600_screen(ctx->screen);
309 struct r600_resource_texture *rtex;
310 unsigned long offset = 0;
311 char *map;
312 int r;
313
314 r600_flush(ctx, 0, NULL);
315 if (rtransfer->linear_texture) {
316 bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
317 } else {
318 rtex = (struct r600_resource_texture*)transfer->resource;
319 if (rtex->depth) {
320 r = r600_texture_from_depth(ctx, rtex, transfer->sr.level);
321 if (r) {
322 return NULL;
323 }
324 r600_flush(ctx, 0, NULL);
325 bo = rtex->uncompressed;
326 } else {
327 bo = ((struct r600_resource *)transfer->resource)->bo;
328 }
329 offset = rtransfer->offset +
330 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
331 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
332 }
333 if (radeon_bo_map(rscreen->rw, bo)) {
334 return NULL;
335 }
336 radeon_bo_wait(rscreen->rw, bo);
337
338 map = bo->data;
339 return map + offset;
340 }
341
342 void r600_texture_transfer_unmap(struct pipe_context *ctx,
343 struct pipe_transfer* transfer)
344 {
345 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
346 struct r600_screen *rscreen = r600_screen(ctx->screen);
347 struct r600_resource_texture *rtex;
348 struct radeon_bo *bo;
349
350 if (rtransfer->linear_texture) {
351 bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
352 } else {
353 rtex = (struct r600_resource_texture*)transfer->resource;
354 if (rtex->depth) {
355 bo = rtex->uncompressed;
356 } else {
357 bo = ((struct r600_resource *)transfer->resource)->bo;
358 }
359 }
360 radeon_bo_unmap(rscreen->rw, bo);
361 }
362
363 struct u_resource_vtbl r600_texture_vtbl =
364 {
365 u_default_resource_get_handle, /* get_handle */
366 r600_texture_destroy, /* resource_destroy */
367 r600_texture_is_referenced, /* is_resource_referenced */
368 r600_texture_get_transfer, /* get_transfer */
369 r600_texture_transfer_destroy, /* transfer_destroy */
370 r600_texture_transfer_map, /* transfer_map */
371 u_default_transfer_flush_region,/* transfer_flush_region */
372 r600_texture_transfer_unmap, /* transfer_unmap */
373 u_default_transfer_inline_write /* transfer_inline_write */
374 };
375
376 void r600_init_screen_texture_functions(struct pipe_screen *screen)
377 {
378 screen->get_tex_surface = r600_get_tex_surface;
379 screen->tex_surface_destroy = r600_tex_surface_destroy;
380 }
381
382 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
383 const unsigned char *swizzle_view)
384 {
385 unsigned i;
386 unsigned char swizzle[4];
387 unsigned result = 0;
388 const uint32_t swizzle_shift[4] = {
389 16, 19, 22, 25,
390 };
391 const uint32_t swizzle_bit[4] = {
392 0, 1, 2, 3,
393 };
394
395 if (swizzle_view) {
396 /* Combine two sets of swizzles. */
397 for (i = 0; i < 4; i++) {
398 swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
399 swizzle_format[swizzle_view[i]] : swizzle_view[i];
400 }
401 } else {
402 memcpy(swizzle, swizzle_format, 4);
403 }
404
405 /* Get swizzle. */
406 for (i = 0; i < 4; i++) {
407 switch (swizzle[i]) {
408 case UTIL_FORMAT_SWIZZLE_Y:
409 result |= swizzle_bit[1] << swizzle_shift[i];
410 break;
411 case UTIL_FORMAT_SWIZZLE_Z:
412 result |= swizzle_bit[2] << swizzle_shift[i];
413 break;
414 case UTIL_FORMAT_SWIZZLE_W:
415 result |= swizzle_bit[3] << swizzle_shift[i];
416 break;
417 case UTIL_FORMAT_SWIZZLE_0:
418 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
419 break;
420 case UTIL_FORMAT_SWIZZLE_1:
421 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
422 break;
423 default: /* UTIL_FORMAT_SWIZZLE_X */
424 result |= swizzle_bit[0] << swizzle_shift[i];
425 }
426 }
427 return result;
428 }
429
430 /* texture format translate */
431 uint32_t r600_translate_texformat(enum pipe_format format,
432 const unsigned char *swizzle_view,
433 uint32_t *word4_p, uint32_t *yuv_format_p)
434 {
435 uint32_t result = 0, word4 = 0, yuv_format = 0;
436 const struct util_format_description *desc;
437 boolean uniform = TRUE;
438 int i;
439 const uint32_t sign_bit[4] = {
440 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
441 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
442 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
443 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
444 };
445 desc = util_format_description(format);
446
447 /* Colorspace (return non-RGB formats directly). */
448 switch (desc->colorspace) {
449 /* Depth stencil formats */
450 case UTIL_FORMAT_COLORSPACE_ZS:
451 switch (format) {
452 case PIPE_FORMAT_Z16_UNORM:
453 result = V_0280A0_COLOR_16;
454 goto out_word4;
455 case PIPE_FORMAT_Z24X8_UNORM:
456 result = V_0280A0_COLOR_8_24;
457 goto out_word4;
458 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
459 result = V_0280A0_COLOR_8_24;
460 goto out_word4;
461 default:
462 goto out_unknown;
463 }
464
465 case UTIL_FORMAT_COLORSPACE_YUV:
466 yuv_format |= (1 << 30);
467 switch (format) {
468 case PIPE_FORMAT_UYVY:
469 case PIPE_FORMAT_YUYV:
470 default:
471 break;
472 }
473 goto out_unknown; /* TODO */
474
475 case UTIL_FORMAT_COLORSPACE_SRGB:
476 word4 |= S_038010_FORCE_DEGAMMA(1);
477 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
478 goto out_unknown; /* fails for some reason - TODO */
479 break;
480
481 default:
482 break;
483 }
484
485 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
486
487 /* S3TC formats. TODO */
488 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
489 goto out_unknown;
490 }
491
492
493 for (i = 0; i < desc->nr_channels; i++) {
494 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
495 word4 |= sign_bit[i];
496 }
497 }
498
499 /* R8G8Bx_SNORM - TODO CxV8U8 */
500
501 /* RGTC - TODO */
502
503 /* See whether the components are of the same size. */
504 for (i = 1; i < desc->nr_channels; i++) {
505 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
506 }
507
508 /* Non-uniform formats. */
509 if (!uniform) {
510 switch(desc->nr_channels) {
511 case 3:
512 if (desc->channel[0].size == 5 &&
513 desc->channel[1].size == 6 &&
514 desc->channel[2].size == 5) {
515 result |= V_0280A0_COLOR_5_6_5;
516 goto out_word4;
517 }
518 goto out_unknown;
519 case 4:
520 if (desc->channel[0].size == 5 &&
521 desc->channel[1].size == 5 &&
522 desc->channel[2].size == 5 &&
523 desc->channel[3].size == 1) {
524 result |= V_0280A0_COLOR_1_5_5_5;
525 goto out_word4;
526 }
527 if (desc->channel[0].size == 10 &&
528 desc->channel[1].size == 10 &&
529 desc->channel[2].size == 10 &&
530 desc->channel[3].size == 2) {
531 result |= V_0280A0_COLOR_10_10_10_2;
532 goto out_word4;
533 }
534 goto out_unknown;
535 }
536 goto out_unknown;
537 }
538
539 /* uniform formats */
540 switch (desc->channel[0].type) {
541 case UTIL_FORMAT_TYPE_UNSIGNED:
542 case UTIL_FORMAT_TYPE_SIGNED:
543 if (!desc->channel[0].normalized &&
544 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
545 goto out_unknown;
546 }
547
548 switch (desc->channel[0].size) {
549 case 4:
550 switch (desc->nr_channels) {
551 case 2:
552 result |= V_0280A0_COLOR_4_4;
553 goto out_word4;
554 case 4:
555 result |= V_0280A0_COLOR_4_4_4_4;
556 goto out_word4;
557 }
558 goto out_unknown;
559 case 8:
560 switch (desc->nr_channels) {
561 case 1:
562 result |= V_0280A0_COLOR_8;
563 goto out_word4;
564 case 2:
565 result |= V_0280A0_COLOR_8_8;
566 goto out_word4;
567 case 4:
568 result |= V_0280A0_COLOR_8_8_8_8;
569 goto out_word4;
570 }
571 goto out_unknown;
572 case 16:
573 switch (desc->nr_channels) {
574 case 1:
575 result |= V_0280A0_COLOR_16;
576 goto out_word4;
577 case 2:
578 result |= V_0280A0_COLOR_16_16;
579 goto out_word4;
580 case 4:
581 result |= V_0280A0_COLOR_16_16_16_16;
582 goto out_word4;
583 }
584 }
585 goto out_unknown;
586
587 case UTIL_FORMAT_TYPE_FLOAT:
588 switch (desc->channel[0].size) {
589 case 16:
590 switch (desc->nr_channels) {
591 case 1:
592 result |= V_0280A0_COLOR_16_FLOAT;
593 goto out_word4;
594 case 2:
595 result |= V_0280A0_COLOR_16_16_FLOAT;
596 goto out_word4;
597 case 4:
598 result |= V_0280A0_COLOR_16_16_16_16_FLOAT;
599 goto out_word4;
600 }
601 goto out_unknown;
602 case 32:
603 switch (desc->nr_channels) {
604 case 1:
605 result |= V_0280A0_COLOR_32_FLOAT;
606 goto out_word4;
607 case 2:
608 result |= V_0280A0_COLOR_32_32_FLOAT;
609 goto out_word4;
610 case 4:
611 result |= V_0280A0_COLOR_32_32_32_32_FLOAT;
612 goto out_word4;
613 }
614 }
615
616 }
617 out_word4:
618 if (word4_p)
619 *word4_p = word4;
620 if (yuv_format_p)
621 *yuv_format_p = yuv_format;
622 return result;
623 out_unknown:
624 R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
625 return ~0;
626 }
627
628 int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
629 {
630 struct r600_screen *rscreen = r600_screen(ctx->screen);
631 int r;
632
633 if (!rtexture->depth) {
634 /* This shouldn't happen maybe print a warning */
635 return 0;
636 }
637 if (rtexture->uncompressed && !rtexture->dirty) {
638 /* Uncompressed bo already in good state */
639 return 0;
640 }
641
642 /* allocate uncompressed texture */
643 if (rtexture->uncompressed == NULL) {
644 rtexture->uncompressed = radeon_bo(rscreen->rw, 0, rtexture->size, 4096, NULL);
645 if (rtexture->uncompressed == NULL) {
646 return -ENOMEM;
647 }
648 }
649
650 /* render a rectangle covering whole buffer to uncompress depth */
651 r = r600_blit_uncompress_depth(ctx, rtexture, level);
652 if (r) {
653 return r;
654 }
655
656 rtexture->dirty = 0;
657 return 0;
658 }
659
660 static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscreen,
661 struct r600_resource_texture *rtexture,
662 unsigned level)
663 {
664 struct radeon_state *rstate;
665
666 rstate = radeon_state(rscreen->rw, R600_STATE_SCISSOR, 0);
667 if (rstate == NULL)
668 return NULL;
669
670 /* set states (most default value are 0 and struct already
671 * initialized to 0, thus avoid resetting them)
672 */
673 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
674 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
675 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
676 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
677 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
678 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
679 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
680 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
681 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
682 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
683 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
684 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
685 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
686 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
687 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
688 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
689 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
690 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
691
692 if (radeon_state_pm4(rstate)) {
693 radeon_state_decref(rstate);
694 return NULL;
695 }
696 return rstate;
697 }
698
699 static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
700 struct r600_resource_texture *rtexture,
701 unsigned level)
702 {
703 struct radeon_state *rstate;
704 struct r600_resource *rbuffer;
705 unsigned pitch, slice;
706 unsigned color_info;
707 unsigned format, swap, ntype;
708 const struct util_format_description *desc;
709
710 rstate = radeon_state(rscreen->rw, R600_STATE_CB0, 0);
711 if (rstate == NULL)
712 return NULL;
713 rbuffer = &rtexture->resource;
714
715 /* set states (most default value are 0 and struct already
716 * initialized to 0, thus avoid resetting them)
717 */
718 pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
719 slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
720 ntype = 0;
721 desc = util_format_description(rbuffer->base.b.format);
722 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
723 ntype = V_0280A0_NUMBER_SRGB;
724 format = r600_translate_colorformat(rtexture->resource.base.b.format);
725 swap = r600_translate_colorswap(rtexture->resource.base.b.format);
726 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
727 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
728 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
729 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
730 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
731 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
732 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
733 rstate->nbo = 3;
734 color_info = 0;
735 } else {
736 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
737 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
738 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
739 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
740 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
741 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
742 rstate->nbo = 3;
743 color_info = S_0280A0_SOURCE_FORMAT(1);
744 }
745 color_info |= S_0280A0_FORMAT(format) |
746 S_0280A0_COMP_SWAP(swap) |
747 S_0280A0_BLEND_CLAMP(1) |
748 S_0280A0_NUMBER_TYPE(ntype);
749 rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
750 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
751 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
752 S_028060_SLICE_TILE_MAX(slice);
753
754 if (radeon_state_pm4(rstate)) {
755 radeon_state_decref(rstate);
756 return NULL;
757 }
758 return rstate;
759 }
760
761 static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
762 struct r600_resource_texture *rtexture,
763 unsigned level)
764 {
765 struct radeon_state *rstate;
766 struct r600_resource *rbuffer;
767 unsigned pitch, slice, format;
768
769 rstate = radeon_state(rscreen->rw, R600_STATE_DB, 0);
770 if (rstate == NULL)
771 return NULL;
772 rbuffer = &rtexture->resource;
773
774 /* set states (most default value are 0 and struct already
775 * initialized to 0, thus avoid resetting them)
776 */
777 pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
778 slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
779 format = r600_translate_dbformat(rbuffer->base.b.format);
780 rstate->states[R600_DB__DB_DEPTH_BASE] = rtexture->offset[level] >> 8;
781 rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtexture->array_mode) |
782 S_028010_FORMAT(format);
783 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
784 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
785 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
786 S_028000_SLICE_TILE_MAX(slice);
787 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
788 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
789 rstate->nbo = 1;
790
791 if (radeon_state_pm4(rstate)) {
792 radeon_state_decref(rstate);
793 return NULL;
794 }
795 return rstate;
796 }
797
798 int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
799 {
800 struct r600_screen *rscreen = r600_screen(ctx->screen);
801
802 if (rtexture->scissor[level] == NULL) {
803 rtexture->scissor[level] = r600_texture_state_scissor(rscreen, rtexture, level);
804 if (rtexture->scissor[level] == NULL) {
805 R600_ERR("failed to create scissor for uncompressing depth\n");
806 return -ENOMEM;
807 }
808 }
809 return 0;
810 }
811
812 static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscreen,
813 struct r600_resource_texture *rtexture,
814 unsigned level)
815 {
816 struct radeon_state *rstate;
817
818 rstate = radeon_state(rscreen->rw, R600_STATE_VIEWPORT, 0);
819 if (rstate == NULL)
820 return NULL;
821
822 /* set states (most default value are 0 and struct already
823 * initialized to 0, thus avoid resetting them)
824 */
825 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0);
826 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0);
827 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0);
828 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0);
829 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
830 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
831 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
832 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
833
834 if (radeon_state_pm4(rstate)) {
835 radeon_state_decref(rstate);
836 return NULL;
837 }
838 return rstate;
839 }
840
841 int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
842 {
843 struct r600_screen *rscreen = r600_screen(ctx->screen);
844
845 if (rtexture->cb0[level] == NULL) {
846 rtexture->cb0[level] = r600_texture_state_cb0(rscreen, rtexture, level);
847 if (rtexture->cb0[level] == NULL) {
848 R600_ERR("failed to create cb0 state for texture\n");
849 return -ENOMEM;
850 }
851 }
852 return 0;
853 }
854
855 int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
856 {
857 struct r600_screen *rscreen = r600_screen(ctx->screen);
858
859 if (rtexture->db[level] == NULL) {
860 rtexture->db[level] = r600_texture_state_db(rscreen, rtexture, level);
861 if (rtexture->db[level] == NULL) {
862 R600_ERR("failed to create db state for texture\n");
863 return -ENOMEM;
864 }
865 }
866 return 0;
867 }
868
869 int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
870 {
871 struct r600_screen *rscreen = r600_screen(ctx->screen);
872
873 if (rtexture->viewport[level] == NULL) {
874 rtexture->viewport[level] = r600_texture_state_viewport(rscreen, rtexture, level);
875 if (rtexture->viewport[level] == NULL) {
876 R600_ERR("failed to create viewport state for texture\n");
877 return -ENOMEM;
878 }
879 }
880 return 0;
881 }