src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_format_s3tc.h>
  31 #include <util/u_math.h>
  32 #include <util/u_inlines.h>
  33 #include <util/u_memory.h>
  34 #include "state_tracker/drm_driver.h"
  35 #include "pipebuffer/pb_buffer.h"
  36 #include "r600_pipe.h"
  37 #include "r600_resource.h"
  38 #include "r600d.h"
  39 #include "r600_formats.h"
  40
  41 /* Copy from a full GPU texture to a transfer's staging one. */
  42 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  43 {
  44         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  45         struct pipe_resource *texture = transfer->resource;
  46
  47         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  48                                 0, 0, 0, 0, texture, transfer->level,
  49                                 &transfer->box);
  50 }
  51
  52
  53 /* Copy from a transfer's staging texture to a full GPU one. */
  54 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  55 {
  56         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  57         struct pipe_resource *texture = transfer->resource;
  58         struct pipe_box sbox;
  59
  60         sbox.x = sbox.y = sbox.z = 0;
  61         sbox.width = transfer->box.width;
  62         sbox.height = transfer->box.height;
  63         /* XXX that might be wrong */
  64         sbox.depth = 1;
  65         ctx->resource_copy_region(ctx, texture, transfer->level,
  66                                   transfer->box.x, transfer->box.y, transfer->box.z,
  67                                   rtransfer->staging_texture,
  68                                   0, &sbox);
  69
  70         ctx->flush(ctx, NULL);
  71 }
  72
  73 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  74                                         unsigned level, unsigned layer)
  75 {
  76         unsigned offset = rtex->offset[level];
  77
  78         switch (rtex->resource.b.b.b.target) {
  79         case PIPE_TEXTURE_3D:
  80         case PIPE_TEXTURE_CUBE:
  81         default:
  82                 return offset + layer * rtex->layer_size[level];
  83         }
  84 }
  85
  86 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
  87                                          enum pipe_format format,
  88                                          unsigned array_mode)
  89 {
  90         struct r600_screen* rscreen = (struct r600_screen *)screen;
  91         unsigned pixsize = util_format_get_blocksize(format);
  92         int p_align;
  93
  94         switch(array_mode) {
  95         case V_038000_ARRAY_1D_TILED_THIN1:
  96                 p_align = MAX2(8,
  97                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
  98                 break;
  99         case V_038000_ARRAY_2D_TILED_THIN1:
 100                 p_align = MAX2(rscreen->tiling_info->num_banks,
 101                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 102                                 rscreen->tiling_info->num_banks)) * 8;
 103                 break;
 104         case V_038000_ARRAY_LINEAR_ALIGNED:
 105                 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
 106                 break;
 107         case V_038000_ARRAY_LINEAR_GENERAL:
 108         default:
 109                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 110                 break;
 111         }
 112         return p_align;
 113 }
 114
 115 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 116                                           unsigned array_mode)
 117 {
 118         struct r600_screen* rscreen = (struct r600_screen *)screen;
 119         int h_align;
 120
 121         switch (array_mode) {
 122         case V_038000_ARRAY_2D_TILED_THIN1:
 123                 h_align = rscreen->tiling_info->num_channels * 8;
 124                 break;
 125         case V_038000_ARRAY_1D_TILED_THIN1:
 126         case V_038000_ARRAY_LINEAR_ALIGNED:
 127                 h_align = 8;
 128                 break;
 129         case V_038000_ARRAY_LINEAR_GENERAL:
 130         default:
 131                 h_align = 1;
 132                 break;
 133         }
 134         return h_align;
 135 }
 136
 137 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 138                                         enum pipe_format format,
 139                                         unsigned array_mode)
 140 {
 141         struct r600_screen* rscreen = (struct r600_screen *)screen;
 142         unsigned pixsize = util_format_get_blocksize(format);
 143         int p_align = r600_get_block_alignment(screen, format, array_mode);
 144         int h_align = r600_get_height_alignment(screen, array_mode);
 145         int b_align;
 146
 147         switch (array_mode) {
 148         case V_038000_ARRAY_2D_TILED_THIN1:
 149                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 150                                p_align * pixsize * h_align);
 151                 break;
 152         case V_038000_ARRAY_1D_TILED_THIN1:
 153         case V_038000_ARRAY_LINEAR_ALIGNED:
 154         case V_038000_ARRAY_LINEAR_GENERAL:
 155         default:
 156                 b_align = rscreen->tiling_info->group_bytes;
 157                 break;
 158         }
 159         return b_align;
 160 }
 161
 162 static unsigned mip_minify(unsigned size, unsigned level)
 163 {
 164         unsigned val;
 165         val = u_minify(size, level);
 166         if (level > 0)
 167                 val = util_next_power_of_two(val);
 168         return val;
 169 }
 170
 171 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
 172                                           struct r600_resource_texture *rtex,
 173                                           unsigned level)
 174 {
 175         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 176         unsigned nblocksx, block_align, width;
 177         unsigned blocksize = util_format_get_blocksize(ptex->format);
 178
 179         if (rtex->pitch_override)
 180                 return rtex->pitch_override / blocksize;
 181
 182         width = mip_minify(ptex->width0, level);
 183         nblocksx = util_format_get_nblocksx(ptex->format, width);
 184
 185         block_align = r600_get_block_alignment(screen, ptex->format,
 186                                               rtex->array_mode[level]);
 187         nblocksx = align(nblocksx, block_align);
 188         return nblocksx;
 189 }
 190
 191 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 192                                           struct r600_resource_texture *rtex,
 193                                           unsigned level)
 194 {
 195         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 196         unsigned height, tile_height;
 197
 198         height = mip_minify(ptex->height0, level);
 199         height = util_format_get_nblocksy(ptex->format, height);
 200         tile_height = r600_get_height_alignment(screen,
 201                                                 rtex->array_mode[level]);
 202         height = align(height, tile_height);
 203         return height;
 204 }
 205
 206 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 207                                         struct r600_resource_texture *rtex,
 208                                         unsigned level, unsigned array_mode)
 209 {
 210         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 211
 212         switch (array_mode) {
 213         case V_0280A0_ARRAY_LINEAR_GENERAL:
 214         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 215         case V_0280A0_ARRAY_1D_TILED_THIN1:
 216         default:
 217                 rtex->array_mode[level] = array_mode;
 218                 break;
 219         case V_0280A0_ARRAY_2D_TILED_THIN1:
 220         {
 221                 unsigned w, h, tile_height, tile_width;
 222
 223                 tile_height = r600_get_height_alignment(screen, array_mode);
 224                 tile_width = r600_get_block_alignment(screen, ptex->format, array_mode);
 225
 226                 w = mip_minify(ptex->width0, level);
 227                 h = mip_minify(ptex->height0, level);
 228                 if (w <= tile_width || h <= tile_height)
 229                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 230                 else
 231                         rtex->array_mode[level] = array_mode;
 232         }
 233         break;
 234         }
 235 }
 236
 237 static void r600_setup_miptree(struct pipe_screen *screen,
 238                                struct r600_resource_texture *rtex,
 239                                unsigned array_mode)
 240 {
 241         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 242         struct radeon *radeon = (struct radeon *)screen->winsys;
 243         enum chip_class chipc = r600_get_family_class(radeon);
 244         unsigned size, layer_size, i, offset;
 245         unsigned nblocksx, nblocksy, extra_size = 0;
 246
 247         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 248                 unsigned blocksize = util_format_get_blocksize(ptex->format);
 249                 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 250
 251                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 252
 253                 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
 254                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 255
 256                 layer_size = nblocksx * nblocksy * blocksize;
 257                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 258                         if (chipc >= R700)
 259                                 size = layer_size * 8;
 260                         else
 261                                 size = layer_size * 6;
 262                 }
 263                 else if (ptex->target == PIPE_TEXTURE_3D)
 264                         size = layer_size * u_minify(ptex->depth0, i);
 265                 else
 266                         size = layer_size * ptex->array_size;
 267
 268                 /* evergreen stores depth and stencil separately */
 269                 if ((chipc >= EVERGREEN) && util_format_is_depth_or_stencil(ptex->format))
 270                         extra_size = align(extra_size + (nblocksx * nblocksy * 1), base_align);
 271
 272                 /* align base image and start of miptree */
 273                 if ((i == 0) || (i == 1))
 274                         offset = align(offset, base_align);
 275                 rtex->offset[i] = offset;
 276                 rtex->layer_size[i] = layer_size;
 277                 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
 278                 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
 279
 280                 offset += size;
 281         }
 282         rtex->size = offset + extra_size;
 283 }
 284
 285 /* Figure out whether u_blitter will fallback to a transfer operation.
 286  * If so, don't use a staging resource.
 287  */
 288 static boolean permit_hardware_blit(struct pipe_screen *screen,
 289                                         const struct pipe_resource *res)
 290 {
 291         unsigned bind;
 292
 293         if (util_format_is_depth_or_stencil(res->format))
 294                 bind = PIPE_BIND_DEPTH_STENCIL;
 295         else
 296                 bind = PIPE_BIND_RENDER_TARGET;
 297
 298         /* hackaround for S3TC */
 299         if (util_format_is_compressed(res->format))
 300                 return TRUE;
 301
 302         if (!screen->is_format_supported(screen,
 303                                 res->format,
 304                                 res->target,
 305                                 res->nr_samples,
 306                                 bind))
 307                 return FALSE;
 308
 309         if (!screen->is_format_supported(screen,
 310                                 res->format,
 311                                 res->target,
 312                                 res->nr_samples,
 313                                 PIPE_BIND_SAMPLER_VIEW))
 314                 return FALSE;
 315
 316         switch (res->usage) {
 317         case PIPE_USAGE_STREAM:
 318         case PIPE_USAGE_STAGING:
 319                 return FALSE;
 320
 321         default:
 322                 return TRUE;
 323         }
 324 }
 325
 326 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 327                                         struct pipe_resource *ptex,
 328                                         struct winsys_handle *whandle)
 329 {
 330         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 331         struct r600_resource *resource = &rtex->resource;
 332         struct radeon *radeon = (struct radeon *)screen->winsys;
 333
 334         return r600_bo_get_winsys_handle(radeon, resource->bo,
 335                         rtex->pitch_in_bytes[0], whandle);
 336 }
 337
 338 static void r600_texture_destroy(struct pipe_screen *screen,
 339                                  struct pipe_resource *ptex)
 340 {
 341         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 342         struct r600_resource *resource = &rtex->resource;
 343         struct radeon *radeon = (struct radeon *)screen->winsys;
 344
 345         if (rtex->flushed_depth_texture)
 346                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 347
 348         if (resource->bo) {
 349                 r600_bo_reference(radeon, &resource->bo, NULL);
 350         }
 351         FREE(rtex);
 352 }
 353
 354 static const struct u_resource_vtbl r600_texture_vtbl =
 355 {
 356         r600_texture_get_handle,        /* get_handle */
 357         r600_texture_destroy,           /* resource_destroy */
 358         r600_texture_get_transfer,      /* get_transfer */
 359         r600_texture_transfer_destroy,  /* transfer_destroy */
 360         r600_texture_transfer_map,      /* transfer_map */
 361         u_default_transfer_flush_region,/* transfer_flush_region */
 362         r600_texture_transfer_unmap,    /* transfer_unmap */
 363         u_default_transfer_inline_write /* transfer_inline_write */
 364 };
 365
 366 static struct r600_resource_texture *
 367 r600_texture_create_object(struct pipe_screen *screen,
 368                            const struct pipe_resource *base,
 369                            unsigned array_mode,
 370                            unsigned pitch_in_bytes_override,
 371                            unsigned max_buffer_size,
 372                            struct r600_bo *bo)
 373 {
 374         struct r600_resource_texture *rtex;
 375         struct r600_resource *resource;
 376         struct radeon *radeon = (struct radeon *)screen->winsys;
 377
 378         rtex = CALLOC_STRUCT(r600_resource_texture);
 379         if (rtex == NULL)
 380                 return NULL;
 381
 382         resource = &rtex->resource;
 383         resource->b.b.b = *base;
 384         resource->b.b.vtbl = &r600_texture_vtbl;
 385         pipe_reference_init(&resource->b.b.b.reference, 1);
 386         resource->b.b.b.screen = screen;
 387         resource->bo = bo;
 388         rtex->pitch_override = pitch_in_bytes_override;
 389         /* only mark depth textures the HW can hit as depth textures */
 390         if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
 391                 rtex->depth = 1;
 392
 393         r600_setup_miptree(screen, rtex, array_mode);
 394
 395         resource->size = rtex->size;
 396
 397         if (!resource->bo) {
 398                 struct pipe_resource *ptex = &rtex->resource.b.b.b;
 399                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 400
 401                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 402                 if (!resource->bo) {
 403                         FREE(rtex);
 404                         return NULL;
 405                 }
 406         }
 407         return rtex;
 408 }
 409
 410 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 411                                                 const struct pipe_resource *templ)
 412 {
 413         unsigned array_mode = 0;
 414         static int force_tiling = -1;
 415
 416         /* Would like some magic "get_bool_option_once" routine.
 417          */
 418         if (force_tiling == -1) {
 419 #if 0
 420                 /* reenable when 2D tiling is fixed better */
 421                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 422                 if (r600_get_minor_version(rscreen->radeon) >= 9)
 423                         force_tiling = debug_get_bool_option("R600_TILING", TRUE);
 424 #endif
 425                 force_tiling = debug_get_bool_option("R600_TILING", FALSE);
 426         }
 427
 428         if (force_tiling && permit_hardware_blit(screen, templ)) {
 429                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 430                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 431                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 432                 }
 433         }
 434
 435         if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 436             util_format_is_compressed(templ->format))
 437                 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
 438
 439         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 440                                                                   0, 0, NULL);
 441
 442 }
 443
 444 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 445                                                 struct pipe_resource *texture,
 446                                                 const struct pipe_surface *surf_tmpl)
 447 {
 448         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 449         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 450         unsigned level = surf_tmpl->u.tex.level;
 451
 452         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 453         if (surface == NULL)
 454                 return NULL;
 455         /* XXX no offset */
 456 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 457         pipe_reference_init(&surface->base.reference, 1);
 458         pipe_resource_reference(&surface->base.texture, texture);
 459         surface->base.context = pipe;
 460         surface->base.format = surf_tmpl->format;
 461         surface->base.width = mip_minify(texture->width0, level);
 462         surface->base.height = mip_minify(texture->height0, level);
 463         surface->base.usage = surf_tmpl->usage;
 464         surface->base.texture = texture;
 465         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 466         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 467         surface->base.u.tex.level = level;
 468
 469         surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
 470                                                             rtex, level);
 471         return &surface->base;
 472 }
 473
 474 static void r600_surface_destroy(struct pipe_context *pipe,
 475                                  struct pipe_surface *surface)
 476 {
 477         pipe_resource_reference(&surface->texture, NULL);
 478         FREE(surface);
 479 }
 480
 481
 482 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 483                                                const struct pipe_resource *templ,
 484                                                struct winsys_handle *whandle)
 485 {
 486         struct radeon *rw = (struct radeon*)screen->winsys;
 487         struct r600_bo *bo = NULL;
 488         unsigned array_mode = 0;
 489
 490         /* Support only 2D textures without mipmaps */
 491         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 492               templ->depth0 != 1 || templ->last_level != 0)
 493                 return NULL;
 494
 495         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 496         if (bo == NULL) {
 497                 return NULL;
 498         }
 499
 500         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 501                                                                   whandle->stride,
 502                                                                   0,
 503                                                                   bo);
 504 }
 505
 506 int r600_texture_depth_flush(struct pipe_context *ctx,
 507                              struct pipe_resource *texture, boolean just_create)
 508 {
 509         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 510         struct pipe_resource resource;
 511
 512         if (rtex->flushed_depth_texture)
 513                 goto out;
 514
 515         resource.target = PIPE_TEXTURE_2D;
 516         resource.format = texture->format;
 517         resource.width0 = texture->width0;
 518         resource.height0 = texture->height0;
 519         resource.depth0 = 1;
 520         resource.array_size = 1;
 521         resource.last_level = texture->last_level;
 522         resource.nr_samples = 0;
 523         resource.usage = PIPE_USAGE_DYNAMIC;
 524         resource.bind = 0;
 525         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 526
 527         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 528
 529         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 530         if (rtex->flushed_depth_texture == NULL) {
 531                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 532                 return -ENOMEM;
 533         }
 534
 535         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 536 out:
 537         if (just_create)
 538                 return 0;
 539
 540         /* XXX: only do this if the depth texture has actually changed:
 541          */
 542         r600_blit_uncompress_depth(ctx, rtex);
 543         return 0;
 544 }
 545
 546 /* Needs adjustment for pixelformat:
 547  */
 548 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 549 {
 550         return box->width * box->depth * box->height;
 551 };
 552
 553 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 554                                                 struct pipe_resource *texture,
 555                                                 unsigned level,
 556                                                 unsigned usage,
 557                                                 const struct pipe_box *box)
 558 {
 559         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 560         struct pipe_resource resource;
 561         struct r600_transfer *trans;
 562         int r;
 563         boolean use_staging_texture = FALSE;
 564
 565         /* We cannot map a tiled texture directly because the data is
 566          * in a different order, therefore we do detiling using a blit.
 567          *
 568          * Also, use a temporary in GTT memory for read transfers, as
 569          * the CPU is much happier reading out of cached system memory
 570          * than uncached VRAM.
 571          */
 572         if (R600_TEX_IS_TILED(rtex, level))
 573                 use_staging_texture = TRUE;
 574
 575         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 576                 use_staging_texture = TRUE;
 577
 578         /* XXX: Use a staging texture for uploads if the underlying BO
 579          * is busy.  No interface for checking that currently? so do
 580          * it eagerly whenever the transfer doesn't require a readback
 581          * and might block.
 582          */
 583         if ((usage & PIPE_TRANSFER_WRITE) &&
 584                         !(usage & (PIPE_TRANSFER_READ |
 585                                         PIPE_TRANSFER_DONTBLOCK |
 586                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 587                 use_staging_texture = TRUE;
 588
 589         if (!permit_hardware_blit(ctx->screen, texture) ||
 590                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 591                 use_staging_texture = FALSE;
 592
 593         trans = CALLOC_STRUCT(r600_transfer);
 594         if (trans == NULL)
 595                 return NULL;
 596         pipe_resource_reference(&trans->transfer.resource, texture);
 597         trans->transfer.level = level;
 598         trans->transfer.usage = usage;
 599         trans->transfer.box = *box;
 600         if (rtex->depth) {
 601                 /* XXX: only readback the rectangle which is being mapped?
 602                 */
 603                 /* XXX: when discard is true, no need to read back from depth texture
 604                 */
 605                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 606                 if (r < 0) {
 607                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 608                         pipe_resource_reference(&trans->transfer.resource, NULL);
 609                         FREE(trans);
 610                         return NULL;
 611                 }
 612                 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
 613                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 614                 return &trans->transfer;
 615         } else if (use_staging_texture) {
 616                 resource.target = PIPE_TEXTURE_2D;
 617                 resource.format = texture->format;
 618                 resource.width0 = box->width;
 619                 resource.height0 = box->height;
 620                 resource.depth0 = 1;
 621                 resource.array_size = 1;
 622                 resource.last_level = 0;
 623                 resource.nr_samples = 0;
 624                 resource.usage = PIPE_USAGE_STAGING;
 625                 resource.bind = 0;
 626                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 627                 /* For texture reading, the temporary (detiled) texture is used as
 628                  * a render target when blitting from a tiled texture. */
 629                 if (usage & PIPE_TRANSFER_READ) {
 630                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 631                 }
 632                 /* For texture writing, the temporary texture is used as a sampler
 633                  * when blitting into a tiled texture. */
 634                 if (usage & PIPE_TRANSFER_WRITE) {
 635                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 636                 }
 637                 /* Create the temporary texture. */
 638                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 639                 if (trans->staging_texture == NULL) {
 640                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 641                         pipe_resource_reference(&trans->transfer.resource, NULL);
 642                         FREE(trans);
 643                         return NULL;
 644                 }
 645
 646                 trans->transfer.stride =
 647                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 648                 if (usage & PIPE_TRANSFER_READ) {
 649                         r600_copy_to_staging_texture(ctx, trans);
 650                         /* Always referenced in the blit. */
 651                         ctx->flush(ctx, NULL);
 652                 }
 653                 return &trans->transfer;
 654         }
 655         trans->transfer.stride = rtex->pitch_in_bytes[level];
 656         trans->transfer.layer_stride = rtex->layer_size[level];
 657         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 658         return &trans->transfer;
 659 }
 660
 661 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 662                                    struct pipe_transfer *transfer)
 663 {
 664         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 665         struct pipe_resource *texture = transfer->resource;
 666         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 667
 668         if (rtransfer->staging_texture) {
 669                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 670                         r600_copy_from_staging_texture(ctx, rtransfer);
 671                 }
 672                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 673         }
 674
 675         if (rtex->depth && !rtex->is_flushing_texture) {
 676                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 677                         r600_blit_push_depth(ctx, rtex);
 678         }
 679
 680         pipe_resource_reference(&transfer->resource, NULL);
 681         FREE(transfer);
 682 }
 683
 684 void* r600_texture_transfer_map(struct pipe_context *ctx,
 685                                 struct pipe_transfer* transfer)
 686 {
 687         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 688         struct r600_bo *bo;
 689         enum pipe_format format = transfer->resource->format;
 690         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 691         unsigned offset = 0;
 692         unsigned usage = 0;
 693         char *map;
 694
 695         if (rtransfer->staging_texture) {
 696                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 697         } else {
 698                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 699
 700                 if (rtex->flushed_depth_texture)
 701                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 702                 else
 703                         bo = ((struct r600_resource *)transfer->resource)->bo;
 704
 705                 offset = rtransfer->offset +
 706                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 707                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 708         }
 709
 710         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 711                 usage |= PB_USAGE_CPU_WRITE;
 712
 713                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 714                 }
 715
 716                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 717                 }
 718         }
 719
 720         if (transfer->usage & PIPE_TRANSFER_READ) {
 721                 usage |= PB_USAGE_CPU_READ;
 722         }
 723
 724         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 725                 usage |= PB_USAGE_DONTBLOCK;
 726         }
 727
 728         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 729                 usage |= PB_USAGE_UNSYNCHRONIZED;
 730         }
 731
 732         map = r600_bo_map(radeon, bo, usage, ctx);
 733         if (!map) {
 734                 return NULL;
 735         }
 736
 737         return map + offset;
 738 }
 739
 740 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 741                                  struct pipe_transfer* transfer)
 742 {
 743         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 744         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 745         struct r600_bo *bo;
 746
 747         if (rtransfer->staging_texture) {
 748                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 749         } else {
 750                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 751
 752                 if (rtex->flushed_depth_texture) {
 753                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 754                 } else {
 755                         bo = ((struct r600_resource *)transfer->resource)->bo;
 756                 }
 757         }
 758         r600_bo_unmap(radeon, bo);
 759 }
 760
 761 void r600_init_surface_functions(struct r600_pipe_context *r600)
 762 {
 763         r600->context.create_surface = r600_create_surface;
 764         r600->context.surface_destroy = r600_surface_destroy;
 765 }
 766
 767 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 768                 const unsigned char *swizzle_view)
 769 {
 770         unsigned i;
 771         unsigned char swizzle[4];
 772         unsigned result = 0;
 773         const uint32_t swizzle_shift[4] = {
 774                 16, 19, 22, 25,
 775         };
 776         const uint32_t swizzle_bit[4] = {
 777                 0, 1, 2, 3,
 778         };
 779
 780         if (swizzle_view) {
 781                 /* Combine two sets of swizzles. */
 782                 for (i = 0; i < 4; i++) {
 783                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 784                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 785                 }
 786         } else {
 787                 memcpy(swizzle, swizzle_format, 4);
 788         }
 789
 790         /* Get swizzle. */
 791         for (i = 0; i < 4; i++) {
 792                 switch (swizzle[i]) {
 793                 case UTIL_FORMAT_SWIZZLE_Y:
 794                         result |= swizzle_bit[1] << swizzle_shift[i];
 795                         break;
 796                 case UTIL_FORMAT_SWIZZLE_Z:
 797                         result |= swizzle_bit[2] << swizzle_shift[i];
 798                         break;
 799                 case UTIL_FORMAT_SWIZZLE_W:
 800                         result |= swizzle_bit[3] << swizzle_shift[i];
 801                         break;
 802                 case UTIL_FORMAT_SWIZZLE_0:
 803                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 804                         break;
 805                 case UTIL_FORMAT_SWIZZLE_1:
 806                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 807                         break;
 808                 default: /* UTIL_FORMAT_SWIZZLE_X */
 809                         result |= swizzle_bit[0] << swizzle_shift[i];
 810                 }
 811         }
 812         return result;
 813 }
 814
 815 /* texture format translate */
 816 uint32_t r600_translate_texformat(struct pipe_screen *screen,
 817                                   enum pipe_format format,
 818                                   const unsigned char *swizzle_view,
 819                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 820 {
 821         uint32_t result = 0, word4 = 0, yuv_format = 0;
 822         const struct util_format_description *desc;
 823         boolean uniform = TRUE;
 824         static int r600_enable_s3tc = -1;
 825
 826         int i;
 827         const uint32_t sign_bit[4] = {
 828                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 829                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 830                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 831                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 832         };
 833         desc = util_format_description(format);
 834
 835         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 836
 837         /* Colorspace (return non-RGB formats directly). */
 838         switch (desc->colorspace) {
 839                 /* Depth stencil formats */
 840         case UTIL_FORMAT_COLORSPACE_ZS:
 841                 switch (format) {
 842                 case PIPE_FORMAT_Z16_UNORM:
 843                         result = FMT_16;
 844                         goto out_word4;
 845                 case PIPE_FORMAT_X24S8_USCALED:
 846                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 847                 case PIPE_FORMAT_Z24X8_UNORM:
 848                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 849                         result = FMT_8_24;
 850                         goto out_word4;
 851                 case PIPE_FORMAT_S8X24_USCALED:
 852                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 853                 case PIPE_FORMAT_X8Z24_UNORM:
 854                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 855                         result = FMT_24_8;
 856                         goto out_word4;
 857                 case PIPE_FORMAT_S8_USCALED:
 858                         result = FMT_8;
 859                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 860                         goto out_word4;
 861                 case PIPE_FORMAT_Z32_FLOAT:
 862                         result = FMT_32_FLOAT;
 863                         goto out_word4;
 864                 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
 865                         result = FMT_X24_8_32_FLOAT;
 866                         goto out_word4;
 867                 default:
 868                         goto out_unknown;
 869                 }
 870
 871         case UTIL_FORMAT_COLORSPACE_YUV:
 872                 yuv_format |= (1 << 30);
 873                 switch (format) {
 874                 case PIPE_FORMAT_UYVY:
 875                 case PIPE_FORMAT_YUYV:
 876                 default:
 877                         break;
 878                 }
 879                 goto out_unknown; /* TODO */
 880
 881         case UTIL_FORMAT_COLORSPACE_SRGB:
 882                 word4 |= S_038010_FORCE_DEGAMMA(1);
 883                 break;
 884
 885         default:
 886                 break;
 887         }
 888
 889         if (r600_enable_s3tc == -1) {
 890                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 891                 if (r600_get_minor_version(rscreen->radeon) >= 9)
 892                         r600_enable_s3tc = 1;
 893                 else
 894                         r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 895         }
 896
 897         if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 898                 if (!r600_enable_s3tc)
 899                         goto out_unknown;
 900
 901                 switch (format) {
 902                 case PIPE_FORMAT_RGTC1_SNORM:
 903                 case PIPE_FORMAT_LATC1_SNORM:
 904                         word4 |= sign_bit[0];
 905                 case PIPE_FORMAT_RGTC1_UNORM:
 906                 case PIPE_FORMAT_LATC1_UNORM:
 907                         result = FMT_BC4;
 908                         goto out_word4;
 909                 case PIPE_FORMAT_RGTC2_SNORM:
 910                 case PIPE_FORMAT_LATC2_SNORM:
 911                         word4 |= sign_bit[0] | sign_bit[1];
 912                 case PIPE_FORMAT_RGTC2_UNORM:
 913                 case PIPE_FORMAT_LATC2_UNORM:
 914                         result = FMT_BC5;
 915                         goto out_word4;
 916                 default:
 917                         goto out_unknown;
 918                 }
 919         }
 920
 921         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 922
 923                 if (!r600_enable_s3tc)
 924                         goto out_unknown;
 925
 926                 if (!util_format_s3tc_enabled) {
 927                         goto out_unknown;
 928                 }
 929
 930                 switch (format) {
 931                 case PIPE_FORMAT_DXT1_RGB:
 932                 case PIPE_FORMAT_DXT1_RGBA:
 933                 case PIPE_FORMAT_DXT1_SRGB:
 934                 case PIPE_FORMAT_DXT1_SRGBA:
 935                         result = FMT_BC1;
 936                         goto out_word4;
 937                 case PIPE_FORMAT_DXT3_RGBA:
 938                 case PIPE_FORMAT_DXT3_SRGBA:
 939                         result = FMT_BC2;
 940                         goto out_word4;
 941                 case PIPE_FORMAT_DXT5_RGBA:
 942                 case PIPE_FORMAT_DXT5_SRGBA:
 943                         result = FMT_BC3;
 944                         goto out_word4;
 945                 default:
 946                         goto out_unknown;
 947                 }
 948         }
 949
 950         if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
 951                 result = FMT_5_9_9_9_SHAREDEXP;
 952                 goto out_word4;
 953         } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 954                 result = FMT_10_11_11_FLOAT;
 955                 goto out_word4;
 956         }
 957
 958
 959         for (i = 0; i < desc->nr_channels; i++) {
 960                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 961                         word4 |= sign_bit[i];
 962                 }
 963         }
 964
 965         /* R8G8Bx_SNORM - TODO CxV8U8 */
 966
 967         /* See whether the components are of the same size. */
 968         for (i = 1; i < desc->nr_channels; i++) {
 969                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 970         }
 971
 972         /* Non-uniform formats. */
 973         if (!uniform) {
 974                 switch(desc->nr_channels) {
 975                 case 3:
 976                         if (desc->channel[0].size == 5 &&
 977                             desc->channel[1].size == 6 &&
 978                             desc->channel[2].size == 5) {
 979                                 result = FMT_5_6_5;
 980                                 goto out_word4;
 981                         }
 982                         goto out_unknown;
 983                 case 4:
 984                         if (desc->channel[0].size == 5 &&
 985                             desc->channel[1].size == 5 &&
 986                             desc->channel[2].size == 5 &&
 987                             desc->channel[3].size == 1) {
 988                                 result = FMT_1_5_5_5;
 989                                 goto out_word4;
 990                         }
 991                         if (desc->channel[0].size == 10 &&
 992                             desc->channel[1].size == 10 &&
 993                             desc->channel[2].size == 10 &&
 994                             desc->channel[3].size == 2) {
 995                                 result = FMT_2_10_10_10;
 996                                 goto out_word4;
 997                         }
 998                         goto out_unknown;
 999                 }
1000                 goto out_unknown;
1001         }
1002
1003         /* Find the first non-VOID channel. */
1004         for (i = 0; i < 4; i++) {
1005                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1006                         break;
1007                 }
1008         }
1009
1010         if (i == 4)
1011                 goto out_unknown;
1012
1013         /* uniform formats */
1014         switch (desc->channel[i].type) {
1015         case UTIL_FORMAT_TYPE_UNSIGNED:
1016         case UTIL_FORMAT_TYPE_SIGNED:
1017                 if (!desc->channel[i].normalized &&
1018                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1019                         goto out_unknown;
1020                 }
1021
1022                 switch (desc->channel[i].size) {
1023                 case 4:
1024                         switch (desc->nr_channels) {
1025                         case 2:
1026                                 result = FMT_4_4;
1027                                 goto out_word4;
1028                         case 4:
1029                                 result = FMT_4_4_4_4;
1030                                 goto out_word4;
1031                         }
1032                         goto out_unknown;
1033                 case 8:
1034                         switch (desc->nr_channels) {
1035                         case 1:
1036                                 result = FMT_8;
1037                                 goto out_word4;
1038                         case 2:
1039                                 result = FMT_8_8;
1040                                 goto out_word4;
1041                         case 4:
1042                                 result = FMT_8_8_8_8;
1043                                 goto out_word4;
1044                         }
1045                         goto out_unknown;
1046                 case 16:
1047                         switch (desc->nr_channels) {
1048                         case 1:
1049                                 result = FMT_16;
1050                                 goto out_word4;
1051                         case 2:
1052                                 result = FMT_16_16;
1053                                 goto out_word4;
1054                         case 4:
1055                                 result = FMT_16_16_16_16;
1056                                 goto out_word4;
1057                         }
1058                         goto out_unknown;
1059                 case 32:
1060                         switch (desc->nr_channels) {
1061                         case 1:
1062                                 result = FMT_32;
1063                                 goto out_word4;
1064                         case 2:
1065                                 result = FMT_32_32;
1066                                 goto out_word4;
1067                         case 4:
1068                                 result = FMT_32_32_32_32;
1069                                 goto out_word4;
1070                         }
1071                 }
1072                 goto out_unknown;
1073
1074         case UTIL_FORMAT_TYPE_FLOAT:
1075                 switch (desc->channel[i].size) {
1076                 case 16:
1077                         switch (desc->nr_channels) {
1078                         case 1:
1079                                 result = FMT_16_FLOAT;
1080                                 goto out_word4;
1081                         case 2:
1082                                 result = FMT_16_16_FLOAT;
1083                                 goto out_word4;
1084                         case 4:
1085                                 result = FMT_16_16_16_16_FLOAT;
1086                                 goto out_word4;
1087                         }
1088                         goto out_unknown;
1089                 case 32:
1090                         switch (desc->nr_channels) {
1091                         case 1:
1092                                 result = FMT_32_FLOAT;
1093                                 goto out_word4;
1094                         case 2:
1095                                 result = FMT_32_32_FLOAT;
1096                                 goto out_word4;
1097                         case 4:
1098                                 result = FMT_32_32_32_32_FLOAT;
1099                                 goto out_word4;
1100                         }
1101                 }
1102                 goto out_unknown;
1103         }
1104
1105 out_word4:
1106         if (word4_p)
1107                 *word4_p = word4;
1108         if (yuv_format_p)
1109                 *yuv_format_p = yuv_format;
1110         return result;
1111 out_unknown:
1112         /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1113         return ~0;
1114 }