2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_formats.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
35 /* Copy from a full GPU texture to a transfer's staging one. */
36 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
38 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
39 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
40 struct pipe_resource
*src
= transfer
->resource
;
42 if (src
->nr_samples
<= 1) {
43 ctx
->resource_copy_region(ctx
, dst
, 0, 0, 0, 0,
44 src
, transfer
->level
, &transfer
->box
);
46 /* Resolve the resource. */
47 struct pipe_blit_info blit
;
49 memset(&blit
, 0, sizeof(blit
));
50 blit
.src
.resource
= src
;
51 blit
.src
.format
= src
->format
;
52 blit
.src
.level
= transfer
->level
;
53 blit
.src
.box
= transfer
->box
;
54 blit
.dst
.resource
= dst
;
55 blit
.dst
.format
= dst
->format
;
56 blit
.dst
.box
.width
= transfer
->box
.width
;
57 blit
.dst
.box
.height
= transfer
->box
.height
;
58 blit
.dst
.box
.depth
= transfer
->box
.depth
;
59 blit
.mask
= PIPE_MASK_RGBA
;
60 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
62 ctx
->blit(ctx
, &blit
);
66 /* Copy from a transfer's staging texture to a full GPU one. */
67 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
69 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
70 struct pipe_resource
*texture
= transfer
->resource
;
73 u_box_origin_2d(transfer
->box
.width
, transfer
->box
.height
, &sbox
);
75 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
76 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
77 &rtransfer
->staging
->b
.b
,
81 unsigned r600_texture_get_offset(struct r600_texture
*rtex
,
82 unsigned level
, unsigned layer
)
84 return rtex
->surface
.level
[level
].offset
+
85 layer
* rtex
->surface
.level
[level
].slice_size
;
88 static int r600_init_surface(struct r600_screen
*rscreen
,
89 struct radeon_surface
*surface
,
90 const struct pipe_resource
*ptex
,
92 bool is_flushed_depth
)
94 const struct util_format_description
*desc
=
95 util_format_description(ptex
->format
);
96 bool is_depth
, is_stencil
;
98 is_depth
= util_format_has_depth(desc
);
99 is_stencil
= util_format_has_stencil(desc
);
101 surface
->npix_x
= ptex
->width0
;
102 surface
->npix_y
= ptex
->height0
;
103 surface
->npix_z
= ptex
->depth0
;
104 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
105 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
107 surface
->array_size
= 1;
108 surface
->last_level
= ptex
->last_level
;
110 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
111 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
112 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
114 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
115 /* align byte per element on dword */
116 if (surface
->bpe
== 3) {
121 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
124 switch (array_mode
) {
125 case V_038000_ARRAY_1D_TILED_THIN1
:
126 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
128 case V_038000_ARRAY_2D_TILED_THIN1
:
129 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
131 case V_038000_ARRAY_LINEAR_ALIGNED
:
132 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
134 case V_038000_ARRAY_LINEAR_GENERAL
:
136 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR
, MODE
);
139 switch (ptex
->target
) {
140 case PIPE_TEXTURE_1D
:
141 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
143 case PIPE_TEXTURE_RECT
:
144 case PIPE_TEXTURE_2D
:
145 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
147 case PIPE_TEXTURE_3D
:
148 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
150 case PIPE_TEXTURE_1D_ARRAY
:
151 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
152 surface
->array_size
= ptex
->array_size
;
154 case PIPE_TEXTURE_2D_ARRAY
:
155 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d layout for now */
156 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
157 surface
->array_size
= ptex
->array_size
;
159 case PIPE_TEXTURE_CUBE
:
160 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
166 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
167 surface
->flags
|= RADEON_SURF_SCANOUT
;
170 if (!is_flushed_depth
&& is_depth
) {
171 surface
->flags
|= RADEON_SURF_ZBUFFER
;
174 surface
->flags
|= RADEON_SURF_SBUFFER
|
175 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
181 static int r600_setup_surface(struct pipe_screen
*screen
,
182 struct r600_texture
*rtex
,
183 unsigned pitch_in_bytes_override
)
185 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
186 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
190 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
194 rtex
->size
= rtex
->surface
.bo_size
;
195 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
196 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
199 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
200 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
201 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
202 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
203 rtex
->surface
.stencil_offset
=
204 rtex
->surface
.stencil_level
[0].offset
= rtex
->surface
.level
[0].slice_size
;
207 for (i
= 0; i
<= ptex
->last_level
; i
++) {
208 switch (rtex
->surface
.level
[i
].mode
) {
209 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
210 rtex
->array_mode
[i
] = V_038000_ARRAY_LINEAR_ALIGNED
;
212 case RADEON_SURF_MODE_1D
:
213 rtex
->array_mode
[i
] = V_038000_ARRAY_1D_TILED_THIN1
;
215 case RADEON_SURF_MODE_2D
:
216 rtex
->array_mode
[i
] = V_038000_ARRAY_2D_TILED_THIN1
;
219 case RADEON_SURF_MODE_LINEAR
:
220 rtex
->array_mode
[i
] = 0;
227 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
228 struct pipe_resource
*ptex
,
229 struct winsys_handle
*whandle
)
231 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
232 struct r600_resource
*resource
= &rtex
->resource
;
233 struct radeon_surface
*surface
= &rtex
->surface
;
234 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
236 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
238 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
239 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
240 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
241 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
242 surface
->bankw
, surface
->bankh
,
244 surface
->stencil_tile_split
,
246 rtex
->surface
.level
[0].pitch_bytes
);
248 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
249 rtex
->surface
.level
[0].pitch_bytes
, whandle
);
252 static void r600_texture_destroy(struct pipe_screen
*screen
,
253 struct pipe_resource
*ptex
)
255 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
256 struct r600_resource
*resource
= &rtex
->resource
;
258 if (rtex
->flushed_depth_texture
)
259 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
261 pb_reference(&resource
->buf
, NULL
);
265 static const struct u_resource_vtbl r600_texture_vtbl
;
267 /* The number of samples can be specified independently of the texture. */
268 void r600_texture_get_fmask_info(struct r600_screen
*rscreen
,
269 struct r600_texture
*rtex
,
271 struct r600_fmask_info
*out
)
273 /* FMASK is allocated pretty much like an ordinary texture.
274 * Here we use bpe in the units of bits, not bytes. */
275 struct radeon_surface fmask
= rtex
->surface
;
277 switch (nr_samples
) {
279 /* This should be 8,1, but we should set nsamples > 1
280 * for the allocator to treat it as a multisample surface.
281 * Let's set 4,2 then. */
295 R600_ERR("Invalid sample count for FMASK allocation.\n");
299 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
300 if (rscreen
->chip_class
<= R700
) {
304 if (rscreen
->chip_class
>= EVERGREEN
) {
305 fmask
.bankh
= nr_samples
<= 4 ? 4 : 1;
308 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
309 R600_ERR("Got error in surface_init while allocating FMASK.\n");
312 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
314 out
->bank_height
= fmask
.bankh
;
315 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
316 out
->size
= (fmask
.bo_size
+ 7) / 8;
319 static void r600_texture_allocate_fmask(struct r600_screen
*rscreen
,
320 struct r600_texture
*rtex
)
322 struct r600_fmask_info fmask
;
324 r600_texture_get_fmask_info(rscreen
, rtex
,
325 rtex
->resource
.b
.b
.nr_samples
, &fmask
);
327 /* Reserve space for FMASK while converting bits back to bytes. */
328 rtex
->fmask_bank_height
= fmask
.bank_height
;
329 rtex
->fmask_offset
= align(rtex
->size
, fmask
.alignment
);
330 rtex
->fmask_size
= fmask
.size
;
331 rtex
->size
= rtex
->fmask_offset
+ rtex
->fmask_size
;
333 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
334 fmask
.npix_x
, fmask
.npix_y
, fmask
.bpe
* fmask
.nsamples
, rtex
->fmask_size
);
338 void r600_texture_get_cmask_info(struct r600_screen
*rscreen
,
339 struct r600_texture
*rtex
,
340 struct r600_cmask_info
*out
)
342 unsigned cmask_tile_width
= 8;
343 unsigned cmask_tile_height
= 8;
344 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
345 unsigned element_bits
= 4;
346 unsigned cmask_cache_bits
= 1024;
347 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
348 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
350 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
351 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
352 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
353 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
354 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
356 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
357 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
359 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
360 unsigned slice_bytes
=
361 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
363 assert(macro_tile_width
% 128 == 0);
364 assert(macro_tile_height
% 128 == 0);
366 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
367 out
->alignment
= MAX2(256, base_align
);
368 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
371 static void r600_texture_allocate_cmask(struct r600_screen
*rscreen
,
372 struct r600_texture
*rtex
)
374 struct r600_cmask_info cmask
;
376 r600_texture_get_cmask_info(rscreen
, rtex
, &cmask
);
378 rtex
->cmask_slice_tile_max
= cmask
.slice_tile_max
;
379 rtex
->cmask_offset
= align(rtex
->size
, cmask
.alignment
);
380 rtex
->cmask_size
= cmask
.size
;
381 rtex
->size
= rtex
->cmask_offset
+ rtex
->cmask_size
;
383 printf("CMASK: macro tile width = %u, macro tile height = %u, "
384 "pitch elements = %u, height = %u, slice tile max = %u\n",
385 macro_tile_width
, macro_tile_height
, pitch_elements
, height
,
386 rtex
->cmask_slice_tile_max
);
390 DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth
, "R600_PRINT_TEXDEPTH", FALSE
);
392 static struct r600_texture
*
393 r600_texture_create_object(struct pipe_screen
*screen
,
394 const struct pipe_resource
*base
,
395 unsigned pitch_in_bytes_override
,
396 struct pb_buffer
*buf
,
398 struct radeon_surface
*surface
)
400 struct r600_texture
*rtex
;
401 struct r600_resource
*resource
;
402 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
405 rtex
= CALLOC_STRUCT(r600_texture
);
409 resource
= &rtex
->resource
;
410 resource
->b
.b
= *base
;
411 resource
->b
.vtbl
= &r600_texture_vtbl
;
412 pipe_reference_init(&resource
->b
.b
.reference
, 1);
413 resource
->b
.b
.screen
= screen
;
414 rtex
->pitch_override
= pitch_in_bytes_override
;
416 /* don't include stencil-only formats which we don't support for rendering */
417 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
419 rtex
->surface
= *surface
;
420 r
= r600_setup_surface(screen
, rtex
,
421 pitch_in_bytes_override
);
427 if (base
->nr_samples
> 1 && !rtex
->is_depth
&& alloc_bo
) {
428 r600_texture_allocate_cmask(rscreen
, rtex
);
429 r600_texture_allocate_fmask(rscreen
, rtex
);
432 if (!rtex
->is_depth
&& base
->nr_samples
> 1 &&
433 (!rtex
->fmask_size
|| !rtex
->cmask_size
)) {
438 /* Tiled depth textures utilize the non-displayable tile order. */
439 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
441 /* Now create the backing buffer. */
442 if (!buf
&& alloc_bo
) {
443 unsigned base_align
= rtex
->surface
.bo_alignment
;
444 unsigned usage
= R600_TEX_IS_TILED(rtex
, 0) ? PIPE_USAGE_STATIC
: base
->usage
;
446 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, base
->bind
, usage
)) {
451 /* This is usually the window framebuffer. We want it in VRAM, always. */
453 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
454 resource
->domains
= RADEON_DOMAIN_VRAM
;
457 if (rtex
->cmask_size
) {
458 /* Initialize the cmask to 0xCC (= compressed state). */
459 char *ptr
= rscreen
->ws
->buffer_map(resource
->cs_buf
, NULL
, PIPE_TRANSFER_WRITE
);
460 memset(ptr
+ rtex
->cmask_offset
, 0xCC, rtex
->cmask_size
);
461 rscreen
->ws
->buffer_unmap(resource
->cs_buf
);
464 if (debug_get_option_print_texdepth() && rtex
->is_depth
&& rtex
->non_disp_tiling
) {
465 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
466 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
467 "bpe=%u, nsamples=%u, flags=%u\n",
468 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
469 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
470 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
471 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
472 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
473 rtex
->surface
.flags
);
474 if (rtex
->surface
.flags
& RADEON_SURF_ZBUFFER
) {
475 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
476 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
477 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
478 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
479 i
, (unsigned long long)rtex
->surface
.level
[i
].offset
,
480 (unsigned long long)rtex
->surface
.level
[i
].slice_size
,
481 rtex
->surface
.level
[i
].npix_x
,
482 rtex
->surface
.level
[i
].npix_y
,
483 rtex
->surface
.level
[i
].npix_z
,
484 rtex
->surface
.level
[i
].nblk_x
,
485 rtex
->surface
.level
[i
].nblk_y
,
486 rtex
->surface
.level
[i
].nblk_z
,
487 rtex
->surface
.level
[i
].pitch_bytes
,
488 rtex
->surface
.level
[i
].mode
);
491 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
492 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
493 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
494 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
495 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
496 i
, (unsigned long long)rtex
->surface
.stencil_level
[i
].offset
,
497 (unsigned long long)rtex
->surface
.stencil_level
[i
].slice_size
,
498 rtex
->surface
.stencil_level
[i
].npix_x
,
499 rtex
->surface
.stencil_level
[i
].npix_y
,
500 rtex
->surface
.stencil_level
[i
].npix_z
,
501 rtex
->surface
.stencil_level
[i
].nblk_x
,
502 rtex
->surface
.stencil_level
[i
].nblk_y
,
503 rtex
->surface
.stencil_level
[i
].nblk_z
,
504 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
505 rtex
->surface
.stencil_level
[i
].mode
);
512 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
513 const struct pipe_resource
*templ
)
515 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
516 struct radeon_surface surface
;
517 const struct util_format_description
*desc
= util_format_description(templ
->format
);
521 /* Default tiling mode for staging textures. */
522 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
524 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
525 * because 422 formats are used for videos, which prefer linear buffers
526 * for fast uploads anyway. */
527 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
528 desc
->layout
!= UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
529 if (!(templ
->bind
& PIPE_BIND_SCANOUT
) &&
530 templ
->usage
!= PIPE_USAGE_STAGING
&&
531 templ
->usage
!= PIPE_USAGE_STREAM
&&
532 templ
->target
!= PIPE_TEXTURE_1D
&&
533 templ
->target
!= PIPE_TEXTURE_1D_ARRAY
&&
534 templ
->height0
> 3) {
535 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
536 } else if (util_format_is_compressed(templ
->format
)) {
537 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
541 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
,
542 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
546 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
550 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
551 0, NULL
, TRUE
, &surface
);
554 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
555 struct pipe_resource
*texture
,
556 const struct pipe_surface
*templ
,
557 unsigned width
, unsigned height
)
559 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
561 assert(templ
->u
.tex
.first_layer
== templ
->u
.tex
.last_layer
);
564 pipe_reference_init(&surface
->base
.reference
, 1);
565 pipe_resource_reference(&surface
->base
.texture
, texture
);
566 surface
->base
.context
= pipe
;
567 surface
->base
.format
= templ
->format
;
568 surface
->base
.width
= width
;
569 surface
->base
.height
= height
;
570 surface
->base
.u
= templ
->u
;
571 return &surface
->base
;
574 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
575 struct pipe_resource
*texture
,
576 const struct pipe_surface
*templ
)
578 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
579 unsigned level
= templ
->u
.tex
.level
;
581 return r600_create_surface_custom(pipe
, texture
, templ
,
582 rtex
->surface
.level
[level
].npix_x
,
583 rtex
->surface
.level
[level
].npix_y
);
586 static void r600_surface_destroy(struct pipe_context
*pipe
,
587 struct pipe_surface
*surface
)
589 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
590 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
, NULL
);
591 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
, NULL
);
592 pipe_resource_reference(&surface
->texture
, NULL
);
596 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
597 const struct pipe_resource
*templ
,
598 struct winsys_handle
*whandle
)
600 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
601 struct pb_buffer
*buf
= NULL
;
603 unsigned array_mode
= 0;
604 enum radeon_bo_layout micro
, macro
;
605 struct radeon_surface surface
;
608 /* Support only 2D textures without mipmaps */
609 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
610 templ
->depth0
!= 1 || templ
->last_level
!= 0)
613 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
617 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
618 &surface
.bankw
, &surface
.bankh
,
620 &surface
.stencil_tile_split
,
623 if (macro
== RADEON_LAYOUT_TILED
)
624 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
625 else if (micro
== RADEON_LAYOUT_TILED
)
626 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
628 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
630 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
634 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
635 stride
, buf
, FALSE
, &surface
);
638 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
639 struct pipe_resource
*texture
,
640 struct r600_texture
**staging
)
642 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
643 struct pipe_resource resource
;
644 struct r600_texture
**flushed_depth_texture
= staging
?
645 staging
: &rtex
->flushed_depth_texture
;
647 if (!staging
&& rtex
->flushed_depth_texture
)
648 return true; /* it's ready */
650 resource
.target
= texture
->target
;
651 resource
.format
= texture
->format
;
652 resource
.width0
= texture
->width0
;
653 resource
.height0
= texture
->height0
;
654 resource
.depth0
= texture
->depth0
;
655 resource
.array_size
= texture
->array_size
;
656 resource
.last_level
= texture
->last_level
;
657 resource
.nr_samples
= texture
->nr_samples
;
658 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_STATIC
;
659 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
660 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
663 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
665 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
666 if (*flushed_depth_texture
== NULL
) {
667 R600_ERR("failed to create temporary texture to hold flushed depth\n");
671 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
672 (*flushed_depth_texture
)->non_disp_tiling
= false;
676 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
677 struct pipe_resource
*texture
,
680 const struct pipe_box
*box
,
681 struct pipe_transfer
**ptransfer
)
683 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
684 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
685 struct pipe_resource resource
;
686 struct r600_transfer
*trans
;
687 boolean use_staging_texture
= FALSE
;
688 enum pipe_format format
= texture
->format
;
689 struct radeon_winsys_cs_handle
*buf
;
693 if ((texture
->bind
& PIPE_BIND_GLOBAL
) && texture
->target
== PIPE_BUFFER
) {
694 return r600_compute_global_transfer_map(ctx
, texture
, level
, usage
, box
, ptransfer
);
697 /* We cannot map a tiled texture directly because the data is
698 * in a different order, therefore we do detiling using a blit.
700 * Also, use a temporary in GTT memory for read transfers, as
701 * the CPU is much happier reading out of cached system memory
702 * than uncached VRAM.
704 if (R600_TEX_IS_TILED(rtex
, level
)) {
705 use_staging_texture
= TRUE
;
708 /* Use a staging texture for uploads if the underlying BO is busy. */
709 if (!(usage
& PIPE_TRANSFER_READ
) &&
710 (rctx
->ws
->cs_is_buffer_referenced(rctx
->cs
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
711 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
))) {
712 use_staging_texture
= TRUE
;
715 if (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
) {
716 use_staging_texture
= FALSE
;
719 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
723 trans
= CALLOC_STRUCT(r600_transfer
);
726 trans
->transfer
.resource
= texture
;
727 trans
->transfer
.level
= level
;
728 trans
->transfer
.usage
= usage
;
729 trans
->transfer
.box
= *box
;
730 if (rtex
->is_depth
) {
731 /* XXX: only readback the rectangle which is being mapped?
733 /* XXX: when discard is true, no need to read back from depth texture
735 struct r600_texture
*staging_depth
;
737 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
738 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
739 R600_ERR("mapping MSAA zbuffer unimplemented\n");
744 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
745 R600_ERR("failed to create temporary texture to hold untiled copy\n");
750 r600_blit_decompress_depth(ctx
, rtex
, staging_depth
,
752 box
->z
, box
->z
+ box
->depth
- 1,
755 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
756 trans
->offset
= r600_texture_get_offset(staging_depth
, level
, box
->z
);
757 trans
->staging
= (struct r600_resource
*)staging_depth
;
758 } else if (use_staging_texture
) {
759 resource
.target
= PIPE_TEXTURE_2D
;
760 resource
.format
= texture
->format
;
761 resource
.width0
= box
->width
;
762 resource
.height0
= box
->height
;
764 resource
.array_size
= 1;
765 resource
.last_level
= 0;
766 resource
.nr_samples
= 0;
767 resource
.usage
= PIPE_USAGE_STAGING
;
769 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
770 /* For texture reading, the temporary (detiled) texture is used as
771 * a render target when blitting from a tiled texture. */
772 if (usage
& PIPE_TRANSFER_READ
) {
773 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
775 /* For texture writing, the temporary texture is used as a sampler
776 * when blitting into a tiled texture. */
777 if (usage
& PIPE_TRANSFER_WRITE
) {
778 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
780 /* Create the temporary texture. */
781 trans
->staging
= (struct r600_resource
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
782 if (trans
->staging
== NULL
) {
783 R600_ERR("failed to create temporary texture to hold untiled copy\n");
788 trans
->transfer
.stride
=
789 ((struct r600_texture
*)trans
->staging
)->surface
.level
[0].pitch_bytes
;
790 if (usage
& PIPE_TRANSFER_READ
) {
791 r600_copy_to_staging_texture(ctx
, trans
);
792 /* Always referenced in the blit. */
793 r600_flush(ctx
, NULL
, 0);
796 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
797 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
798 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
801 if (trans
->staging
) {
802 buf
= ((struct r600_resource
*)trans
->staging
)->cs_buf
;
804 buf
= ((struct r600_resource
*)texture
)->cs_buf
;
807 if (rtex
->is_depth
|| !trans
->staging
)
808 offset
= trans
->offset
+
809 box
->y
/ util_format_get_blockheight(format
) * trans
->transfer
.stride
+
810 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
812 if (!(map
= rctx
->ws
->buffer_map(buf
, rctx
->cs
, usage
))) {
813 pipe_resource_reference((struct pipe_resource
**)&trans
->staging
, NULL
);
818 *ptransfer
= &trans
->transfer
;
822 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
823 struct pipe_transfer
* transfer
)
825 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
826 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
827 struct radeon_winsys_cs_handle
*buf
;
828 struct pipe_resource
*texture
= transfer
->resource
;
829 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
831 if ((transfer
->resource
->bind
& PIPE_BIND_GLOBAL
) && transfer
->resource
->target
== PIPE_BUFFER
) {
832 return r600_compute_global_transfer_unmap(ctx
, transfer
);
835 if (rtransfer
->staging
) {
836 buf
= ((struct r600_resource
*)rtransfer
->staging
)->cs_buf
;
838 buf
= ((struct r600_resource
*)transfer
->resource
)->cs_buf
;
840 rctx
->ws
->buffer_unmap(buf
);
842 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
843 if (rtex
->is_depth
) {
844 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
845 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
846 &rtransfer
->staging
->b
.b
, transfer
->level
,
849 r600_copy_from_staging_texture(ctx
, rtransfer
);
853 if (rtransfer
->staging
)
854 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
859 void r600_init_surface_functions(struct r600_context
*r600
)
861 r600
->context
.create_surface
= r600_create_surface
;
862 r600
->context
.surface_destroy
= r600_surface_destroy
;
865 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
866 const unsigned char *swizzle_view
)
869 unsigned char swizzle
[4];
871 const uint32_t swizzle_shift
[4] = {
874 const uint32_t swizzle_bit
[4] = {
879 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
881 memcpy(swizzle
, swizzle_format
, 4);
885 for (i
= 0; i
< 4; i
++) {
886 switch (swizzle
[i
]) {
887 case UTIL_FORMAT_SWIZZLE_Y
:
888 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
890 case UTIL_FORMAT_SWIZZLE_Z
:
891 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
893 case UTIL_FORMAT_SWIZZLE_W
:
894 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
896 case UTIL_FORMAT_SWIZZLE_0
:
897 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
899 case UTIL_FORMAT_SWIZZLE_1
:
900 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
902 default: /* UTIL_FORMAT_SWIZZLE_X */
903 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
909 /* texture format translate */
910 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
911 enum pipe_format format
,
912 const unsigned char *swizzle_view
,
913 uint32_t *word4_p
, uint32_t *yuv_format_p
)
915 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
916 const struct util_format_description
*desc
;
917 boolean uniform
= TRUE
;
918 static int r600_enable_s3tc
= -1;
919 bool is_srgb_valid
= FALSE
;
922 const uint32_t sign_bit
[4] = {
923 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
924 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
925 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
926 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
928 desc
= util_format_description(format
);
930 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
932 /* Colorspace (return non-RGB formats directly). */
933 switch (desc
->colorspace
) {
934 /* Depth stencil formats */
935 case UTIL_FORMAT_COLORSPACE_ZS
:
937 case PIPE_FORMAT_Z16_UNORM
:
940 case PIPE_FORMAT_X24S8_UINT
:
941 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
942 case PIPE_FORMAT_Z24X8_UNORM
:
943 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
946 case PIPE_FORMAT_S8X24_UINT
:
947 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
948 case PIPE_FORMAT_X8Z24_UNORM
:
949 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
952 case PIPE_FORMAT_S8_UINT
:
954 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
956 case PIPE_FORMAT_Z32_FLOAT
:
957 result
= FMT_32_FLOAT
;
959 case PIPE_FORMAT_X32_S8X24_UINT
:
960 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
961 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
962 result
= FMT_X24_8_32_FLOAT
;
968 case UTIL_FORMAT_COLORSPACE_YUV
:
969 yuv_format
|= (1 << 30);
971 case PIPE_FORMAT_UYVY
:
972 case PIPE_FORMAT_YUYV
:
976 goto out_unknown
; /* XXX */
978 case UTIL_FORMAT_COLORSPACE_SRGB
:
979 word4
|= S_038010_FORCE_DEGAMMA(1);
986 if (r600_enable_s3tc
== -1) {
987 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
988 if (rscreen
->info
.drm_minor
>= 9)
989 r600_enable_s3tc
= 1;
991 r600_enable_s3tc
= debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
994 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
995 if (!r600_enable_s3tc
)
999 case PIPE_FORMAT_RGTC1_SNORM
:
1000 case PIPE_FORMAT_LATC1_SNORM
:
1001 word4
|= sign_bit
[0];
1002 case PIPE_FORMAT_RGTC1_UNORM
:
1003 case PIPE_FORMAT_LATC1_UNORM
:
1006 case PIPE_FORMAT_RGTC2_SNORM
:
1007 case PIPE_FORMAT_LATC2_SNORM
:
1008 word4
|= sign_bit
[0] | sign_bit
[1];
1009 case PIPE_FORMAT_RGTC2_UNORM
:
1010 case PIPE_FORMAT_LATC2_UNORM
:
1018 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1020 if (!r600_enable_s3tc
)
1023 if (!util_format_s3tc_enabled
) {
1028 case PIPE_FORMAT_DXT1_RGB
:
1029 case PIPE_FORMAT_DXT1_RGBA
:
1030 case PIPE_FORMAT_DXT1_SRGB
:
1031 case PIPE_FORMAT_DXT1_SRGBA
:
1033 is_srgb_valid
= TRUE
;
1035 case PIPE_FORMAT_DXT3_RGBA
:
1036 case PIPE_FORMAT_DXT3_SRGBA
:
1038 is_srgb_valid
= TRUE
;
1040 case PIPE_FORMAT_DXT5_RGBA
:
1041 case PIPE_FORMAT_DXT5_SRGBA
:
1043 is_srgb_valid
= TRUE
;
1050 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1052 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1053 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1056 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1057 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1065 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1066 result
= FMT_5_9_9_9_SHAREDEXP
;
1068 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1069 result
= FMT_10_11_11_FLOAT
;
1074 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1075 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1076 word4
|= sign_bit
[i
];
1080 /* R8G8Bx_SNORM - XXX CxV8U8 */
1082 /* See whether the components are of the same size. */
1083 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1084 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1087 /* Non-uniform formats. */
1089 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1090 desc
->channel
[0].pure_integer
)
1091 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1092 switch(desc
->nr_channels
) {
1094 if (desc
->channel
[0].size
== 5 &&
1095 desc
->channel
[1].size
== 6 &&
1096 desc
->channel
[2].size
== 5) {
1102 if (desc
->channel
[0].size
== 5 &&
1103 desc
->channel
[1].size
== 5 &&
1104 desc
->channel
[2].size
== 5 &&
1105 desc
->channel
[3].size
== 1) {
1106 result
= FMT_1_5_5_5
;
1109 if (desc
->channel
[0].size
== 10 &&
1110 desc
->channel
[1].size
== 10 &&
1111 desc
->channel
[2].size
== 10 &&
1112 desc
->channel
[3].size
== 2) {
1113 result
= FMT_2_10_10_10
;
1121 /* Find the first non-VOID channel. */
1122 for (i
= 0; i
< 4; i
++) {
1123 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1131 /* uniform formats */
1132 switch (desc
->channel
[i
].type
) {
1133 case UTIL_FORMAT_TYPE_UNSIGNED
:
1134 case UTIL_FORMAT_TYPE_SIGNED
:
1136 if (!desc
->channel
[i
].normalized
&&
1137 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
1141 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1142 desc
->channel
[i
].pure_integer
)
1143 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1145 switch (desc
->channel
[i
].size
) {
1147 switch (desc
->nr_channels
) {
1152 result
= FMT_4_4_4_4
;
1157 switch (desc
->nr_channels
) {
1165 result
= FMT_8_8_8_8
;
1166 is_srgb_valid
= TRUE
;
1171 switch (desc
->nr_channels
) {
1179 result
= FMT_16_16_16_16
;
1184 switch (desc
->nr_channels
) {
1192 result
= FMT_32_32_32_32
;
1198 case UTIL_FORMAT_TYPE_FLOAT
:
1199 switch (desc
->channel
[i
].size
) {
1201 switch (desc
->nr_channels
) {
1203 result
= FMT_16_FLOAT
;
1206 result
= FMT_16_16_FLOAT
;
1209 result
= FMT_16_16_16_16_FLOAT
;
1214 switch (desc
->nr_channels
) {
1216 result
= FMT_32_FLOAT
;
1219 result
= FMT_32_32_FLOAT
;
1222 result
= FMT_32_32_32_32_FLOAT
;
1231 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
1236 *yuv_format_p
= yuv_format
;
1239 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1243 static const struct u_resource_vtbl r600_texture_vtbl
=
1245 r600_texture_get_handle
, /* get_handle */
1246 r600_texture_destroy
, /* resource_destroy */
1247 r600_texture_transfer_map
, /* transfer_map */
1248 NULL
, /* transfer_flush_region */
1249 r600_texture_transfer_unmap
, /* transfer_unmap */
1250 NULL
/* transfer_inline_write */