src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_format_s3tc.h>
  31 #include <util/u_math.h>
  32 #include <util/u_inlines.h>
  33 #include <util/u_memory.h>
  34 #include "pipebuffer/pb_buffer.h"
  35 #include "r600_pipe.h"
  36 #include "r600_resource.h"
  37 #include "r600d.h"
  38 #include "r600_formats.h"
  39
  40 /* Copy from a full GPU texture to a transfer's staging one. */
  41 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  42 {
  43         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  44         struct pipe_resource *texture = transfer->resource;
  45
  46         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  47                                 0, 0, 0, 0, texture, transfer->level,
  48                                 &transfer->box);
  49 }
  50
  51
  52 /* Copy from a transfer's staging texture to a full GPU one. */
  53 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  54 {
  55         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  56         struct pipe_resource *texture = transfer->resource;
  57         struct pipe_box sbox;
  58
  59         sbox.x = sbox.y = sbox.z = 0;
  60         sbox.width = transfer->box.width;
  61         sbox.height = transfer->box.height;
  62         /* XXX that might be wrong */
  63         sbox.depth = 1;
  64         ctx->resource_copy_region(ctx, texture, transfer->level,
  65                                   transfer->box.x, transfer->box.y, transfer->box.z,
  66                                   rtransfer->staging_texture,
  67                                   0, &sbox);
  68
  69         ctx->flush(ctx, NULL);
  70 }
  71
  72 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  73                                         unsigned level, unsigned layer)
  74 {
  75         unsigned offset = rtex->offset[level];
  76
  77         switch (rtex->resource.b.b.b.target) {
  78         case PIPE_TEXTURE_3D:
  79         case PIPE_TEXTURE_CUBE:
  80         default:
  81                 return offset + layer * rtex->layer_size[level];
  82         }
  83 }
  84
  85 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
  86                                          enum pipe_format format,
  87                                          unsigned array_mode)
  88 {
  89         struct r600_screen* rscreen = (struct r600_screen *)screen;
  90         unsigned pixsize = util_format_get_blocksize(format);
  91         int p_align;
  92
  93         switch(array_mode) {
  94         case V_038000_ARRAY_1D_TILED_THIN1:
  95                 p_align = MAX2(8,
  96                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
  97                 break;
  98         case V_038000_ARRAY_2D_TILED_THIN1:
  99                 p_align = MAX2(rscreen->tiling_info->num_banks,
 100                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 101                                 rscreen->tiling_info->num_banks)) * 8;
 102                 break;
 103         case V_038000_ARRAY_LINEAR_ALIGNED:
 104                 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
 105                 break;
 106         case V_038000_ARRAY_LINEAR_GENERAL:
 107         default:
 108                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 109                 break;
 110         }
 111         return p_align;
 112 }
 113
 114 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 115                                           unsigned array_mode)
 116 {
 117         struct r600_screen* rscreen = (struct r600_screen *)screen;
 118         int h_align;
 119
 120         switch (array_mode) {
 121         case V_038000_ARRAY_2D_TILED_THIN1:
 122                 h_align = rscreen->tiling_info->num_channels * 8;
 123                 break;
 124         case V_038000_ARRAY_1D_TILED_THIN1:
 125         case V_038000_ARRAY_LINEAR_ALIGNED:
 126                 h_align = 8;
 127                 break;
 128         case V_038000_ARRAY_LINEAR_GENERAL:
 129         default:
 130                 h_align = 1;
 131                 break;
 132         }
 133         return h_align;
 134 }
 135
 136 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 137                                         enum pipe_format format,
 138                                         unsigned array_mode)
 139 {
 140         struct r600_screen* rscreen = (struct r600_screen *)screen;
 141         unsigned pixsize = util_format_get_blocksize(format);
 142         int p_align = r600_get_block_alignment(screen, format, array_mode);
 143         int h_align = r600_get_height_alignment(screen, array_mode);
 144         int b_align;
 145
 146         switch (array_mode) {
 147         case V_038000_ARRAY_2D_TILED_THIN1:
 148                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 149                                p_align * pixsize * h_align);
 150                 break;
 151         case V_038000_ARRAY_1D_TILED_THIN1:
 152         case V_038000_ARRAY_LINEAR_ALIGNED:
 153         case V_038000_ARRAY_LINEAR_GENERAL:
 154         default:
 155                 b_align = rscreen->tiling_info->group_bytes;
 156                 break;
 157         }
 158         return b_align;
 159 }
 160
 161 static unsigned mip_minify(unsigned size, unsigned level)
 162 {
 163         unsigned val;
 164         val = u_minify(size, level);
 165         if (level > 0)
 166                 val = util_next_power_of_two(val);
 167         return val;
 168 }
 169
 170 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
 171                                           struct r600_resource_texture *rtex,
 172                                           unsigned level)
 173 {
 174         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 175         unsigned nblocksx, block_align, width;
 176         unsigned blocksize = util_format_get_blocksize(ptex->format);
 177
 178         if (rtex->pitch_override)
 179                 return rtex->pitch_override / blocksize;
 180
 181         width = mip_minify(ptex->width0, level);
 182         nblocksx = util_format_get_nblocksx(ptex->format, width);
 183
 184         block_align = r600_get_block_alignment(screen, ptex->format,
 185                                               rtex->array_mode[level]);
 186         nblocksx = align(nblocksx, block_align);
 187         return nblocksx;
 188 }
 189
 190 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 191                                           struct r600_resource_texture *rtex,
 192                                           unsigned level)
 193 {
 194         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 195         unsigned height, tile_height;
 196
 197         height = mip_minify(ptex->height0, level);
 198         height = util_format_get_nblocksy(ptex->format, height);
 199         tile_height = r600_get_height_alignment(screen,
 200                                                 rtex->array_mode[level]);
 201         height = align(height, tile_height);
 202         return height;
 203 }
 204
 205 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 206                                         struct r600_resource_texture *rtex,
 207                                         unsigned level, unsigned array_mode)
 208 {
 209         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 210
 211         switch (array_mode) {
 212         case V_0280A0_ARRAY_LINEAR_GENERAL:
 213         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 214         case V_0280A0_ARRAY_1D_TILED_THIN1:
 215         default:
 216                 rtex->array_mode[level] = array_mode;
 217                 break;
 218         case V_0280A0_ARRAY_2D_TILED_THIN1:
 219         {
 220                 unsigned w, h, tile_height, tile_width;
 221
 222                 tile_height = r600_get_height_alignment(screen, array_mode);
 223                 tile_width = r600_get_block_alignment(screen, ptex->format, array_mode);
 224
 225                 w = mip_minify(ptex->width0, level);
 226                 h = mip_minify(ptex->height0, level);
 227                 if (w <= tile_width || h <= tile_height)
 228                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 229                 else
 230                         rtex->array_mode[level] = array_mode;
 231         }
 232         break;
 233         }
 234 }
 235
 236 static void r600_setup_miptree(struct pipe_screen *screen,
 237                                struct r600_resource_texture *rtex,
 238                                unsigned array_mode)
 239 {
 240         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 241         struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
 242         enum chip_class chipc = r600_get_family_class(radeon);
 243         unsigned size, layer_size, i, offset;
 244         unsigned nblocksx, nblocksy, extra_size = 0;
 245
 246         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 247                 unsigned blocksize = util_format_get_blocksize(ptex->format);
 248                 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 249
 250                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 251
 252                 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
 253                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 254
 255                 layer_size = nblocksx * nblocksy * blocksize;
 256                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 257                         if (chipc >= R700)
 258                                 size = layer_size * 8;
 259                         else
 260                                 size = layer_size * 6;
 261                 }
 262                 else if (ptex->target == PIPE_TEXTURE_3D)
 263                         size = layer_size * u_minify(ptex->depth0, i);
 264                 else
 265                         size = layer_size * ptex->array_size;
 266
 267                 /* evergreen stores depth and stencil separately */
 268                 if ((chipc >= EVERGREEN) && util_format_is_depth_or_stencil(ptex->format))
 269                         extra_size = align(extra_size + (nblocksx * nblocksy * 1), base_align);
 270
 271                 /* align base image and start of miptree */
 272                 if ((i == 0) || (i == 1))
 273                         offset = align(offset, base_align);
 274                 rtex->offset[i] = offset;
 275                 rtex->layer_size[i] = layer_size;
 276                 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
 277                 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
 278
 279                 offset += size;
 280         }
 281         rtex->size = offset + extra_size;
 282 }
 283
 284 /* Figure out whether u_blitter will fallback to a transfer operation.
 285  * If so, don't use a staging resource.
 286  */
 287 static boolean permit_hardware_blit(struct pipe_screen *screen,
 288                                         const struct pipe_resource *res)
 289 {
 290         unsigned bind;
 291
 292         if (util_format_is_depth_or_stencil(res->format))
 293                 bind = PIPE_BIND_DEPTH_STENCIL;
 294         else
 295                 bind = PIPE_BIND_RENDER_TARGET;
 296
 297         /* hackaround for S3TC */
 298         if (util_format_is_compressed(res->format))
 299                 return TRUE;
 300
 301         if (!screen->is_format_supported(screen,
 302                                 res->format,
 303                                 res->target,
 304                                 res->nr_samples,
 305                                 bind))
 306                 return FALSE;
 307
 308         if (!screen->is_format_supported(screen,
 309                                 res->format,
 310                                 res->target,
 311                                 res->nr_samples,
 312                                 PIPE_BIND_SAMPLER_VIEW))
 313                 return FALSE;
 314
 315         switch (res->usage) {
 316         case PIPE_USAGE_STREAM:
 317         case PIPE_USAGE_STAGING:
 318                 return FALSE;
 319
 320         default:
 321                 return TRUE;
 322         }
 323 }
 324
 325 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 326                                         struct pipe_resource *ptex,
 327                                         struct winsys_handle *whandle)
 328 {
 329         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 330         struct r600_resource *resource = &rtex->resource;
 331         struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
 332
 333         return r600_bo_get_winsys_handle(radeon, resource->bo,
 334                         rtex->pitch_in_bytes[0], whandle);
 335 }
 336
 337 static void r600_texture_destroy(struct pipe_screen *screen,
 338                                  struct pipe_resource *ptex)
 339 {
 340         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 341         struct r600_resource *resource = &rtex->resource;
 342         struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
 343
 344         if (rtex->flushed_depth_texture)
 345                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 346
 347         if (resource->bo) {
 348                 r600_bo_reference(radeon, &resource->bo, NULL);
 349         }
 350         FREE(rtex);
 351 }
 352
 353 static const struct u_resource_vtbl r600_texture_vtbl =
 354 {
 355         r600_texture_get_handle,        /* get_handle */
 356         r600_texture_destroy,           /* resource_destroy */
 357         r600_texture_get_transfer,      /* get_transfer */
 358         r600_texture_transfer_destroy,  /* transfer_destroy */
 359         r600_texture_transfer_map,      /* transfer_map */
 360         u_default_transfer_flush_region,/* transfer_flush_region */
 361         r600_texture_transfer_unmap,    /* transfer_unmap */
 362         u_default_transfer_inline_write /* transfer_inline_write */
 363 };
 364
 365 static struct r600_resource_texture *
 366 r600_texture_create_object(struct pipe_screen *screen,
 367                            const struct pipe_resource *base,
 368                            unsigned array_mode,
 369                            unsigned pitch_in_bytes_override,
 370                            unsigned max_buffer_size,
 371                            struct r600_bo *bo)
 372 {
 373         struct r600_resource_texture *rtex;
 374         struct r600_resource *resource;
 375         struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
 376
 377         rtex = CALLOC_STRUCT(r600_resource_texture);
 378         if (rtex == NULL)
 379                 return NULL;
 380
 381         resource = &rtex->resource;
 382         resource->b.b.b = *base;
 383         resource->b.b.vtbl = &r600_texture_vtbl;
 384         pipe_reference_init(&resource->b.b.b.reference, 1);
 385         resource->b.b.b.screen = screen;
 386         resource->bo = bo;
 387         rtex->pitch_override = pitch_in_bytes_override;
 388         /* only mark depth textures the HW can hit as depth textures */
 389         if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
 390                 rtex->depth = 1;
 391
 392         r600_setup_miptree(screen, rtex, array_mode);
 393
 394         resource->size = rtex->size;
 395
 396         if (!resource->bo) {
 397                 struct pipe_resource *ptex = &rtex->resource.b.b.b;
 398                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 399
 400                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 401                 if (!resource->bo) {
 402                         FREE(rtex);
 403                         return NULL;
 404                 }
 405         }
 406         return rtex;
 407 }
 408
 409 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 410                                                 const struct pipe_resource *templ)
 411 {
 412         unsigned array_mode = 0;
 413         static int force_tiling = -1;
 414
 415         /* Would like some magic "get_bool_option_once" routine.
 416          */
 417         if (force_tiling == -1) {
 418 #if 0
 419                 /* reenable when 2D tiling is fixed better */
 420                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 421                 if (r600_get_minor_version(rscreen->radeon) >= 9)
 422                         force_tiling = debug_get_bool_option("R600_TILING", TRUE);
 423 #endif
 424                 force_tiling = debug_get_bool_option("R600_TILING", FALSE);
 425         }
 426
 427         if (force_tiling && permit_hardware_blit(screen, templ)) {
 428                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 429                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 430                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 431                 }
 432         }
 433
 434         if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 435             util_format_is_compressed(templ->format))
 436                 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
 437
 438         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 439                                                                   0, 0, NULL);
 440
 441 }
 442
 443 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 444                                                 struct pipe_resource *texture,
 445                                                 const struct pipe_surface *surf_tmpl)
 446 {
 447         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 448         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 449         unsigned level = surf_tmpl->u.tex.level;
 450
 451         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 452         if (surface == NULL)
 453                 return NULL;
 454         /* XXX no offset */
 455 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 456         pipe_reference_init(&surface->base.reference, 1);
 457         pipe_resource_reference(&surface->base.texture, texture);
 458         surface->base.context = pipe;
 459         surface->base.format = surf_tmpl->format;
 460         surface->base.width = mip_minify(texture->width0, level);
 461         surface->base.height = mip_minify(texture->height0, level);
 462         surface->base.usage = surf_tmpl->usage;
 463         surface->base.texture = texture;
 464         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 465         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 466         surface->base.u.tex.level = level;
 467
 468         surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
 469                                                             rtex, level);
 470         return &surface->base;
 471 }
 472
 473 static void r600_surface_destroy(struct pipe_context *pipe,
 474                                  struct pipe_surface *surface)
 475 {
 476         pipe_resource_reference(&surface->texture, NULL);
 477         FREE(surface);
 478 }
 479
 480
 481 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 482                                                const struct pipe_resource *templ,
 483                                                struct winsys_handle *whandle)
 484 {
 485         struct radeon *rw = ((struct r600_screen*)screen)->radeon;
 486         struct r600_bo *bo = NULL;
 487         unsigned stride = 0;
 488         unsigned array_mode = 0;
 489
 490         /* Support only 2D textures without mipmaps */
 491         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 492               templ->depth0 != 1 || templ->last_level != 0)
 493                 return NULL;
 494
 495         bo = r600_bo_handle(rw, whandle, &stride, &array_mode);
 496         if (bo == NULL) {
 497                 return NULL;
 498         }
 499
 500         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 501                                                                   stride, 0, bo);
 502 }
 503
 504 int r600_texture_depth_flush(struct pipe_context *ctx,
 505                              struct pipe_resource *texture, boolean just_create)
 506 {
 507         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 508         struct pipe_resource resource;
 509
 510         if (rtex->flushed_depth_texture)
 511                 goto out;
 512
 513         resource.target = PIPE_TEXTURE_2D;
 514         resource.format = texture->format;
 515         resource.width0 = texture->width0;
 516         resource.height0 = texture->height0;
 517         resource.depth0 = 1;
 518         resource.array_size = 1;
 519         resource.last_level = texture->last_level;
 520         resource.nr_samples = 0;
 521         resource.usage = PIPE_USAGE_DYNAMIC;
 522         resource.bind = 0;
 523         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 524
 525         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 526
 527         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 528         if (rtex->flushed_depth_texture == NULL) {
 529                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 530                 return -ENOMEM;
 531         }
 532
 533         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 534 out:
 535         if (just_create)
 536                 return 0;
 537
 538         /* XXX: only do this if the depth texture has actually changed:
 539          */
 540         r600_blit_uncompress_depth(ctx, rtex);
 541         return 0;
 542 }
 543
 544 /* Needs adjustment for pixelformat:
 545  */
 546 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 547 {
 548         return box->width * box->depth * box->height;
 549 };
 550
 551 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 552                                                 struct pipe_resource *texture,
 553                                                 unsigned level,
 554                                                 unsigned usage,
 555                                                 const struct pipe_box *box)
 556 {
 557         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 558         struct pipe_resource resource;
 559         struct r600_transfer *trans;
 560         int r;
 561         boolean use_staging_texture = FALSE;
 562
 563         /* We cannot map a tiled texture directly because the data is
 564          * in a different order, therefore we do detiling using a blit.
 565          *
 566          * Also, use a temporary in GTT memory for read transfers, as
 567          * the CPU is much happier reading out of cached system memory
 568          * than uncached VRAM.
 569          */
 570         if (R600_TEX_IS_TILED(rtex, level))
 571                 use_staging_texture = TRUE;
 572
 573         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 574                 use_staging_texture = TRUE;
 575
 576         /* XXX: Use a staging texture for uploads if the underlying BO
 577          * is busy.  No interface for checking that currently? so do
 578          * it eagerly whenever the transfer doesn't require a readback
 579          * and might block.
 580          */
 581         if ((usage & PIPE_TRANSFER_WRITE) &&
 582                         !(usage & (PIPE_TRANSFER_READ |
 583                                         PIPE_TRANSFER_DONTBLOCK |
 584                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 585                 use_staging_texture = TRUE;
 586
 587         if (!permit_hardware_blit(ctx->screen, texture) ||
 588                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 589                 use_staging_texture = FALSE;
 590
 591         trans = CALLOC_STRUCT(r600_transfer);
 592         if (trans == NULL)
 593                 return NULL;
 594         pipe_resource_reference(&trans->transfer.resource, texture);
 595         trans->transfer.level = level;
 596         trans->transfer.usage = usage;
 597         trans->transfer.box = *box;
 598         if (rtex->depth) {
 599                 /* XXX: only readback the rectangle which is being mapped?
 600                 */
 601                 /* XXX: when discard is true, no need to read back from depth texture
 602                 */
 603                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 604                 if (r < 0) {
 605                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 606                         pipe_resource_reference(&trans->transfer.resource, NULL);
 607                         FREE(trans);
 608                         return NULL;
 609                 }
 610                 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
 611                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 612                 return &trans->transfer;
 613         } else if (use_staging_texture) {
 614                 resource.target = PIPE_TEXTURE_2D;
 615                 resource.format = texture->format;
 616                 resource.width0 = box->width;
 617                 resource.height0 = box->height;
 618                 resource.depth0 = 1;
 619                 resource.array_size = 1;
 620                 resource.last_level = 0;
 621                 resource.nr_samples = 0;
 622                 resource.usage = PIPE_USAGE_STAGING;
 623                 resource.bind = 0;
 624                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 625                 /* For texture reading, the temporary (detiled) texture is used as
 626                  * a render target when blitting from a tiled texture. */
 627                 if (usage & PIPE_TRANSFER_READ) {
 628                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 629                 }
 630                 /* For texture writing, the temporary texture is used as a sampler
 631                  * when blitting into a tiled texture. */
 632                 if (usage & PIPE_TRANSFER_WRITE) {
 633                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 634                 }
 635                 /* Create the temporary texture. */
 636                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 637                 if (trans->staging_texture == NULL) {
 638                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 639                         pipe_resource_reference(&trans->transfer.resource, NULL);
 640                         FREE(trans);
 641                         return NULL;
 642                 }
 643
 644                 trans->transfer.stride =
 645                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 646                 if (usage & PIPE_TRANSFER_READ) {
 647                         r600_copy_to_staging_texture(ctx, trans);
 648                         /* Always referenced in the blit. */
 649                         ctx->flush(ctx, NULL);
 650                 }
 651                 return &trans->transfer;
 652         }
 653         trans->transfer.stride = rtex->pitch_in_bytes[level];
 654         trans->transfer.layer_stride = rtex->layer_size[level];
 655         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 656         return &trans->transfer;
 657 }
 658
 659 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 660                                    struct pipe_transfer *transfer)
 661 {
 662         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 663         struct pipe_resource *texture = transfer->resource;
 664         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 665
 666         if (rtransfer->staging_texture) {
 667                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 668                         r600_copy_from_staging_texture(ctx, rtransfer);
 669                 }
 670                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 671         }
 672
 673         if (rtex->depth && !rtex->is_flushing_texture) {
 674                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 675                         r600_blit_push_depth(ctx, rtex);
 676         }
 677
 678         pipe_resource_reference(&transfer->resource, NULL);
 679         FREE(transfer);
 680 }
 681
 682 void* r600_texture_transfer_map(struct pipe_context *ctx,
 683                                 struct pipe_transfer* transfer)
 684 {
 685         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 686         struct r600_bo *bo;
 687         enum pipe_format format = transfer->resource->format;
 688         struct radeon *radeon = ((struct r600_screen*)ctx->screen)->radeon;
 689         unsigned offset = 0;
 690         char *map;
 691
 692         if (rtransfer->staging_texture) {
 693                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 694         } else {
 695                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 696
 697                 if (rtex->flushed_depth_texture)
 698                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 699                 else
 700                         bo = ((struct r600_resource *)transfer->resource)->bo;
 701
 702                 offset = rtransfer->offset +
 703                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 704                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 705         }
 706
 707         if (!(map = r600_bo_map(radeon, bo, transfer->usage, ctx))) {
 708                 return NULL;
 709         }
 710
 711         return map + offset;
 712 }
 713
 714 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 715                                  struct pipe_transfer* transfer)
 716 {
 717         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 718         struct radeon *radeon = ((struct r600_screen*)ctx->screen)->radeon;
 719         struct r600_bo *bo;
 720
 721         if (rtransfer->staging_texture) {
 722                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 723         } else {
 724                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 725
 726                 if (rtex->flushed_depth_texture) {
 727                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 728                 } else {
 729                         bo = ((struct r600_resource *)transfer->resource)->bo;
 730                 }
 731         }
 732         r600_bo_unmap(radeon, bo);
 733 }
 734
 735 void r600_init_surface_functions(struct r600_pipe_context *r600)
 736 {
 737         r600->context.create_surface = r600_create_surface;
 738         r600->context.surface_destroy = r600_surface_destroy;
 739 }
 740
 741 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 742                 const unsigned char *swizzle_view)
 743 {
 744         unsigned i;
 745         unsigned char swizzle[4];
 746         unsigned result = 0;
 747         const uint32_t swizzle_shift[4] = {
 748                 16, 19, 22, 25,
 749         };
 750         const uint32_t swizzle_bit[4] = {
 751                 0, 1, 2, 3,
 752         };
 753
 754         if (swizzle_view) {
 755                 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
 756         } else {
 757                 memcpy(swizzle, swizzle_format, 4);
 758         }
 759
 760         /* Get swizzle. */
 761         for (i = 0; i < 4; i++) {
 762                 switch (swizzle[i]) {
 763                 case UTIL_FORMAT_SWIZZLE_Y:
 764                         result |= swizzle_bit[1] << swizzle_shift[i];
 765                         break;
 766                 case UTIL_FORMAT_SWIZZLE_Z:
 767                         result |= swizzle_bit[2] << swizzle_shift[i];
 768                         break;
 769                 case UTIL_FORMAT_SWIZZLE_W:
 770                         result |= swizzle_bit[3] << swizzle_shift[i];
 771                         break;
 772                 case UTIL_FORMAT_SWIZZLE_0:
 773                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 774                         break;
 775                 case UTIL_FORMAT_SWIZZLE_1:
 776                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 777                         break;
 778                 default: /* UTIL_FORMAT_SWIZZLE_X */
 779                         result |= swizzle_bit[0] << swizzle_shift[i];
 780                 }
 781         }
 782         return result;
 783 }
 784
 785 /* texture format translate */
 786 uint32_t r600_translate_texformat(struct pipe_screen *screen,
 787                                   enum pipe_format format,
 788                                   const unsigned char *swizzle_view,
 789                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 790 {
 791         uint32_t result = 0, word4 = 0, yuv_format = 0;
 792         const struct util_format_description *desc;
 793         boolean uniform = TRUE;
 794         static int r600_enable_s3tc = -1;
 795
 796         int i;
 797         const uint32_t sign_bit[4] = {
 798                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 799                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 800                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 801                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 802         };
 803         desc = util_format_description(format);
 804
 805         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 806
 807         /* Colorspace (return non-RGB formats directly). */
 808         switch (desc->colorspace) {
 809                 /* Depth stencil formats */
 810         case UTIL_FORMAT_COLORSPACE_ZS:
 811                 switch (format) {
 812                 case PIPE_FORMAT_Z16_UNORM:
 813                         result = FMT_16;
 814                         goto out_word4;
 815                 case PIPE_FORMAT_X24S8_USCALED:
 816                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 817                 case PIPE_FORMAT_Z24X8_UNORM:
 818                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 819                         result = FMT_8_24;
 820                         goto out_word4;
 821                 case PIPE_FORMAT_S8X24_USCALED:
 822                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 823                 case PIPE_FORMAT_X8Z24_UNORM:
 824                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 825                         result = FMT_24_8;
 826                         goto out_word4;
 827                 case PIPE_FORMAT_S8_USCALED:
 828                         result = FMT_8;
 829                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 830                         goto out_word4;
 831                 case PIPE_FORMAT_Z32_FLOAT:
 832                         result = FMT_32_FLOAT;
 833                         goto out_word4;
 834                 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
 835                         result = FMT_X24_8_32_FLOAT;
 836                         goto out_word4;
 837                 default:
 838                         goto out_unknown;
 839                 }
 840
 841         case UTIL_FORMAT_COLORSPACE_YUV:
 842                 yuv_format |= (1 << 30);
 843                 switch (format) {
 844                 case PIPE_FORMAT_UYVY:
 845                 case PIPE_FORMAT_YUYV:
 846                 default:
 847                         break;
 848                 }
 849                 goto out_unknown; /* TODO */
 850
 851         case UTIL_FORMAT_COLORSPACE_SRGB:
 852                 word4 |= S_038010_FORCE_DEGAMMA(1);
 853                 break;
 854
 855         default:
 856                 break;
 857         }
 858
 859         if (r600_enable_s3tc == -1) {
 860                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 861                 if (r600_get_minor_version(rscreen->radeon) >= 9)
 862                         r600_enable_s3tc = 1;
 863                 else
 864                         r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 865         }
 866
 867         if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 868                 if (!r600_enable_s3tc)
 869                         goto out_unknown;
 870
 871                 switch (format) {
 872                 case PIPE_FORMAT_RGTC1_SNORM:
 873                 case PIPE_FORMAT_LATC1_SNORM:
 874                         word4 |= sign_bit[0];
 875                 case PIPE_FORMAT_RGTC1_UNORM:
 876                 case PIPE_FORMAT_LATC1_UNORM:
 877                         result = FMT_BC4;
 878                         goto out_word4;
 879                 case PIPE_FORMAT_RGTC2_SNORM:
 880                 case PIPE_FORMAT_LATC2_SNORM:
 881                         word4 |= sign_bit[0] | sign_bit[1];
 882                 case PIPE_FORMAT_RGTC2_UNORM:
 883                 case PIPE_FORMAT_LATC2_UNORM:
 884                         result = FMT_BC5;
 885                         goto out_word4;
 886                 default:
 887                         goto out_unknown;
 888                 }
 889         }
 890
 891         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 892
 893                 if (!r600_enable_s3tc)
 894                         goto out_unknown;
 895
 896                 if (!util_format_s3tc_enabled) {
 897                         goto out_unknown;
 898                 }
 899
 900                 switch (format) {
 901                 case PIPE_FORMAT_DXT1_RGB:
 902                 case PIPE_FORMAT_DXT1_RGBA:
 903                 case PIPE_FORMAT_DXT1_SRGB:
 904                 case PIPE_FORMAT_DXT1_SRGBA:
 905                         result = FMT_BC1;
 906                         goto out_word4;
 907                 case PIPE_FORMAT_DXT3_RGBA:
 908                 case PIPE_FORMAT_DXT3_SRGBA:
 909                         result = FMT_BC2;
 910                         goto out_word4;
 911                 case PIPE_FORMAT_DXT5_RGBA:
 912                 case PIPE_FORMAT_DXT5_SRGBA:
 913                         result = FMT_BC3;
 914                         goto out_word4;
 915                 default:
 916                         goto out_unknown;
 917                 }
 918         }
 919
 920         if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
 921                 result = FMT_5_9_9_9_SHAREDEXP;
 922                 goto out_word4;
 923         } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 924                 result = FMT_10_11_11_FLOAT;
 925                 goto out_word4;
 926         }
 927
 928
 929         for (i = 0; i < desc->nr_channels; i++) {
 930                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 931                         word4 |= sign_bit[i];
 932                 }
 933         }
 934
 935         /* R8G8Bx_SNORM - TODO CxV8U8 */
 936
 937         /* See whether the components are of the same size. */
 938         for (i = 1; i < desc->nr_channels; i++) {
 939                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 940         }
 941
 942         /* Non-uniform formats. */
 943         if (!uniform) {
 944                 switch(desc->nr_channels) {
 945                 case 3:
 946                         if (desc->channel[0].size == 5 &&
 947                             desc->channel[1].size == 6 &&
 948                             desc->channel[2].size == 5) {
 949                                 result = FMT_5_6_5;
 950                                 goto out_word4;
 951                         }
 952                         goto out_unknown;
 953                 case 4:
 954                         if (desc->channel[0].size == 5 &&
 955                             desc->channel[1].size == 5 &&
 956                             desc->channel[2].size == 5 &&
 957                             desc->channel[3].size == 1) {
 958                                 result = FMT_1_5_5_5;
 959                                 goto out_word4;
 960                         }
 961                         if (desc->channel[0].size == 10 &&
 962                             desc->channel[1].size == 10 &&
 963                             desc->channel[2].size == 10 &&
 964                             desc->channel[3].size == 2) {
 965                                 result = FMT_2_10_10_10;
 966                                 goto out_word4;
 967                         }
 968                         goto out_unknown;
 969                 }
 970                 goto out_unknown;
 971         }
 972
 973         /* Find the first non-VOID channel. */
 974         for (i = 0; i < 4; i++) {
 975                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 976                         break;
 977                 }
 978         }
 979
 980         if (i == 4)
 981                 goto out_unknown;
 982
 983         /* uniform formats */
 984         switch (desc->channel[i].type) {
 985         case UTIL_FORMAT_TYPE_UNSIGNED:
 986         case UTIL_FORMAT_TYPE_SIGNED:
 987                 if (!desc->channel[i].normalized &&
 988                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 989                         goto out_unknown;
 990                 }
 991
 992                 switch (desc->channel[i].size) {
 993                 case 4:
 994                         switch (desc->nr_channels) {
 995                         case 2:
 996                                 result = FMT_4_4;
 997                                 goto out_word4;
 998                         case 4:
 999                                 result = FMT_4_4_4_4;
1000                                 goto out_word4;
1001                         }
1002                         goto out_unknown;
1003                 case 8:
1004                         switch (desc->nr_channels) {
1005                         case 1:
1006                                 result = FMT_8;
1007                                 goto out_word4;
1008                         case 2:
1009                                 result = FMT_8_8;
1010                                 goto out_word4;
1011                         case 4:
1012                                 result = FMT_8_8_8_8;
1013                                 goto out_word4;
1014                         }
1015                         goto out_unknown;
1016                 case 16:
1017                         switch (desc->nr_channels) {
1018                         case 1:
1019                                 result = FMT_16;
1020                                 goto out_word4;
1021                         case 2:
1022                                 result = FMT_16_16;
1023                                 goto out_word4;
1024                         case 4:
1025                                 result = FMT_16_16_16_16;
1026                                 goto out_word4;
1027                         }
1028                         goto out_unknown;
1029                 case 32:
1030                         switch (desc->nr_channels) {
1031                         case 1:
1032                                 result = FMT_32;
1033                                 goto out_word4;
1034                         case 2:
1035                                 result = FMT_32_32;
1036                                 goto out_word4;
1037                         case 4:
1038                                 result = FMT_32_32_32_32;
1039                                 goto out_word4;
1040                         }
1041                 }
1042                 goto out_unknown;
1043
1044         case UTIL_FORMAT_TYPE_FLOAT:
1045                 switch (desc->channel[i].size) {
1046                 case 16:
1047                         switch (desc->nr_channels) {
1048                         case 1:
1049                                 result = FMT_16_FLOAT;
1050                                 goto out_word4;
1051                         case 2:
1052                                 result = FMT_16_16_FLOAT;
1053                                 goto out_word4;
1054                         case 4:
1055                                 result = FMT_16_16_16_16_FLOAT;
1056                                 goto out_word4;
1057                         }
1058                         goto out_unknown;
1059                 case 32:
1060                         switch (desc->nr_channels) {
1061                         case 1:
1062                                 result = FMT_32_FLOAT;
1063                                 goto out_word4;
1064                         case 2:
1065                                 result = FMT_32_32_FLOAT;
1066                                 goto out_word4;
1067                         case 4:
1068                                 result = FMT_32_32_32_32_FLOAT;
1069                                 goto out_word4;
1070                         }
1071                 }
1072                 goto out_unknown;
1073         }
1074
1075 out_word4:
1076         if (word4_p)
1077                 *word4_p = word4;
1078         if (yuv_format_p)
1079                 *yuv_format_p = yuv_format;
1080         return result;
1081 out_unknown:
1082         /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1083         return ~0;
1084 }