projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: cleanup includes
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
36 {
37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
38 struct pipe_resource *texture = transfer->resource;
39
40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b.b,
41 0, 0, 0, 0, texture, transfer->level,
42 &transfer->box);
43 }
44
45
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
48 {
49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
50 struct pipe_resource *texture = transfer->resource;
51 struct pipe_box sbox;
52
53 sbox.x = sbox.y = sbox.z = 0;
54 sbox.width = transfer->box.width;
55 sbox.height = transfer->box.height;
56 /* XXX that might be wrong */
57 sbox.depth = 1;
58 ctx->resource_copy_region(ctx, texture, transfer->level,
59 transfer->box.x, transfer->box.y, transfer->box.z,
60 &rtransfer->staging->b.b.b,
61 0, &sbox);
62 }
63
64 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
65 unsigned level, unsigned layer)
66 {
67 unsigned offset = rtex->offset[level];
68
69 switch (rtex->resource.b.b.b.target) {
70 case PIPE_TEXTURE_3D:
71 case PIPE_TEXTURE_CUBE:
72 default:
73 return offset + layer * rtex->layer_size[level];
74 }
75 }
76
77 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
78 enum pipe_format format,
79 unsigned array_mode)
80 {
81 struct r600_screen* rscreen = (struct r600_screen *)screen;
82 unsigned pixsize = util_format_get_blocksize(format);
83 int p_align;
84
85 switch(array_mode) {
86 case V_038000_ARRAY_1D_TILED_THIN1:
87 p_align = MAX2(8,
88 ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
89 break;
90 case V_038000_ARRAY_2D_TILED_THIN1:
91 p_align = MAX2(rscreen->tiling_info.num_banks,
92 (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
93 rscreen->tiling_info.num_banks)) * 8;
94 break;
95 case V_038000_ARRAY_LINEAR_ALIGNED:
96 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
97 break;
98 case V_038000_ARRAY_LINEAR_GENERAL:
99 default:
100 p_align = rscreen->tiling_info.group_bytes / pixsize;
101 break;
102 }
103 return p_align;
104 }
105
106 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
107 unsigned array_mode)
108 {
109 struct r600_screen* rscreen = (struct r600_screen *)screen;
110 int h_align;
111
112 switch (array_mode) {
113 case V_038000_ARRAY_2D_TILED_THIN1:
114 h_align = rscreen->tiling_info.num_channels * 8;
115 break;
116 case V_038000_ARRAY_1D_TILED_THIN1:
117 case V_038000_ARRAY_LINEAR_ALIGNED:
118 h_align = 8;
119 break;
120 case V_038000_ARRAY_LINEAR_GENERAL:
121 default:
122 h_align = 1;
123 break;
124 }
125 return h_align;
126 }
127
128 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
129 enum pipe_format format,
130 unsigned array_mode)
131 {
132 struct r600_screen* rscreen = (struct r600_screen *)screen;
133 unsigned pixsize = util_format_get_blocksize(format);
134 int p_align = r600_get_block_alignment(screen, format, array_mode);
135 int h_align = r600_get_height_alignment(screen, array_mode);
136 int b_align;
137
138 switch (array_mode) {
139 case V_038000_ARRAY_2D_TILED_THIN1:
140 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
141 p_align * pixsize * h_align);
142 break;
143 case V_038000_ARRAY_1D_TILED_THIN1:
144 case V_038000_ARRAY_LINEAR_ALIGNED:
145 case V_038000_ARRAY_LINEAR_GENERAL:
146 default:
147 b_align = rscreen->tiling_info.group_bytes;
148 break;
149 }
150 return b_align;
151 }
152
153 static unsigned mip_minify(unsigned size, unsigned level)
154 {
155 unsigned val;
156 val = u_minify(size, level);
157 if (level > 0)
158 val = util_next_power_of_two(val);
159 return val;
160 }
161
162 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
163 struct r600_resource_texture *rtex,
164 unsigned level)
165 {
166 struct pipe_resource *ptex = &rtex->resource.b.b.b;
167 unsigned nblocksx, block_align, width;
168 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
169
170 if (rtex->pitch_override)
171 return rtex->pitch_override / blocksize;
172
173 width = mip_minify(ptex->width0, level);
174 nblocksx = util_format_get_nblocksx(rtex->real_format, width);
175
176 block_align = r600_get_block_alignment(screen, rtex->real_format,
177 rtex->array_mode[level]);
178 nblocksx = align(nblocksx, block_align);
179 return nblocksx;
180 }
181
182 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
183 struct r600_resource_texture *rtex,
184 unsigned level)
185 {
186 struct pipe_resource *ptex = &rtex->resource.b.b.b;
187 unsigned height, tile_height;
188
189 height = mip_minify(ptex->height0, level);
190 height = util_format_get_nblocksy(rtex->real_format, height);
191 tile_height = r600_get_height_alignment(screen,
192 rtex->array_mode[level]);
193
194 /* XXX Hack around an alignment issue. Less tests fail with this.
195 *
196 * The thing is depth-stencil buffers should be tiled, i.e.
197 * the alignment should be >=8. If I make them tiled, stencil starts
198 * working because it no longer overlaps with the depth buffer
199 * in memory, but texturing like drawpix-stencil breaks. */
200 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
201 tile_height = 8;
202
203 height = align(height, tile_height);
204 return height;
205 }
206
207 static void r600_texture_set_array_mode(struct pipe_screen *screen,
208 struct r600_resource_texture *rtex,
209 unsigned level, unsigned array_mode)
210 {
211 struct pipe_resource *ptex = &rtex->resource.b.b.b;
212
213 switch (array_mode) {
214 case V_0280A0_ARRAY_LINEAR_GENERAL:
215 case V_0280A0_ARRAY_LINEAR_ALIGNED:
216 case V_0280A0_ARRAY_1D_TILED_THIN1:
217 default:
218 rtex->array_mode[level] = array_mode;
219 break;
220 case V_0280A0_ARRAY_2D_TILED_THIN1:
221 {
222 unsigned w, h, tile_height, tile_width;
223
224 tile_height = r600_get_height_alignment(screen, array_mode);
225 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
226
227 w = mip_minify(ptex->width0, level);
228 h = mip_minify(ptex->height0, level);
229 if (w <= tile_width || h <= tile_height)
230 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
231 else
232 rtex->array_mode[level] = array_mode;
233 }
234 break;
235 }
236 }
237
238 static int r600_init_surface(struct radeon_surface *surface,
239 const struct pipe_resource *ptex,
240 unsigned array_mode)
241 {
242 surface->npix_x = ptex->width0;
243 surface->npix_y = ptex->height0;
244 surface->npix_z = ptex->depth0;
245 surface->blk_w = util_format_get_blockwidth(ptex->format);
246 surface->blk_h = util_format_get_blockheight(ptex->format);
247 surface->blk_d = 1;
248 surface->array_size = 1;
249 surface->last_level = ptex->last_level;
250 surface->bpe = util_format_get_blocksize(ptex->format);
251 /* align byte per element on dword */
252 if (surface->bpe == 3) {
253 surface->bpe = 4;
254 }
255 surface->nsamples = 1;
256 surface->flags = 0;
257 switch (array_mode) {
258 case V_038000_ARRAY_1D_TILED_THIN1:
259 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
260 break;
261 case V_038000_ARRAY_2D_TILED_THIN1:
262 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
263 break;
264 case V_038000_ARRAY_LINEAR_ALIGNED:
265 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
266 break;
267 case V_038000_ARRAY_LINEAR_GENERAL:
268 default:
269 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
270 break;
271 }
272 switch (ptex->target) {
273 case PIPE_TEXTURE_1D:
274 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
275 break;
276 case PIPE_TEXTURE_RECT:
277 case PIPE_TEXTURE_2D:
278 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
279 break;
280 case PIPE_TEXTURE_3D:
281 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
282 break;
283 case PIPE_TEXTURE_1D_ARRAY:
284 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
285 surface->array_size = ptex->array_size;
286 break;
287 case PIPE_TEXTURE_2D_ARRAY:
288 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
289 surface->array_size = ptex->array_size;
290 break;
291 case PIPE_TEXTURE_CUBE:
292 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
293 break;
294 case PIPE_BUFFER:
295 default:
296 return -EINVAL;
297 }
298 if (ptex->bind & PIPE_BIND_SCANOUT) {
299 surface->flags |= RADEON_SURF_SCANOUT;
300 }
301 if (util_format_is_depth_and_stencil(ptex->format)) {
302 surface->flags |= RADEON_SURF_ZBUFFER;
303 surface->flags |= RADEON_SURF_SBUFFER;
304 }
305
306 return 0;
307 }
308
309 static int r600_setup_surface(struct pipe_screen *screen,
310 struct r600_resource_texture *rtex,
311 unsigned array_mode,
312 unsigned pitch_in_bytes_override)
313 {
314 struct pipe_resource *ptex = &rtex->resource.b.b.b;
315 struct r600_screen *rscreen = (struct r600_screen*)screen;
316 unsigned i;
317 int r;
318
319 if (util_format_is_depth_or_stencil(rtex->real_format)) {
320 rtex->surface.flags |= RADEON_SURF_ZBUFFER;
321 rtex->surface.flags |= RADEON_SURF_SBUFFER;
322 }
323
324 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
325 if (r) {
326 return r;
327 }
328 rtex->size = rtex->surface.bo_size;
329 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
330 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
331 * for those
332 */
333 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
334 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
335 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
336 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
337 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
338 }
339 }
340 for (i = 0; i <= ptex->last_level; i++) {
341 rtex->offset[i] = rtex->surface.level[i].offset;
342 rtex->layer_size[i] = rtex->surface.level[i].slice_size;
343 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
344 switch (rtex->surface.level[i].mode) {
345 case RADEON_SURF_MODE_LINEAR_ALIGNED:
346 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
347 break;
348 case RADEON_SURF_MODE_1D:
349 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
350 break;
351 case RADEON_SURF_MODE_2D:
352 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
353 break;
354 default:
355 case RADEON_SURF_MODE_LINEAR:
356 rtex->array_mode[i] = 0;
357 break;
358 }
359 }
360 return 0;
361 }
362
363 static void r600_setup_miptree(struct pipe_screen *screen,
364 struct r600_resource_texture *rtex,
365 unsigned array_mode)
366 {
367 struct pipe_resource *ptex = &rtex->resource.b.b.b;
368 enum chip_class chipc = ((struct r600_screen*)screen)->chip_class;
369 unsigned size, layer_size, i, offset;
370 unsigned nblocksx, nblocksy;
371
372 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
373 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
374 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
375
376 r600_texture_set_array_mode(screen, rtex, i, array_mode);
377
378 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
379 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
380
381 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL)
382 layer_size = align(nblocksx, 64) * nblocksy * blocksize;
383 else
384 layer_size = nblocksx * nblocksy * blocksize;
385
386 if (ptex->target == PIPE_TEXTURE_CUBE) {
387 if (chipc >= R700)
388 size = layer_size * 8;
389 else
390 size = layer_size * 6;
391 }
392 else if (ptex->target == PIPE_TEXTURE_3D)
393 size = layer_size * u_minify(ptex->depth0, i);
394 else
395 size = layer_size * ptex->array_size;
396
397 /* align base image and start of miptree */
398 if ((i == 0) || (i == 1))
399 offset = align(offset, base_align);
400 rtex->offset[i] = offset;
401 rtex->layer_size[i] = layer_size;
402 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
403 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
404
405 offset += size;
406 }
407 rtex->size = offset;
408 }
409
410 /* Figure out whether u_blitter will fallback to a transfer operation.
411 * If so, don't use a staging resource.
412 */
413 static boolean permit_hardware_blit(struct pipe_screen *screen,
414 const struct pipe_resource *res)
415 {
416 unsigned bind;
417
418 if (util_format_is_depth_or_stencil(res->format))
419 bind = PIPE_BIND_DEPTH_STENCIL;
420 else
421 bind = PIPE_BIND_RENDER_TARGET;
422
423 /* hackaround for S3TC */
424 if (util_format_is_compressed(res->format))
425 return TRUE;
426
427 if (!screen->is_format_supported(screen,
428 res->format,
429 res->target,
430 res->nr_samples,
431 bind))
432 return FALSE;
433
434 if (!screen->is_format_supported(screen,
435 res->format,
436 res->target,
437 res->nr_samples,
438 PIPE_BIND_SAMPLER_VIEW))
439 return FALSE;
440
441 return TRUE;
442 }
443
444 static boolean r600_texture_get_handle(struct pipe_screen* screen,
445 struct pipe_resource *ptex,
446 struct winsys_handle *whandle)
447 {
448 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
449 struct r600_resource *resource = &rtex->resource;
450 struct r600_screen *rscreen = (struct r600_screen*)screen;
451
452 return rscreen->ws->buffer_get_handle(resource->buf,
453 rtex->pitch_in_bytes[0], whandle);
454 }
455
456 static void r600_texture_destroy(struct pipe_screen *screen,
457 struct pipe_resource *ptex)
458 {
459 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
460 struct r600_resource *resource = &rtex->resource;
461
462 if (rtex->flushed_depth_texture)
463 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
464
465 if (rtex->stencil)
466 pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL);
467
468 pb_reference(&resource->buf, NULL);
469 FREE(rtex);
470 }
471
472 static const struct u_resource_vtbl r600_texture_vtbl =
473 {
474 r600_texture_get_handle, /* get_handle */
475 r600_texture_destroy, /* resource_destroy */
476 r600_texture_get_transfer, /* get_transfer */
477 r600_texture_transfer_destroy, /* transfer_destroy */
478 r600_texture_transfer_map, /* transfer_map */
479 NULL, /* transfer_flush_region */
480 r600_texture_transfer_unmap, /* transfer_unmap */
481 NULL /* transfer_inline_write */
482 };
483
484 static struct r600_resource_texture *
485 r600_texture_create_object(struct pipe_screen *screen,
486 const struct pipe_resource *base,
487 unsigned array_mode,
488 unsigned pitch_in_bytes_override,
489 unsigned max_buffer_size,
490 struct pb_buffer *buf,
491 boolean alloc_bo,
492 struct radeon_surface *surface)
493 {
494 struct r600_resource_texture *rtex;
495 struct r600_resource *resource;
496 struct r600_screen *rscreen = (struct r600_screen*)screen;
497 int r;
498
499 rtex = CALLOC_STRUCT(r600_resource_texture);
500 if (rtex == NULL)
501 return NULL;
502
503 resource = &rtex->resource;
504 resource->b.b.b = *base;
505 resource->b.b.vtbl = &r600_texture_vtbl;
506 pipe_reference_init(&resource->b.b.b.reference, 1);
507 resource->b.b.b.screen = screen;
508 rtex->pitch_override = pitch_in_bytes_override;
509 rtex->real_format = base->format;
510
511 /* We must split depth and stencil into two separate buffers on Evergreen. */
512 if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) &&
513 ((struct r600_screen*)screen)->chip_class >= EVERGREEN &&
514 util_format_is_depth_and_stencil(base->format) &&
515 !rscreen->use_surface_alloc) {
516 struct pipe_resource stencil;
517 unsigned stencil_pitch_override = 0;
518
519 switch (base->format) {
520 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
521 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
522 break;
523 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
524 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
525 break;
526 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
527 rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
528 break;
529 default:
530 assert(0);
531 FREE(rtex);
532 return NULL;
533 }
534
535 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
536 if (pitch_in_bytes_override) {
537 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT ||
538 base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
539 stencil_pitch_override = pitch_in_bytes_override / 4;
540 }
541
542 /* Allocate the stencil buffer. */
543 stencil = *base;
544 stencil.format = PIPE_FORMAT_S8_UINT;
545 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
546 stencil_pitch_override,
547 max_buffer_size, NULL, FALSE, surface);
548 if (!rtex->stencil) {
549 FREE(rtex);
550 return NULL;
551 }
552 /* Proceed in creating the depth buffer. */
553 }
554
555 /* only mark depth textures the HW can hit as depth textures */
556 if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
557 rtex->is_depth = true;
558
559 r600_setup_miptree(screen, rtex, array_mode);
560 if (rscreen->use_surface_alloc) {
561 rtex->surface = *surface;
562 r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
563 if (r) {
564 FREE(rtex);
565 return NULL;
566 }
567 }
568
569 /* If we initialized separate stencil for Evergreen. place it after depth. */
570 if (rtex->stencil) {
571 unsigned stencil_align, stencil_offset;
572
573 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
574 stencil_offset = align(rtex->size, stencil_align);
575
576 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++)
577 rtex->stencil->offset[i] += stencil_offset;
578
579 rtex->size = stencil_offset + rtex->stencil->size;
580 }
581
582 /* Now create the backing buffer. */
583 if (!buf && alloc_bo) {
584 struct pipe_resource *ptex = &rtex->resource.b.b.b;
585 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
586
587 if (rscreen->use_surface_alloc) {
588 base_align = rtex->surface.bo_alignment;
589 } else if (util_format_is_depth_or_stencil(rtex->real_format)) {
590 /* ugly work around depth buffer need stencil room at end of bo */
591 rtex->size += ptex->width0 * ptex->height0;
592 }
593 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
594 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
595 FREE(rtex);
596 return NULL;
597 }
598 } else if (buf) {
599 resource->buf = buf;
600 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
601 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
602 }
603
604 if (rtex->stencil) {
605 pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf);
606 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf;
607 rtex->stencil->resource.domains = rtex->resource.domains;
608 }
609 return rtex;
610 }
611
612 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
613 const struct pipe_resource *templ)
614 {
615 struct r600_screen *rscreen = (struct r600_screen*)screen;
616 struct radeon_surface surface;
617 unsigned array_mode = 0;
618 int r;
619
620 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) {
621 if (rscreen->use_surface_alloc &&
622 !(templ->bind & PIPE_BIND_SCANOUT) &&
623 templ->usage != PIPE_USAGE_STAGING &&
624 templ->usage != PIPE_USAGE_STREAM &&
625 permit_hardware_blit(screen, templ)) {
626 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
627 } else if (util_format_is_compressed(templ->format)) {
628 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
629 }
630 }
631
632 r = r600_init_surface(&surface, templ, array_mode);
633 if (r) {
634 return NULL;
635 }
636 r = rscreen->ws->surface_best(rscreen->ws, &surface);
637 if (r) {
638 return NULL;
639 }
640 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
641 0, 0, NULL, TRUE, &surface);
642 }
643
644 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
645 struct pipe_resource *texture,
646 const struct pipe_surface *surf_tmpl)
647 {
648 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
649 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
650 unsigned level = surf_tmpl->u.tex.level;
651
652 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
653 if (surface == NULL)
654 return NULL;
655 pipe_reference_init(&surface->base.reference, 1);
656 pipe_resource_reference(&surface->base.texture, texture);
657 surface->base.context = pipe;
658 surface->base.format = surf_tmpl->format;
659 surface->base.width = mip_minify(texture->width0, level);
660 surface->base.height = mip_minify(texture->height0, level);
661 surface->base.usage = surf_tmpl->usage;
662 surface->base.texture = texture;
663 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
664 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
665 surface->base.u.tex.level = level;
666
667 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
668 rtex, level);
669 return &surface->base;
670 }
671
672 static void r600_surface_destroy(struct pipe_context *pipe,
673 struct pipe_surface *surface)
674 {
675 pipe_resource_reference(&surface->texture, NULL);
676 FREE(surface);
677 }
678
679 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
680 const struct pipe_resource *templ,
681 struct winsys_handle *whandle)
682 {
683 struct r600_screen *rscreen = (struct r600_screen*)screen;
684 struct pb_buffer *buf = NULL;
685 unsigned stride = 0;
686 unsigned array_mode = 0;
687 enum radeon_bo_layout micro, macro;
688 struct radeon_surface surface;
689 int r;
690
691 /* Support only 2D textures without mipmaps */
692 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
693 templ->depth0 != 1 || templ->last_level != 0)
694 return NULL;
695
696 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
697 if (!buf)
698 return NULL;
699
700 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
701 &surface.bankw, &surface.bankh,
702 &surface.tile_split,
703 &surface.stencil_tile_split,
704 &surface.mtilea);
705
706 if (macro == RADEON_LAYOUT_TILED)
707 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
708 else if (micro == RADEON_LAYOUT_TILED)
709 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
710 else
711 array_mode = 0;
712
713 r = r600_init_surface(&surface, templ, array_mode);
714 if (r) {
715 return NULL;
716 }
717 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
718 stride, 0, buf, FALSE, &surface);
719 }
720
721 int r600_texture_depth_flush(struct pipe_context *ctx,
722 struct pipe_resource *texture, boolean just_create)
723 {
724 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
725 struct pipe_resource resource;
726
727 if (rtex->flushed_depth_texture)
728 goto out;
729
730 resource.target = texture->target;
731 resource.format = texture->format;
732 resource.width0 = texture->width0;
733 resource.height0 = texture->height0;
734 resource.depth0 = texture->depth0;
735 resource.array_size = texture->array_size;
736 resource.last_level = texture->last_level;
737 resource.nr_samples = texture->nr_samples;
738 resource.usage = PIPE_USAGE_DYNAMIC;
739 resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL;
740 resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags;
741
742 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
743 if (rtex->flushed_depth_texture == NULL) {
744 R600_ERR("failed to create temporary texture to hold untiled copy\n");
745 return -ENOMEM;
746 }
747
748 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
749 out:
750 if (just_create)
751 return 0;
752
753 /* XXX: only do this if the depth texture has actually changed:
754 */
755 r600_blit_uncompress_depth(ctx, rtex);
756 return 0;
757 }
758
759 /* Needs adjustment for pixelformat:
760 */
761 static INLINE unsigned u_box_volume( const struct pipe_box *box )
762 {
763 return box->width * box->depth * box->height;
764 };
765
766 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
767 struct pipe_resource *texture,
768 unsigned level,
769 unsigned usage,
770 const struct pipe_box *box)
771 {
772 struct r600_context *rctx = (struct r600_context*)ctx;
773 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
774 struct pipe_resource resource;
775 struct r600_transfer *trans;
776 int r;
777 boolean use_staging_texture = FALSE;
778
779 /* We cannot map a tiled texture directly because the data is
780 * in a different order, therefore we do detiling using a blit.
781 *
782 * Also, use a temporary in GTT memory for read transfers, as
783 * the CPU is much happier reading out of cached system memory
784 * than uncached VRAM.
785 */
786 if (R600_TEX_IS_TILED(rtex, level))
787 use_staging_texture = TRUE;
788
789 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
790 use_staging_texture = TRUE;
791
792 /* Use a staging texture for uploads if the underlying BO is busy. */
793 if (!(usage & PIPE_TRANSFER_READ) &&
794 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
795 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE)))
796 use_staging_texture = TRUE;
797
798 if (!permit_hardware_blit(ctx->screen, texture) ||
799 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
800 use_staging_texture = FALSE;
801
802 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
803 return NULL;
804
805 trans = CALLOC_STRUCT(r600_transfer);
806 if (trans == NULL)
807 return NULL;
808 pipe_resource_reference(&trans->transfer.resource, texture);
809 trans->transfer.level = level;
810 trans->transfer.usage = usage;
811 trans->transfer.box = *box;
812 if (rtex->is_depth) {
813 /* XXX: only readback the rectangle which is being mapped?
814 */
815 /* XXX: when discard is true, no need to read back from depth texture
816 */
817 r = r600_texture_depth_flush(ctx, texture, FALSE);
818 if (r < 0) {
819 R600_ERR("failed to create temporary texture to hold untiled copy\n");
820 pipe_resource_reference(&trans->transfer.resource, NULL);
821 FREE(trans);
822 return NULL;
823 }
824 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
825 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
826 return &trans->transfer;
827 } else if (use_staging_texture) {
828 resource.target = PIPE_TEXTURE_2D;
829 resource.format = texture->format;
830 resource.width0 = box->width;
831 resource.height0 = box->height;
832 resource.depth0 = 1;
833 resource.array_size = 1;
834 resource.last_level = 0;
835 resource.nr_samples = 0;
836 resource.usage = PIPE_USAGE_STAGING;
837 resource.bind = 0;
838 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
839 /* For texture reading, the temporary (detiled) texture is used as
840 * a render target when blitting from a tiled texture. */
841 if (usage & PIPE_TRANSFER_READ) {
842 resource.bind |= PIPE_BIND_RENDER_TARGET;
843 }
844 /* For texture writing, the temporary texture is used as a sampler
845 * when blitting into a tiled texture. */
846 if (usage & PIPE_TRANSFER_WRITE) {
847 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
848 }
849 /* Create the temporary texture. */
850 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
851 if (trans->staging == NULL) {
852 R600_ERR("failed to create temporary texture to hold untiled copy\n");
853 pipe_resource_reference(&trans->transfer.resource, NULL);
854 FREE(trans);
855 return NULL;
856 }
857
858 trans->transfer.stride =
859 ((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0];
860 if (usage & PIPE_TRANSFER_READ) {
861 r600_copy_to_staging_texture(ctx, trans);
862 /* Always referenced in the blit. */
863 r600_flush(ctx, NULL, 0);
864 }
865 return &trans->transfer;
866 }
867 trans->transfer.stride = rtex->pitch_in_bytes[level];
868 trans->transfer.layer_stride = rtex->layer_size[level];
869 trans->offset = r600_texture_get_offset(rtex, level, box->z);
870 return &trans->transfer;
871 }
872
873 void r600_texture_transfer_destroy(struct pipe_context *ctx,
874 struct pipe_transfer *transfer)
875 {
876 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
877 struct pipe_resource *texture = transfer->resource;
878 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
879
880 if (rtransfer->staging) {
881 if (transfer->usage & PIPE_TRANSFER_WRITE) {
882 r600_copy_from_staging_texture(ctx, rtransfer);
883 }
884 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
885 }
886
887 if (rtex->is_depth && !rtex->is_flushing_texture) {
888 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
889 r600_blit_push_depth(ctx, rtex);
890 }
891
892 pipe_resource_reference(&transfer->resource, NULL);
893 FREE(transfer);
894 }
895
896 void* r600_texture_transfer_map(struct pipe_context *ctx,
897 struct pipe_transfer* transfer)
898 {
899 struct r600_context *rctx = (struct r600_context *)ctx;
900 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
901 struct pb_buffer *buf;
902 enum pipe_format format = transfer->resource->format;
903 unsigned offset = 0;
904 char *map;
905
906 if (rtransfer->staging) {
907 buf = ((struct r600_resource *)rtransfer->staging)->buf;
908 } else {
909 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
910
911 if (rtex->flushed_depth_texture)
912 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf;
913 else
914 buf = ((struct r600_resource *)transfer->resource)->buf;
915
916 offset = rtransfer->offset +
917 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
918 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
919 }
920
921 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
922 return NULL;
923 }
924
925 return map + offset;
926 }
927
928 void r600_texture_transfer_unmap(struct pipe_context *ctx,
929 struct pipe_transfer* transfer)
930 {
931 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
932 struct r600_context *rctx = (struct r600_context*)ctx;
933 struct pb_buffer *buf;
934
935 if (rtransfer->staging) {
936 buf = ((struct r600_resource *)rtransfer->staging)->buf;
937 } else {
938 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
939
940 if (rtex->flushed_depth_texture) {
941 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf;
942 } else {
943 buf = ((struct r600_resource *)transfer->resource)->buf;
944 }
945 }
946 rctx->ws->buffer_unmap(buf);
947 }
948
949 void r600_init_surface_functions(struct r600_context *r600)
950 {
951 r600->context.create_surface = r600_create_surface;
952 r600->context.surface_destroy = r600_surface_destroy;
953 }
954
955 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
956 const unsigned char *swizzle_view)
957 {
958 unsigned i;
959 unsigned char swizzle[4];
960 unsigned result = 0;
961 const uint32_t swizzle_shift[4] = {
962 16, 19, 22, 25,
963 };
964 const uint32_t swizzle_bit[4] = {
965 0, 1, 2, 3,
966 };
967
968 if (swizzle_view) {
969 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
970 } else {
971 memcpy(swizzle, swizzle_format, 4);
972 }
973
974 /* Get swizzle. */
975 for (i = 0; i < 4; i++) {
976 switch (swizzle[i]) {
977 case UTIL_FORMAT_SWIZZLE_Y:
978 result |= swizzle_bit[1] << swizzle_shift[i];
979 break;
980 case UTIL_FORMAT_SWIZZLE_Z:
981 result |= swizzle_bit[2] << swizzle_shift[i];
982 break;
983 case UTIL_FORMAT_SWIZZLE_W:
984 result |= swizzle_bit[3] << swizzle_shift[i];
985 break;
986 case UTIL_FORMAT_SWIZZLE_0:
987 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
988 break;
989 case UTIL_FORMAT_SWIZZLE_1:
990 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
991 break;
992 default: /* UTIL_FORMAT_SWIZZLE_X */
993 result |= swizzle_bit[0] << swizzle_shift[i];
994 }
995 }
996 return result;
997 }
998
999 /* texture format translate */
1000 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1001 enum pipe_format format,
1002 const unsigned char *swizzle_view,
1003 uint32_t *word4_p, uint32_t *yuv_format_p)
1004 {
1005 uint32_t result = 0, word4 = 0, yuv_format = 0;
1006 const struct util_format_description *desc;
1007 boolean uniform = TRUE;
1008 static int r600_enable_s3tc = -1;
1009 bool is_srgb_valid = FALSE;
1010
1011 int i;
1012 const uint32_t sign_bit[4] = {
1013 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1014 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1015 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1016 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1017 };
1018 desc = util_format_description(format);
1019
1020 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
1021
1022 /* Colorspace (return non-RGB formats directly). */
1023 switch (desc->colorspace) {
1024 /* Depth stencil formats */
1025 case UTIL_FORMAT_COLORSPACE_ZS:
1026 switch (format) {
1027 case PIPE_FORMAT_Z16_UNORM:
1028 result = FMT_16;
1029 goto out_word4;
1030 case PIPE_FORMAT_X24S8_UINT:
1031 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1032 case PIPE_FORMAT_Z24X8_UNORM:
1033 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1034 result = FMT_8_24;
1035 goto out_word4;
1036 case PIPE_FORMAT_S8X24_UINT:
1037 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1038 case PIPE_FORMAT_X8Z24_UNORM:
1039 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1040 result = FMT_24_8;
1041 goto out_word4;
1042 case PIPE_FORMAT_S8_UINT:
1043 result = FMT_8;
1044 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1045 goto out_word4;
1046 case PIPE_FORMAT_Z32_FLOAT:
1047 result = FMT_32_FLOAT;
1048 goto out_word4;
1049 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1050 result = FMT_X24_8_32_FLOAT;
1051 goto out_word4;
1052 default:
1053 goto out_unknown;
1054 }
1055
1056 case UTIL_FORMAT_COLORSPACE_YUV:
1057 yuv_format |= (1 << 30);
1058 switch (format) {
1059 case PIPE_FORMAT_UYVY:
1060 case PIPE_FORMAT_YUYV:
1061 default:
1062 break;
1063 }
1064 goto out_unknown; /* XXX */
1065
1066 case UTIL_FORMAT_COLORSPACE_SRGB:
1067 word4 |= S_038010_FORCE_DEGAMMA(1);
1068 break;
1069
1070 default:
1071 break;
1072 }
1073
1074 if (r600_enable_s3tc == -1) {
1075 struct r600_screen *rscreen = (struct r600_screen *)screen;
1076 if (rscreen->info.drm_minor >= 9)
1077 r600_enable_s3tc = 1;
1078 else
1079 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
1080 }
1081
1082 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1083 if (!r600_enable_s3tc)
1084 goto out_unknown;
1085
1086 switch (format) {
1087 case PIPE_FORMAT_RGTC1_SNORM:
1088 case PIPE_FORMAT_LATC1_SNORM:
1089 word4 |= sign_bit[0];
1090 case PIPE_FORMAT_RGTC1_UNORM:
1091 case PIPE_FORMAT_LATC1_UNORM:
1092 result = FMT_BC4;
1093 goto out_word4;
1094 case PIPE_FORMAT_RGTC2_SNORM:
1095 case PIPE_FORMAT_LATC2_SNORM:
1096 word4 |= sign_bit[0] | sign_bit[1];
1097 case PIPE_FORMAT_RGTC2_UNORM:
1098 case PIPE_FORMAT_LATC2_UNORM:
1099 result = FMT_BC5;
1100 goto out_word4;
1101 default:
1102 goto out_unknown;
1103 }
1104 }
1105
1106 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1107
1108 if (!r600_enable_s3tc)
1109 goto out_unknown;
1110
1111 if (!util_format_s3tc_enabled) {
1112 goto out_unknown;
1113 }
1114
1115 switch (format) {
1116 case PIPE_FORMAT_DXT1_RGB:
1117 case PIPE_FORMAT_DXT1_RGBA:
1118 case PIPE_FORMAT_DXT1_SRGB:
1119 case PIPE_FORMAT_DXT1_SRGBA:
1120 result = FMT_BC1;
1121 is_srgb_valid = TRUE;
1122 goto out_word4;
1123 case PIPE_FORMAT_DXT3_RGBA:
1124 case PIPE_FORMAT_DXT3_SRGBA:
1125 result = FMT_BC2;
1126 is_srgb_valid = TRUE;
1127 goto out_word4;
1128 case PIPE_FORMAT_DXT5_RGBA:
1129 case PIPE_FORMAT_DXT5_SRGBA:
1130 result = FMT_BC3;
1131 is_srgb_valid = TRUE;
1132 goto out_word4;
1133 default:
1134 goto out_unknown;
1135 }
1136 }
1137
1138 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1139 result = FMT_5_9_9_9_SHAREDEXP;
1140 goto out_word4;
1141 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1142 result = FMT_10_11_11_FLOAT;
1143 goto out_word4;
1144 }
1145
1146
1147 for (i = 0; i < desc->nr_channels; i++) {
1148 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1149 word4 |= sign_bit[i];
1150 }
1151 }
1152
1153 /* R8G8Bx_SNORM - XXX CxV8U8 */
1154
1155 /* See whether the components are of the same size. */
1156 for (i = 1; i < desc->nr_channels; i++) {
1157 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1158 }
1159
1160 /* Non-uniform formats. */
1161 if (!uniform) {
1162 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1163 desc->channel[0].pure_integer)
1164 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1165 switch(desc->nr_channels) {
1166 case 3:
1167 if (desc->channel[0].size == 5 &&
1168 desc->channel[1].size == 6 &&
1169 desc->channel[2].size == 5) {
1170 result = FMT_5_6_5;
1171 goto out_word4;
1172 }
1173 goto out_unknown;
1174 case 4:
1175 if (desc->channel[0].size == 5 &&
1176 desc->channel[1].size == 5 &&
1177 desc->channel[2].size == 5 &&
1178 desc->channel[3].size == 1) {
1179 result = FMT_1_5_5_5;
1180 goto out_word4;
1181 }
1182 if (desc->channel[0].size == 10 &&
1183 desc->channel[1].size == 10 &&
1184 desc->channel[2].size == 10 &&
1185 desc->channel[3].size == 2) {
1186 result = FMT_2_10_10_10;
1187 goto out_word4;
1188 }
1189 goto out_unknown;
1190 }
1191 goto out_unknown;
1192 }
1193
1194 /* Find the first non-VOID channel. */
1195 for (i = 0; i < 4; i++) {
1196 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1197 break;
1198 }
1199 }
1200
1201 if (i == 4)
1202 goto out_unknown;
1203
1204 /* uniform formats */
1205 switch (desc->channel[i].type) {
1206 case UTIL_FORMAT_TYPE_UNSIGNED:
1207 case UTIL_FORMAT_TYPE_SIGNED:
1208 #if 0
1209 if (!desc->channel[i].normalized &&
1210 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1211 goto out_unknown;
1212 }
1213 #endif
1214 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1215 desc->channel[i].pure_integer)
1216 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1217
1218 switch (desc->channel[i].size) {
1219 case 4:
1220 switch (desc->nr_channels) {
1221 case 2:
1222 result = FMT_4_4;
1223 goto out_word4;
1224 case 4:
1225 result = FMT_4_4_4_4;
1226 goto out_word4;
1227 }
1228 goto out_unknown;
1229 case 8:
1230 switch (desc->nr_channels) {
1231 case 1:
1232 result = FMT_8;
1233 goto out_word4;
1234 case 2:
1235 result = FMT_8_8;
1236 goto out_word4;
1237 case 4:
1238 result = FMT_8_8_8_8;
1239 is_srgb_valid = TRUE;
1240 goto out_word4;
1241 }
1242 goto out_unknown;
1243 case 16:
1244 switch (desc->nr_channels) {
1245 case 1:
1246 result = FMT_16;
1247 goto out_word4;
1248 case 2:
1249 result = FMT_16_16;
1250 goto out_word4;
1251 case 4:
1252 result = FMT_16_16_16_16;
1253 goto out_word4;
1254 }
1255 goto out_unknown;
1256 case 32:
1257 switch (desc->nr_channels) {
1258 case 1:
1259 result = FMT_32;
1260 goto out_word4;
1261 case 2:
1262 result = FMT_32_32;
1263 goto out_word4;
1264 case 4:
1265 result = FMT_32_32_32_32;
1266 goto out_word4;
1267 }
1268 }
1269 goto out_unknown;
1270
1271 case UTIL_FORMAT_TYPE_FLOAT:
1272 switch (desc->channel[i].size) {
1273 case 16:
1274 switch (desc->nr_channels) {
1275 case 1:
1276 result = FMT_16_FLOAT;
1277 goto out_word4;
1278 case 2:
1279 result = FMT_16_16_FLOAT;
1280 goto out_word4;
1281 case 4:
1282 result = FMT_16_16_16_16_FLOAT;
1283 goto out_word4;
1284 }
1285 goto out_unknown;
1286 case 32:
1287 switch (desc->nr_channels) {
1288 case 1:
1289 result = FMT_32_FLOAT;
1290 goto out_word4;
1291 case 2:
1292 result = FMT_32_32_FLOAT;
1293 goto out_word4;
1294 case 4:
1295 result = FMT_32_32_32_32_FLOAT;
1296 goto out_word4;
1297 }
1298 }
1299 goto out_unknown;
1300 }
1301
1302 out_word4:
1303
1304 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1305 return ~0;
1306 if (word4_p)
1307 *word4_p = word4;
1308 if (yuv_format_p)
1309 *yuv_format_p = yuv_format;
1310 return result;
1311 out_unknown:
1312 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1313 return ~0;
1314 }