src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_format_s3tc.h>
  31 #include <util/u_math.h>
  32 #include <util/u_inlines.h>
  33 #include <util/u_memory.h>
  34 #include "state_tracker/drm_driver.h"
  35 #include "pipebuffer/pb_buffer.h"
  36 #include "r600_pipe.h"
  37 #include "r600_resource.h"
  38 #include "r600d.h"
  39 #include "r600_formats.h"
  40
  41 /* Copy from a full GPU texture to a transfer's staging one. */
  42 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  43 {
  44         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  45         struct pipe_resource *texture = transfer->resource;
  46
  47         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  48                                 0, 0, 0, 0, texture, transfer->level,
  49                                 &transfer->box);
  50 }
  51
  52
  53 /* Copy from a transfer's staging texture to a full GPU one. */
  54 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  55 {
  56         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  57         struct pipe_resource *texture = transfer->resource;
  58         struct pipe_box sbox;
  59
  60         sbox.x = sbox.y = sbox.z = 0;
  61         sbox.width = transfer->box.width;
  62         sbox.height = transfer->box.height;
  63         /* XXX that might be wrong */
  64         sbox.depth = 1;
  65         ctx->resource_copy_region(ctx, texture, transfer->level,
  66                                   transfer->box.x, transfer->box.y, transfer->box.z,
  67                                   rtransfer->staging_texture,
  68                                   0, &sbox);
  69
  70         ctx->flush(ctx, NULL);
  71 }
  72
  73 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  74                                         unsigned level, unsigned layer)
  75 {
  76         unsigned offset = rtex->offset[level];
  77
  78         switch (rtex->resource.b.b.b.target) {
  79         case PIPE_TEXTURE_3D:
  80         case PIPE_TEXTURE_CUBE:
  81         default:
  82                 return offset + layer * rtex->layer_size[level];
  83         }
  84 }
  85
  86 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
  87                                          enum pipe_format format,
  88                                          unsigned array_mode)
  89 {
  90         struct r600_screen* rscreen = (struct r600_screen *)screen;
  91         unsigned pixsize = util_format_get_blocksize(format);
  92         int p_align;
  93
  94         switch(array_mode) {
  95         case V_038000_ARRAY_1D_TILED_THIN1:
  96                 p_align = MAX2(8,
  97                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
  98                 break;
  99         case V_038000_ARRAY_2D_TILED_THIN1:
 100                 p_align = MAX2(rscreen->tiling_info->num_banks,
 101                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 102                                 rscreen->tiling_info->num_banks)) * 8;
 103                 break;
 104         case V_038000_ARRAY_LINEAR_ALIGNED:
 105                 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
 106                 break;
 107         case V_038000_ARRAY_LINEAR_GENERAL:
 108         default:
 109                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 110                 break;
 111         }
 112         return p_align;
 113 }
 114
 115 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 116                                           unsigned array_mode)
 117 {
 118         struct r600_screen* rscreen = (struct r600_screen *)screen;
 119         int h_align;
 120
 121         switch (array_mode) {
 122         case V_038000_ARRAY_2D_TILED_THIN1:
 123                 h_align = rscreen->tiling_info->num_channels * 8;
 124                 break;
 125         case V_038000_ARRAY_1D_TILED_THIN1:
 126         case V_038000_ARRAY_LINEAR_ALIGNED:
 127                 h_align = 8;
 128                 break;
 129         case V_038000_ARRAY_LINEAR_GENERAL:
 130         default:
 131                 h_align = 1;
 132                 break;
 133         }
 134         return h_align;
 135 }
 136
 137 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 138                                         enum pipe_format format,
 139                                         unsigned array_mode)
 140 {
 141         struct r600_screen* rscreen = (struct r600_screen *)screen;
 142         unsigned pixsize = util_format_get_blocksize(format);
 143         int p_align = r600_get_block_alignment(screen, format, array_mode);
 144         int h_align = r600_get_height_alignment(screen, array_mode);
 145         int b_align;
 146
 147         switch (array_mode) {
 148         case V_038000_ARRAY_2D_TILED_THIN1:
 149                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 150                                p_align * pixsize * h_align);
 151                 break;
 152         case V_038000_ARRAY_1D_TILED_THIN1:
 153         case V_038000_ARRAY_LINEAR_ALIGNED:
 154         case V_038000_ARRAY_LINEAR_GENERAL:
 155         default:
 156                 b_align = rscreen->tiling_info->group_bytes;
 157                 break;
 158         }
 159         return b_align;
 160 }
 161
 162 static unsigned mip_minify(unsigned size, unsigned level)
 163 {
 164         unsigned val;
 165         val = u_minify(size, level);
 166         if (level > 0)
 167                 val = util_next_power_of_two(val);
 168         return val;
 169 }
 170
 171 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
 172                                           struct r600_resource_texture *rtex,
 173                                           unsigned level)
 174 {
 175         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 176         unsigned nblocksx, block_align, width;
 177         unsigned blocksize = util_format_get_blocksize(ptex->format);
 178
 179         if (rtex->pitch_override)
 180                 return rtex->pitch_override / blocksize;
 181
 182         width = mip_minify(ptex->width0, level);
 183         nblocksx = util_format_get_nblocksx(ptex->format, width);
 184
 185         block_align = r600_get_block_alignment(screen, ptex->format,
 186                                               rtex->array_mode[level]);
 187         nblocksx = align(nblocksx, block_align);
 188         return nblocksx;
 189 }
 190
 191 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 192                                           struct r600_resource_texture *rtex,
 193                                           unsigned level)
 194 {
 195         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 196         unsigned height, tile_height;
 197
 198         height = mip_minify(ptex->height0, level);
 199         height = util_format_get_nblocksy(ptex->format, height);
 200         tile_height = r600_get_height_alignment(screen,
 201                                                 rtex->array_mode[level]);
 202         height = align(height, tile_height);
 203         return height;
 204 }
 205
 206 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 207                                         struct r600_resource_texture *rtex,
 208                                         unsigned level, unsigned array_mode)
 209 {
 210         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 211
 212         switch (array_mode) {
 213         case V_0280A0_ARRAY_LINEAR_GENERAL:
 214         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 215         case V_0280A0_ARRAY_1D_TILED_THIN1:
 216         default:
 217                 rtex->array_mode[level] = array_mode;
 218                 break;
 219         case V_0280A0_ARRAY_2D_TILED_THIN1:
 220         {
 221                 unsigned w, h, tile_height, tile_width;
 222
 223                 tile_height = r600_get_height_alignment(screen, array_mode);
 224                 tile_width = r600_get_block_alignment(screen, ptex->format, array_mode);
 225
 226                 w = mip_minify(ptex->width0, level);
 227                 h = mip_minify(ptex->height0, level);
 228                 if (w <= tile_width || h <= tile_height)
 229                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 230                 else
 231                         rtex->array_mode[level] = array_mode;
 232         }
 233         break;
 234         }
 235 }
 236
 237 static void r600_setup_miptree(struct pipe_screen *screen,
 238                                struct r600_resource_texture *rtex,
 239                                unsigned array_mode)
 240 {
 241         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 242         struct radeon *radeon = (struct radeon *)screen->winsys;
 243         enum chip_class chipc = r600_get_family_class(radeon);
 244         unsigned size, layer_size, i, offset;
 245         unsigned nblocksx, nblocksy, extra_size = 0;
 246
 247         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 248                 unsigned blocksize = util_format_get_blocksize(ptex->format);
 249                 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 250
 251                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 252
 253                 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
 254                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 255
 256                 layer_size = nblocksx * nblocksy * blocksize;
 257                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 258                         if (chipc >= R700)
 259                                 size = layer_size * 8;
 260                         else
 261                                 size = layer_size * 6;
 262                 }
 263                 else if (ptex->target == PIPE_TEXTURE_3D)
 264                         size = layer_size * u_minify(ptex->depth0, i);
 265                 else
 266                         size = layer_size * ptex->array_size;
 267
 268                 /* evergreen stores depth and stencil separately */
 269                 if ((chipc >= EVERGREEN) && util_format_is_depth_or_stencil(ptex->format))
 270                         extra_size = align(extra_size + (nblocksx * nblocksy * 1), base_align);
 271
 272                 /* align base image and start of miptree */
 273                 if ((i == 0) || (i == 1))
 274                         offset = align(offset, base_align);
 275                 rtex->offset[i] = offset;
 276                 rtex->layer_size[i] = layer_size;
 277                 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
 278                 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
 279
 280                 offset += size;
 281         }
 282         rtex->size = offset + extra_size;
 283 }
 284
 285 /* Figure out whether u_blitter will fallback to a transfer operation.
 286  * If so, don't use a staging resource.
 287  */
 288 static boolean permit_hardware_blit(struct pipe_screen *screen,
 289                                         const struct pipe_resource *res)
 290 {
 291         unsigned bind;
 292
 293         if (util_format_is_depth_or_stencil(res->format))
 294                 bind = PIPE_BIND_DEPTH_STENCIL;
 295         else
 296                 bind = PIPE_BIND_RENDER_TARGET;
 297
 298         /* hackaround for S3TC */
 299         if (util_format_is_compressed(res->format))
 300                 return TRUE;
 301
 302         if (!screen->is_format_supported(screen,
 303                                 res->format,
 304                                 res->target,
 305                                 res->nr_samples,
 306                                 bind))
 307                 return FALSE;
 308
 309         if (!screen->is_format_supported(screen,
 310                                 res->format,
 311                                 res->target,
 312                                 res->nr_samples,
 313                                 PIPE_BIND_SAMPLER_VIEW))
 314                 return FALSE;
 315
 316         switch (res->usage) {
 317         case PIPE_USAGE_STREAM:
 318         case PIPE_USAGE_STAGING:
 319         case PIPE_USAGE_STATIC:
 320         case PIPE_USAGE_IMMUTABLE:
 321                 return FALSE;
 322
 323         default:
 324                 return TRUE;
 325         }
 326 }
 327
 328 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 329                                         struct pipe_resource *ptex,
 330                                         struct winsys_handle *whandle)
 331 {
 332         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 333         struct r600_resource *resource = &rtex->resource;
 334         struct radeon *radeon = (struct radeon *)screen->winsys;
 335
 336         return r600_bo_get_winsys_handle(radeon, resource->bo,
 337                         rtex->pitch_in_bytes[0], whandle);
 338 }
 339
 340 static void r600_texture_destroy(struct pipe_screen *screen,
 341                                  struct pipe_resource *ptex)
 342 {
 343         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 344         struct r600_resource *resource = &rtex->resource;
 345         struct radeon *radeon = (struct radeon *)screen->winsys;
 346
 347         if (rtex->flushed_depth_texture)
 348                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 349
 350         if (resource->bo) {
 351                 r600_bo_reference(radeon, &resource->bo, NULL);
 352         }
 353         FREE(rtex);
 354 }
 355
 356 static const struct u_resource_vtbl r600_texture_vtbl =
 357 {
 358         r600_texture_get_handle,        /* get_handle */
 359         r600_texture_destroy,           /* resource_destroy */
 360         r600_texture_get_transfer,      /* get_transfer */
 361         r600_texture_transfer_destroy,  /* transfer_destroy */
 362         r600_texture_transfer_map,      /* transfer_map */
 363         u_default_transfer_flush_region,/* transfer_flush_region */
 364         r600_texture_transfer_unmap,    /* transfer_unmap */
 365         u_default_transfer_inline_write /* transfer_inline_write */
 366 };
 367
 368 static struct r600_resource_texture *
 369 r600_texture_create_object(struct pipe_screen *screen,
 370                            const struct pipe_resource *base,
 371                            unsigned array_mode,
 372                            unsigned pitch_in_bytes_override,
 373                            unsigned max_buffer_size,
 374                            struct r600_bo *bo)
 375 {
 376         struct r600_resource_texture *rtex;
 377         struct r600_resource *resource;
 378         struct radeon *radeon = (struct radeon *)screen->winsys;
 379
 380         rtex = CALLOC_STRUCT(r600_resource_texture);
 381         if (rtex == NULL)
 382                 return NULL;
 383
 384         resource = &rtex->resource;
 385         resource->b.b.b = *base;
 386         resource->b.b.vtbl = &r600_texture_vtbl;
 387         pipe_reference_init(&resource->b.b.b.reference, 1);
 388         resource->b.b.b.screen = screen;
 389         resource->bo = bo;
 390         rtex->pitch_override = pitch_in_bytes_override;
 391         /* only mark depth textures the HW can hit as depth textures */
 392         if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
 393                 rtex->depth = 1;
 394
 395         r600_setup_miptree(screen, rtex, array_mode);
 396
 397         resource->size = rtex->size;
 398
 399         if (!resource->bo) {
 400                 struct pipe_resource *ptex = &rtex->resource.b.b.b;
 401                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 402
 403                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 404                 if (!resource->bo) {
 405                         FREE(rtex);
 406                         return NULL;
 407                 }
 408         }
 409         return rtex;
 410 }
 411
 412 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 413                                                 const struct pipe_resource *templ)
 414 {
 415         unsigned array_mode = 0;
 416         static int force_tiling = -1;
 417
 418         /* Would like some magic "get_bool_option_once" routine.
 419          */
 420         if (force_tiling == -1) {
 421 #if 0
 422                 /* reenable when 2D tiling is fixed better */
 423                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 424                 if (r600_get_minor_version(rscreen->radeon) >= 9)
 425                         force_tiling = debug_get_bool_option("R600_TILING", TRUE);
 426 #endif
 427                 force_tiling = debug_get_bool_option("R600_TILING", FALSE);
 428         }
 429
 430         if (force_tiling && permit_hardware_blit(screen, templ)) {
 431                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 432                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 433                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 434                 }
 435         }
 436
 437         if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 438             util_format_is_compressed(templ->format))
 439                 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
 440
 441         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 442                                                                   0, 0, NULL);
 443
 444 }
 445
 446 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 447                                                 struct pipe_resource *texture,
 448                                                 const struct pipe_surface *surf_tmpl)
 449 {
 450         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 451         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 452         unsigned level = surf_tmpl->u.tex.level;
 453
 454         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 455         if (surface == NULL)
 456                 return NULL;
 457         /* XXX no offset */
 458 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 459         pipe_reference_init(&surface->base.reference, 1);
 460         pipe_resource_reference(&surface->base.texture, texture);
 461         surface->base.context = pipe;
 462         surface->base.format = surf_tmpl->format;
 463         surface->base.width = mip_minify(texture->width0, level);
 464         surface->base.height = mip_minify(texture->height0, level);
 465         surface->base.usage = surf_tmpl->usage;
 466         surface->base.texture = texture;
 467         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 468         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 469         surface->base.u.tex.level = level;
 470
 471         surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
 472                                                             rtex, level);
 473         return &surface->base;
 474 }
 475
 476 static void r600_surface_destroy(struct pipe_context *pipe,
 477                                  struct pipe_surface *surface)
 478 {
 479         pipe_resource_reference(&surface->texture, NULL);
 480         FREE(surface);
 481 }
 482
 483
 484 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 485                                                const struct pipe_resource *templ,
 486                                                struct winsys_handle *whandle)
 487 {
 488         struct radeon *rw = (struct radeon*)screen->winsys;
 489         struct r600_bo *bo = NULL;
 490         unsigned array_mode = 0;
 491
 492         /* Support only 2D textures without mipmaps */
 493         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 494               templ->depth0 != 1 || templ->last_level != 0)
 495                 return NULL;
 496
 497         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 498         if (bo == NULL) {
 499                 return NULL;
 500         }
 501
 502         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 503                                                                   whandle->stride,
 504                                                                   0,
 505                                                                   bo);
 506 }
 507
 508 int r600_texture_depth_flush(struct pipe_context *ctx,
 509                              struct pipe_resource *texture, boolean just_create)
 510 {
 511         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 512         struct pipe_resource resource;
 513
 514         if (rtex->flushed_depth_texture)
 515                 goto out;
 516
 517         resource.target = PIPE_TEXTURE_2D;
 518         resource.format = texture->format;
 519         resource.width0 = texture->width0;
 520         resource.height0 = texture->height0;
 521         resource.depth0 = 1;
 522         resource.array_size = 1;
 523         resource.last_level = texture->last_level;
 524         resource.nr_samples = 0;
 525         resource.usage = PIPE_USAGE_DYNAMIC;
 526         resource.bind = 0;
 527         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 528
 529         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 530
 531         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 532         if (rtex->flushed_depth_texture == NULL) {
 533                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 534                 return -ENOMEM;
 535         }
 536
 537         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 538 out:
 539         if (just_create)
 540                 return 0;
 541
 542         /* XXX: only do this if the depth texture has actually changed:
 543          */
 544         r600_blit_uncompress_depth(ctx, rtex);
 545         return 0;
 546 }
 547
 548 /* Needs adjustment for pixelformat:
 549  */
 550 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 551 {
 552         return box->width * box->depth * box->height;
 553 };
 554
 555 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 556                                                 struct pipe_resource *texture,
 557                                                 unsigned level,
 558                                                 unsigned usage,
 559                                                 const struct pipe_box *box)
 560 {
 561         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 562         struct pipe_resource resource;
 563         struct r600_transfer *trans;
 564         int r;
 565         boolean use_staging_texture = FALSE;
 566
 567         /* We cannot map a tiled texture directly because the data is
 568          * in a different order, therefore we do detiling using a blit.
 569          *
 570          * Also, use a temporary in GTT memory for read transfers, as
 571          * the CPU is much happier reading out of cached system memory
 572          * than uncached VRAM.
 573          */
 574         if (R600_TEX_IS_TILED(rtex, level))
 575                 use_staging_texture = TRUE;
 576
 577         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 578                 use_staging_texture = TRUE;
 579
 580         /* XXX: Use a staging texture for uploads if the underlying BO
 581          * is busy.  No interface for checking that currently? so do
 582          * it eagerly whenever the transfer doesn't require a readback
 583          * and might block.
 584          */
 585         if ((usage & PIPE_TRANSFER_WRITE) &&
 586                         !(usage & (PIPE_TRANSFER_READ |
 587                                         PIPE_TRANSFER_DONTBLOCK |
 588                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 589                 use_staging_texture = TRUE;
 590
 591         if (!permit_hardware_blit(ctx->screen, texture) ||
 592                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 593                 use_staging_texture = FALSE;
 594
 595         trans = CALLOC_STRUCT(r600_transfer);
 596         if (trans == NULL)
 597                 return NULL;
 598         pipe_resource_reference(&trans->transfer.resource, texture);
 599         trans->transfer.level = level;
 600         trans->transfer.usage = usage;
 601         trans->transfer.box = *box;
 602         if (rtex->depth) {
 603                 /* XXX: only readback the rectangle which is being mapped?
 604                 */
 605                 /* XXX: when discard is true, no need to read back from depth texture
 606                 */
 607                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 608                 if (r < 0) {
 609                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 610                         pipe_resource_reference(&trans->transfer.resource, NULL);
 611                         FREE(trans);
 612                         return NULL;
 613                 }
 614                 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
 615                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 616                 return &trans->transfer;
 617         } else if (use_staging_texture) {
 618                 resource.target = PIPE_TEXTURE_2D;
 619                 resource.format = texture->format;
 620                 resource.width0 = box->width;
 621                 resource.height0 = box->height;
 622                 resource.depth0 = 1;
 623                 resource.array_size = 1;
 624                 resource.last_level = 0;
 625                 resource.nr_samples = 0;
 626                 resource.usage = PIPE_USAGE_STAGING;
 627                 resource.bind = 0;
 628                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 629                 /* For texture reading, the temporary (detiled) texture is used as
 630                  * a render target when blitting from a tiled texture. */
 631                 if (usage & PIPE_TRANSFER_READ) {
 632                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 633                 }
 634                 /* For texture writing, the temporary texture is used as a sampler
 635                  * when blitting into a tiled texture. */
 636                 if (usage & PIPE_TRANSFER_WRITE) {
 637                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 638                 }
 639                 /* Create the temporary texture. */
 640                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 641                 if (trans->staging_texture == NULL) {
 642                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 643                         pipe_resource_reference(&trans->transfer.resource, NULL);
 644                         FREE(trans);
 645                         return NULL;
 646                 }
 647
 648                 trans->transfer.stride =
 649                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 650                 if (usage & PIPE_TRANSFER_READ) {
 651                         r600_copy_to_staging_texture(ctx, trans);
 652                         /* Always referenced in the blit. */
 653                         ctx->flush(ctx, NULL);
 654                 }
 655                 return &trans->transfer;
 656         }
 657         trans->transfer.stride = rtex->pitch_in_bytes[level];
 658         trans->transfer.layer_stride = rtex->layer_size[level];
 659         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 660         return &trans->transfer;
 661 }
 662
 663 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 664                                    struct pipe_transfer *transfer)
 665 {
 666         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 667         struct pipe_resource *texture = transfer->resource;
 668         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 669
 670         if (rtransfer->staging_texture) {
 671                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 672                         r600_copy_from_staging_texture(ctx, rtransfer);
 673                 }
 674                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 675         }
 676
 677         if (rtex->depth && !rtex->is_flushing_texture) {
 678                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 679                         r600_blit_push_depth(ctx, rtex);
 680         }
 681
 682         pipe_resource_reference(&transfer->resource, NULL);
 683         FREE(transfer);
 684 }
 685
 686 void* r600_texture_transfer_map(struct pipe_context *ctx,
 687                                 struct pipe_transfer* transfer)
 688 {
 689         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 690         struct r600_bo *bo;
 691         enum pipe_format format = transfer->resource->format;
 692         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 693         unsigned offset = 0;
 694         unsigned usage = 0;
 695         char *map;
 696
 697         if (rtransfer->staging_texture) {
 698                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 699         } else {
 700                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 701
 702                 if (rtex->flushed_depth_texture)
 703                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 704                 else
 705                         bo = ((struct r600_resource *)transfer->resource)->bo;
 706
 707                 offset = rtransfer->offset +
 708                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 709                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 710         }
 711
 712         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 713                 usage |= PB_USAGE_CPU_WRITE;
 714
 715                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 716                 }
 717
 718                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 719                 }
 720         }
 721
 722         if (transfer->usage & PIPE_TRANSFER_READ) {
 723                 usage |= PB_USAGE_CPU_READ;
 724         }
 725
 726         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 727                 usage |= PB_USAGE_DONTBLOCK;
 728         }
 729
 730         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 731                 usage |= PB_USAGE_UNSYNCHRONIZED;
 732         }
 733
 734         map = r600_bo_map(radeon, bo, usage, ctx);
 735         if (!map) {
 736                 return NULL;
 737         }
 738
 739         return map + offset;
 740 }
 741
 742 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 743                                  struct pipe_transfer* transfer)
 744 {
 745         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 746         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 747         struct r600_bo *bo;
 748
 749         if (rtransfer->staging_texture) {
 750                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 751         } else {
 752                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 753
 754                 if (rtex->flushed_depth_texture) {
 755                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 756                 } else {
 757                         bo = ((struct r600_resource *)transfer->resource)->bo;
 758                 }
 759         }
 760         r600_bo_unmap(radeon, bo);
 761 }
 762
 763 void r600_init_surface_functions(struct r600_pipe_context *r600)
 764 {
 765         r600->context.create_surface = r600_create_surface;
 766         r600->context.surface_destroy = r600_surface_destroy;
 767 }
 768
 769 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 770                 const unsigned char *swizzle_view)
 771 {
 772         unsigned i;
 773         unsigned char swizzle[4];
 774         unsigned result = 0;
 775         const uint32_t swizzle_shift[4] = {
 776                 16, 19, 22, 25,
 777         };
 778         const uint32_t swizzle_bit[4] = {
 779                 0, 1, 2, 3,
 780         };
 781
 782         if (swizzle_view) {
 783                 /* Combine two sets of swizzles. */
 784                 for (i = 0; i < 4; i++) {
 785                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 786                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 787                 }
 788         } else {
 789                 memcpy(swizzle, swizzle_format, 4);
 790         }
 791
 792         /* Get swizzle. */
 793         for (i = 0; i < 4; i++) {
 794                 switch (swizzle[i]) {
 795                 case UTIL_FORMAT_SWIZZLE_Y:
 796                         result |= swizzle_bit[1] << swizzle_shift[i];
 797                         break;
 798                 case UTIL_FORMAT_SWIZZLE_Z:
 799                         result |= swizzle_bit[2] << swizzle_shift[i];
 800                         break;
 801                 case UTIL_FORMAT_SWIZZLE_W:
 802                         result |= swizzle_bit[3] << swizzle_shift[i];
 803                         break;
 804                 case UTIL_FORMAT_SWIZZLE_0:
 805                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 806                         break;
 807                 case UTIL_FORMAT_SWIZZLE_1:
 808                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 809                         break;
 810                 default: /* UTIL_FORMAT_SWIZZLE_X */
 811                         result |= swizzle_bit[0] << swizzle_shift[i];
 812                 }
 813         }
 814         return result;
 815 }
 816
 817 /* texture format translate */
 818 uint32_t r600_translate_texformat(struct pipe_screen *screen,
 819                                   enum pipe_format format,
 820                                   const unsigned char *swizzle_view,
 821                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 822 {
 823         uint32_t result = 0, word4 = 0, yuv_format = 0;
 824         const struct util_format_description *desc;
 825         boolean uniform = TRUE;
 826         static int r600_enable_s3tc = -1;
 827
 828         int i;
 829         const uint32_t sign_bit[4] = {
 830                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 831                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 832                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 833                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 834         };
 835         desc = util_format_description(format);
 836
 837         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 838
 839         /* Colorspace (return non-RGB formats directly). */
 840         switch (desc->colorspace) {
 841                 /* Depth stencil formats */
 842         case UTIL_FORMAT_COLORSPACE_ZS:
 843                 switch (format) {
 844                 case PIPE_FORMAT_Z16_UNORM:
 845                         result = FMT_16;
 846                         goto out_word4;
 847                 case PIPE_FORMAT_X24S8_USCALED:
 848                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 849                 case PIPE_FORMAT_Z24X8_UNORM:
 850                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 851                         result = FMT_8_24;
 852                         goto out_word4;
 853                 case PIPE_FORMAT_S8X24_USCALED:
 854                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 855                 case PIPE_FORMAT_X8Z24_UNORM:
 856                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 857                         result = FMT_24_8;
 858                         goto out_word4;
 859                 case PIPE_FORMAT_S8_USCALED:
 860                         result = FMT_8;
 861                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 862                         goto out_word4;
 863                 case PIPE_FORMAT_Z32_FLOAT:
 864                         result = FMT_32_FLOAT;
 865                         goto out_word4;
 866                 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
 867                         result = FMT_X24_8_32_FLOAT;
 868                         goto out_word4;
 869                 default:
 870                         goto out_unknown;
 871                 }
 872
 873         case UTIL_FORMAT_COLORSPACE_YUV:
 874                 yuv_format |= (1 << 30);
 875                 switch (format) {
 876                 case PIPE_FORMAT_UYVY:
 877                 case PIPE_FORMAT_YUYV:
 878                 default:
 879                         break;
 880                 }
 881                 goto out_unknown; /* TODO */
 882
 883         case UTIL_FORMAT_COLORSPACE_SRGB:
 884                 word4 |= S_038010_FORCE_DEGAMMA(1);
 885                 break;
 886
 887         default:
 888                 break;
 889         }
 890
 891         if (r600_enable_s3tc == -1) {
 892                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 893                 if (r600_get_minor_version(rscreen->radeon) >= 9)
 894                         r600_enable_s3tc = 1;
 895                 else
 896                         r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 897         }
 898
 899         if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 900                 if (!r600_enable_s3tc)
 901                         goto out_unknown;
 902
 903                 switch (format) {
 904                 case PIPE_FORMAT_RGTC1_SNORM:
 905                 case PIPE_FORMAT_LATC1_SNORM:
 906                         word4 |= sign_bit[0];
 907                 case PIPE_FORMAT_RGTC1_UNORM:
 908                 case PIPE_FORMAT_LATC1_UNORM:
 909                         result = FMT_BC4;
 910                         goto out_word4;
 911                 case PIPE_FORMAT_RGTC2_SNORM:
 912                 case PIPE_FORMAT_LATC2_SNORM:
 913                         word4 |= sign_bit[0] | sign_bit[1];
 914                 case PIPE_FORMAT_RGTC2_UNORM:
 915                 case PIPE_FORMAT_LATC2_UNORM:
 916                         result = FMT_BC5;
 917                         goto out_word4;
 918                 default:
 919                         goto out_unknown;
 920                 }
 921         }
 922
 923         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 924
 925                 if (!r600_enable_s3tc)
 926                         goto out_unknown;
 927
 928                 if (!util_format_s3tc_enabled) {
 929                         goto out_unknown;
 930                 }
 931
 932                 switch (format) {
 933                 case PIPE_FORMAT_DXT1_RGB:
 934                 case PIPE_FORMAT_DXT1_RGBA:
 935                 case PIPE_FORMAT_DXT1_SRGB:
 936                 case PIPE_FORMAT_DXT1_SRGBA:
 937                         result = FMT_BC1;
 938                         goto out_word4;
 939                 case PIPE_FORMAT_DXT3_RGBA:
 940                 case PIPE_FORMAT_DXT3_SRGBA:
 941                         result = FMT_BC2;
 942                         goto out_word4;
 943                 case PIPE_FORMAT_DXT5_RGBA:
 944                 case PIPE_FORMAT_DXT5_SRGBA:
 945                         result = FMT_BC3;
 946                         goto out_word4;
 947                 default:
 948                         goto out_unknown;
 949                 }
 950         }
 951
 952         if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
 953                 result = FMT_5_9_9_9_SHAREDEXP;
 954                 goto out_word4;
 955         } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 956                 result = FMT_10_11_11_FLOAT;
 957                 goto out_word4;
 958         }
 959
 960
 961         for (i = 0; i < desc->nr_channels; i++) {
 962                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 963                         word4 |= sign_bit[i];
 964                 }
 965         }
 966
 967         /* R8G8Bx_SNORM - TODO CxV8U8 */
 968
 969         /* See whether the components are of the same size. */
 970         for (i = 1; i < desc->nr_channels; i++) {
 971                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 972         }
 973
 974         /* Non-uniform formats. */
 975         if (!uniform) {
 976                 switch(desc->nr_channels) {
 977                 case 3:
 978                         if (desc->channel[0].size == 5 &&
 979                             desc->channel[1].size == 6 &&
 980                             desc->channel[2].size == 5) {
 981                                 result = FMT_5_6_5;
 982                                 goto out_word4;
 983                         }
 984                         goto out_unknown;
 985                 case 4:
 986                         if (desc->channel[0].size == 5 &&
 987                             desc->channel[1].size == 5 &&
 988                             desc->channel[2].size == 5 &&
 989                             desc->channel[3].size == 1) {
 990                                 result = FMT_1_5_5_5;
 991                                 goto out_word4;
 992                         }
 993                         if (desc->channel[0].size == 10 &&
 994                             desc->channel[1].size == 10 &&
 995                             desc->channel[2].size == 10 &&
 996                             desc->channel[3].size == 2) {
 997                                 result = FMT_2_10_10_10;
 998                                 goto out_word4;
 999                         }
1000                         goto out_unknown;
1001                 }
1002                 goto out_unknown;
1003         }
1004
1005         /* Find the first non-VOID channel. */
1006         for (i = 0; i < 4; i++) {
1007                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1008                         break;
1009                 }
1010         }
1011
1012         if (i == 4)
1013                 goto out_unknown;
1014
1015         /* uniform formats */
1016         switch (desc->channel[i].type) {
1017         case UTIL_FORMAT_TYPE_UNSIGNED:
1018         case UTIL_FORMAT_TYPE_SIGNED:
1019                 if (!desc->channel[i].normalized &&
1020                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1021                         goto out_unknown;
1022                 }
1023
1024                 switch (desc->channel[i].size) {
1025                 case 4:
1026                         switch (desc->nr_channels) {
1027                         case 2:
1028                                 result = FMT_4_4;
1029                                 goto out_word4;
1030                         case 4:
1031                                 result = FMT_4_4_4_4;
1032                                 goto out_word4;
1033                         }
1034                         goto out_unknown;
1035                 case 8:
1036                         switch (desc->nr_channels) {
1037                         case 1:
1038                                 result = FMT_8;
1039                                 goto out_word4;
1040                         case 2:
1041                                 result = FMT_8_8;
1042                                 goto out_word4;
1043                         case 4:
1044                                 result = FMT_8_8_8_8;
1045                                 goto out_word4;
1046                         }
1047                         goto out_unknown;
1048                 case 16:
1049                         switch (desc->nr_channels) {
1050                         case 1:
1051                                 result = FMT_16;
1052                                 goto out_word4;
1053                         case 2:
1054                                 result = FMT_16_16;
1055                                 goto out_word4;
1056                         case 4:
1057                                 result = FMT_16_16_16_16;
1058                                 goto out_word4;
1059                         }
1060                         goto out_unknown;
1061                 case 32:
1062                         switch (desc->nr_channels) {
1063                         case 1:
1064                                 result = FMT_32;
1065                                 goto out_word4;
1066                         case 2:
1067                                 result = FMT_32_32;
1068                                 goto out_word4;
1069                         case 4:
1070                                 result = FMT_32_32_32_32;
1071                                 goto out_word4;
1072                         }
1073                 }
1074                 goto out_unknown;
1075
1076         case UTIL_FORMAT_TYPE_FLOAT:
1077                 switch (desc->channel[i].size) {
1078                 case 16:
1079                         switch (desc->nr_channels) {
1080                         case 1:
1081                                 result = FMT_16_FLOAT;
1082                                 goto out_word4;
1083                         case 2:
1084                                 result = FMT_16_16_FLOAT;
1085                                 goto out_word4;
1086                         case 4:
1087                                 result = FMT_16_16_16_16_FLOAT;
1088                                 goto out_word4;
1089                         }
1090                         goto out_unknown;
1091                 case 32:
1092                         switch (desc->nr_channels) {
1093                         case 1:
1094                                 result = FMT_32_FLOAT;
1095                                 goto out_word4;
1096                         case 2:
1097                                 result = FMT_32_32_FLOAT;
1098                                 goto out_word4;
1099                         case 4:
1100                                 result = FMT_32_32_32_32_FLOAT;
1101                                 goto out_word4;
1102                         }
1103                 }
1104                 goto out_unknown;
1105         }
1106
1107 out_word4:
1108         if (word4_p)
1109                 *word4_p = word4;
1110         if (yuv_format_p)
1111                 *yuv_format_p = yuv_format;
1112         return result;
1113 out_unknown:
1114         /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1115         return ~0;
1116 }