src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_math.h>
  31 #include <util/u_inlines.h>
  32 #include <util/u_memory.h>
  33 #include "state_tracker/drm_driver.h"
  34 #include "r600_screen.h"
  35 #include "r600_context.h"
  36 #include "r600_resource.h"
  37 #include "r600_state_inlines.h"
  38 #include "r600d.h"
  39
  40 extern struct u_resource_vtbl r600_texture_vtbl;
  41
  42 /* Copy from a tiled texture to a detiled one. */
  43 static void r600_copy_from_tiled_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  44 {
  45         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  46         struct pipe_resource *texture = transfer->resource;
  47         struct pipe_subresource subdst;
  48
  49         subdst.face = 0;
  50         subdst.level = 0;
  51         ctx->resource_copy_region(ctx, rtransfer->linear_texture,
  52                                 subdst, 0, 0, 0, texture, transfer->sr,
  53                                 transfer->box.x, transfer->box.y, transfer->box.z,
  54                                 transfer->box.width, transfer->box.height);
  55 }
  56
  57 static unsigned long r600_texture_get_offset(struct r600_resource_texture *rtex,
  58                                         unsigned level, unsigned zslice,
  59                                         unsigned face)
  60 {
  61         unsigned long offset = rtex->offset[level];
  62
  63         switch (rtex->resource.base.b.target) {
  64         case PIPE_TEXTURE_3D:
  65                 assert(face == 0);
  66                 return offset + zslice * rtex->layer_size[level];
  67         case PIPE_TEXTURE_CUBE:
  68                 assert(zslice == 0);
  69                 return offset + face * rtex->layer_size[level];
  70         default:
  71                 assert(zslice == 0 && face == 0);
  72                 return offset;
  73         }
  74 }
  75
  76 static void r600_setup_miptree(struct r600_resource_texture *rtex, enum chip_class chipc)
  77 {
  78         struct pipe_resource *ptex = &rtex->resource.base.b;
  79         unsigned long w, h, pitch, size, layer_size, i, offset;
  80
  81         rtex->bpt = util_format_get_blocksize(ptex->format);
  82         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
  83                 w = u_minify(ptex->width0, i);
  84                 h = u_minify(ptex->height0, i);
  85                 h = util_next_power_of_two(h);
  86                 pitch = util_format_get_stride(ptex->format, align(w, 64));
  87                 pitch = align(pitch, 256);
  88                 layer_size = pitch * h;
  89                 if (ptex->target == PIPE_TEXTURE_CUBE) {
  90                         if (chipc == R700)
  91                                 size = layer_size * 8;
  92                         else
  93                                 size = layer_size * 6;
  94                 }
  95                 else
  96                         size = layer_size * u_minify(ptex->depth0, i);
  97                 rtex->offset[i] = offset;
  98                 rtex->layer_size[i] = layer_size;
  99                 rtex->pitch[i] = pitch;
 100                 rtex->width[i] = w;
 101                 rtex->height[i] = h;
 102                 offset += size;
 103         }
 104         rtex->size = offset;
 105 }
 106
 107 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 108                                                 const struct pipe_resource *templ)
 109 {
 110         struct r600_resource_texture *rtex;
 111         struct r600_resource *resource;
 112         struct radeon *radeon = (struct radeon *)screen->winsys;
 113
 114         rtex = CALLOC_STRUCT(r600_resource_texture);
 115         if (!rtex) {
 116                 return NULL;
 117         }
 118         resource = &rtex->resource;
 119         resource->base.b = *templ;
 120         resource->base.vtbl = &r600_texture_vtbl;
 121         pipe_reference_init(&resource->base.b.reference, 1);
 122         resource->base.b.screen = screen;
 123         r600_setup_miptree(rtex, radeon_get_family_class(radeon));
 124
 125         /* FIXME alignment 4096 enought ? too much ? */
 126         resource->domain = r600_domain_from_usage(resource->base.b.bind);
 127         resource->size = rtex->size;
 128         resource->bo = radeon_ws_bo(radeon, rtex->size, 4096, 0);
 129         if (resource->bo == NULL) {
 130                 FREE(rtex);
 131                 return NULL;
 132         }
 133         return &resource->base.b;
 134 }
 135
 136 static void r600_texture_destroy_state(struct pipe_resource *ptexture)
 137 {
 138         struct r600_resource_texture *rtexture = (struct r600_resource_texture*)ptexture;
 139
 140         for (int i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
 141                 radeon_state_fini(&rtexture->scissor[i]);
 142                 radeon_state_fini(&rtexture->db[i]);
 143                 for (int j = 0; j < 8; j++) {
 144                         radeon_state_fini(&rtexture->cb[j][i]);
 145                 }
 146         }
 147 }
 148
 149 static void r600_texture_destroy(struct pipe_screen *screen,
 150                                  struct pipe_resource *ptex)
 151 {
 152         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 153         struct r600_resource *resource = &rtex->resource;
 154         struct radeon *radeon = (struct radeon *)screen->winsys;
 155
 156         if (resource->bo) {
 157                 radeon_ws_bo_reference(radeon, &resource->bo, NULL);
 158         }
 159         if (rtex->uncompressed) {
 160                 radeon_ws_bo_reference(radeon, &rtex->uncompressed, NULL);
 161         }
 162         r600_texture_destroy_state(ptex);
 163         FREE(rtex);
 164 }
 165
 166 static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen,
 167                                                 struct pipe_resource *texture,
 168                                                 unsigned face, unsigned level,
 169                                                 unsigned zslice, unsigned flags)
 170 {
 171         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 172         struct pipe_surface *surface = CALLOC_STRUCT(pipe_surface);
 173         unsigned long offset;
 174
 175         if (surface == NULL)
 176                 return NULL;
 177         offset = r600_texture_get_offset(rtex, level, zslice, face);
 178         pipe_reference_init(&surface->reference, 1);
 179         pipe_resource_reference(&surface->texture, texture);
 180         surface->format = texture->format;
 181         surface->width = u_minify(texture->width0, level);
 182         surface->height = u_minify(texture->height0, level);
 183         surface->offset = offset;
 184         surface->usage = flags;
 185         surface->zslice = zslice;
 186         surface->texture = texture;
 187         surface->face = face;
 188         surface->level = level;
 189         return surface;
 190 }
 191
 192 static void r600_tex_surface_destroy(struct pipe_surface *surface)
 193 {
 194         pipe_resource_reference(&surface->texture, NULL);
 195         FREE(surface);
 196 }
 197
 198 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 199                                                const struct pipe_resource *templ,
 200                                                struct winsys_handle *whandle)
 201 {
 202         struct radeon *rw = (struct radeon*)screen->winsys;
 203         struct r600_resource_texture *rtex;
 204         struct r600_resource *resource;
 205         struct radeon_ws_bo *bo = NULL;
 206
 207         /* Support only 2D textures without mipmaps */
 208         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 209               templ->depth0 != 1 || templ->last_level != 0)
 210                 return NULL;
 211
 212         rtex = CALLOC_STRUCT(r600_resource_texture);
 213         if (rtex == NULL)
 214                 return NULL;
 215
 216         bo = radeon_ws_bo_handle(rw, whandle->handle);
 217         if (bo == NULL) {
 218                 FREE(rtex);
 219                 return NULL;
 220         }
 221
 222         resource = &rtex->resource;
 223         resource->base.b = *templ;
 224         resource->base.vtbl = &r600_texture_vtbl;
 225         pipe_reference_init(&resource->base.b.reference, 1);
 226         resource->base.b.screen = screen;
 227         resource->bo = bo;
 228         rtex->depth = 0;
 229         rtex->pitch_override = whandle->stride;
 230         rtex->bpt = util_format_get_blocksize(templ->format);
 231         rtex->pitch[0] = whandle->stride;
 232         rtex->width[0] = templ->width0;
 233         rtex->height[0] = templ->height0;
 234         rtex->offset[0] = 0;
 235         rtex->size = align(rtex->pitch[0] * templ->height0, 64);
 236
 237         return &resource->base.b;
 238 }
 239
 240 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 241                                                 struct pipe_resource *texture,
 242                                                 unsigned face, unsigned level)
 243 {
 244         /* FIXME */
 245         return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 246 }
 247
 248 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 249                                                 struct pipe_resource *texture,
 250                                                 struct pipe_subresource sr,
 251                                                 unsigned usage,
 252                                                 const struct pipe_box *box)
 253 {
 254         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 255         struct pipe_resource resource;
 256         struct r600_transfer *trans;
 257
 258         trans = CALLOC_STRUCT(r600_transfer);
 259         if (trans == NULL)
 260                 return NULL;
 261         pipe_resource_reference(&trans->transfer.resource, texture);
 262         trans->transfer.sr = sr;
 263         trans->transfer.usage = usage;
 264         trans->transfer.box = *box;
 265         trans->transfer.stride = rtex->pitch[sr.level];
 266         trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
 267         if (rtex->tilled && !rtex->depth) {
 268                 resource.target = PIPE_TEXTURE_2D;
 269                 resource.format = texture->format;
 270                 resource.width0 = box->width;
 271                 resource.height0 = box->height;
 272                 resource.depth0 = 0;
 273                 resource.last_level = 0;
 274                 resource.nr_samples = 0;
 275                 resource.usage = PIPE_USAGE_DYNAMIC;
 276                 resource.bind = 0;
 277                 resource.flags = 0;
 278                 /* For texture reading, the temporary (detiled) texture is used as
 279                  * a render target when blitting from a tiled texture. */
 280                 if (usage & PIPE_TRANSFER_READ) {
 281                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 282                 }
 283                 /* For texture writing, the temporary texture is used as a sampler
 284                  * when blitting into a tiled texture. */
 285                 if (usage & PIPE_TRANSFER_WRITE) {
 286                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 287                 }
 288                 /* Create the temporary texture. */
 289                 trans->linear_texture = ctx->screen->resource_create(ctx->screen, &resource);
 290                 if (trans->linear_texture == NULL) {
 291                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 292                         pipe_resource_reference(&trans->transfer.resource, NULL);
 293                         FREE(trans);
 294                         return NULL;
 295                 }
 296                 if (usage & PIPE_TRANSFER_READ) {
 297                         /* We cannot map a tiled texture directly because the data is
 298                          * in a different order, therefore we do detiling using a blit. */
 299                         r600_copy_from_tiled_texture(ctx, trans);
 300                         /* Always referenced in the blit. */
 301                         ctx->flush(ctx, 0, NULL);
 302                 }
 303         }
 304         return &trans->transfer;
 305 }
 306
 307 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 308                                    struct pipe_transfer *transfer)
 309 {
 310         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 311
 312         if (rtransfer->linear_texture) {
 313                 pipe_resource_reference(&rtransfer->linear_texture, NULL);
 314         }
 315         pipe_resource_reference(&transfer->resource, NULL);
 316         FREE(transfer);
 317 }
 318
 319 void* r600_texture_transfer_map(struct pipe_context *ctx,
 320                                 struct pipe_transfer* transfer)
 321 {
 322         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 323         struct radeon_ws_bo *bo;
 324         enum pipe_format format = transfer->resource->format;
 325         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 326         struct r600_resource_texture *rtex;
 327         unsigned long offset = 0;
 328         char *map;
 329         int r;
 330
 331         if (rtransfer->linear_texture) {
 332                 bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
 333         } else {
 334                 rtex = (struct r600_resource_texture*)transfer->resource;
 335                 if (rtex->depth && radeon_get_family_class(radeon) != EVERGREEN) {
 336                         r = r600_texture_from_depth(ctx, rtex, transfer->sr.level);
 337                         if (r) {
 338                                 return NULL;
 339                         }
 340                         r600_flush(ctx, 0, NULL);
 341                         bo = rtex->uncompressed;
 342                 } else {
 343                         bo = ((struct r600_resource *)transfer->resource)->bo;
 344                 }
 345                 offset = rtransfer->offset +
 346                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 347                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 348         }
 349         map = radeon_ws_bo_map(radeon, bo, 0, r600_context(ctx));
 350         if (!map) {
 351                 return NULL;
 352         }
 353
 354         return map + offset;
 355 }
 356
 357 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 358                                  struct pipe_transfer* transfer)
 359 {
 360         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 361         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 362         struct r600_resource_texture *rtex;
 363         struct radeon_ws_bo *bo;
 364
 365         if (rtransfer->linear_texture) {
 366                 bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
 367         } else {
 368                 rtex = (struct r600_resource_texture*)transfer->resource;
 369                 if (rtex->depth) {
 370                         bo = rtex->uncompressed;
 371                 } else {
 372                         bo = ((struct r600_resource *)transfer->resource)->bo;
 373                 }
 374         }
 375         radeon_ws_bo_unmap(radeon, bo);
 376 }
 377
 378 struct u_resource_vtbl r600_texture_vtbl =
 379 {
 380         u_default_resource_get_handle,  /* get_handle */
 381         r600_texture_destroy,           /* resource_destroy */
 382         r600_texture_is_referenced,     /* is_resource_referenced */
 383         r600_texture_get_transfer,      /* get_transfer */
 384         r600_texture_transfer_destroy,  /* transfer_destroy */
 385         r600_texture_transfer_map,      /* transfer_map */
 386         u_default_transfer_flush_region,/* transfer_flush_region */
 387         r600_texture_transfer_unmap,    /* transfer_unmap */
 388         u_default_transfer_inline_write /* transfer_inline_write */
 389 };
 390
 391 void r600_init_screen_texture_functions(struct pipe_screen *screen)
 392 {
 393         screen->get_tex_surface = r600_get_tex_surface;
 394         screen->tex_surface_destroy = r600_tex_surface_destroy;
 395 }
 396
 397 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 398                 const unsigned char *swizzle_view)
 399 {
 400         unsigned i;
 401         unsigned char swizzle[4];
 402         unsigned result = 0;
 403         const uint32_t swizzle_shift[4] = {
 404                 16, 19, 22, 25,
 405         };
 406         const uint32_t swizzle_bit[4] = {
 407                 0, 1, 2, 3,
 408         };
 409
 410         if (swizzle_view) {
 411                 /* Combine two sets of swizzles. */
 412                 for (i = 0; i < 4; i++) {
 413                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 414                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 415                 }
 416         } else {
 417                 memcpy(swizzle, swizzle_format, 4);
 418         }
 419
 420         /* Get swizzle. */
 421         for (i = 0; i < 4; i++) {
 422                 switch (swizzle[i]) {
 423                 case UTIL_FORMAT_SWIZZLE_Y:
 424                         result |= swizzle_bit[1] << swizzle_shift[i];
 425                         break;
 426                 case UTIL_FORMAT_SWIZZLE_Z:
 427                         result |= swizzle_bit[2] << swizzle_shift[i];
 428                         break;
 429                 case UTIL_FORMAT_SWIZZLE_W:
 430                         result |= swizzle_bit[3] << swizzle_shift[i];
 431                         break;
 432                 case UTIL_FORMAT_SWIZZLE_0:
 433                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 434                         break;
 435                 case UTIL_FORMAT_SWIZZLE_1:
 436                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 437                         break;
 438                 default: /* UTIL_FORMAT_SWIZZLE_X */
 439                         result |= swizzle_bit[0] << swizzle_shift[i];
 440                 }
 441         }
 442         return result;
 443 }
 444
 445 /* texture format translate */
 446 uint32_t r600_translate_texformat(enum pipe_format format,
 447                                   const unsigned char *swizzle_view,
 448                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 449 {
 450         uint32_t result = 0, word4 = 0, yuv_format = 0;
 451         const struct util_format_description *desc;
 452         boolean uniform = TRUE;
 453         int i;
 454         const uint32_t sign_bit[4] = {
 455                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 456                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 457                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 458                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 459         };
 460         desc = util_format_description(format);
 461
 462         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 463
 464         /* Colorspace (return non-RGB formats directly). */
 465         switch (desc->colorspace) {
 466                 /* Depth stencil formats */
 467         case UTIL_FORMAT_COLORSPACE_ZS:
 468                 switch (format) {
 469                 case PIPE_FORMAT_Z16_UNORM:
 470                         result = V_0280A0_COLOR_16;
 471                         goto out_word4;
 472                 case PIPE_FORMAT_Z24X8_UNORM:
 473                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 474                         result = V_0280A0_COLOR_8_24;
 475                         goto out_word4;
 476                 case PIPE_FORMAT_X8Z24_UNORM:
 477                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 478                         result = V_0280A0_COLOR_24_8;
 479                         goto out_word4;
 480                 default:
 481                         goto out_unknown;
 482                 }
 483
 484         case UTIL_FORMAT_COLORSPACE_YUV:
 485                 yuv_format |= (1 << 30);
 486                 switch (format) {
 487                 case PIPE_FORMAT_UYVY:
 488                 case PIPE_FORMAT_YUYV:
 489                 default:
 490                         break;
 491                 }
 492                 goto out_unknown; /* TODO */
 493
 494         case UTIL_FORMAT_COLORSPACE_SRGB:
 495                 word4 |= S_038010_FORCE_DEGAMMA(1);
 496                 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
 497                         goto out_unknown; /* fails for some reason - TODO */
 498                 break;
 499
 500         default:
 501                 break;
 502         }
 503
 504         /* S3TC formats. TODO */
 505         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 506                 goto out_unknown;
 507         }
 508
 509
 510         for (i = 0; i < desc->nr_channels; i++) {
 511                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 512                         word4 |= sign_bit[i];
 513                 }
 514         }
 515
 516         /* R8G8Bx_SNORM - TODO CxV8U8 */
 517
 518         /* RGTC - TODO */
 519
 520         /* See whether the components are of the same size. */
 521         for (i = 1; i < desc->nr_channels; i++) {
 522                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 523         }
 524
 525         /* Non-uniform formats. */
 526         if (!uniform) {
 527                 switch(desc->nr_channels) {
 528                 case 3:
 529                         if (desc->channel[0].size == 5 &&
 530                             desc->channel[1].size == 6 &&
 531                             desc->channel[2].size == 5) {
 532                                 result = V_0280A0_COLOR_5_6_5;
 533                                 goto out_word4;
 534                         }
 535                         goto out_unknown;
 536                 case 4:
 537                         if (desc->channel[0].size == 5 &&
 538                             desc->channel[1].size == 5 &&
 539                             desc->channel[2].size == 5 &&
 540                             desc->channel[3].size == 1) {
 541                                 result = V_0280A0_COLOR_1_5_5_5;
 542                                 goto out_word4;
 543                         }
 544                         if (desc->channel[0].size == 10 &&
 545                             desc->channel[1].size == 10 &&
 546                             desc->channel[2].size == 10 &&
 547                             desc->channel[3].size == 2) {
 548                                 result = V_0280A0_COLOR_10_10_10_2;
 549                                 goto out_word4;
 550                         }
 551                         goto out_unknown;
 552                 }
 553                 goto out_unknown;
 554         }
 555
 556         /* uniform formats */
 557         switch (desc->channel[0].type) {
 558         case UTIL_FORMAT_TYPE_UNSIGNED:
 559         case UTIL_FORMAT_TYPE_SIGNED:
 560                 if (!desc->channel[0].normalized &&
 561                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 562                         goto out_unknown;
 563                 }
 564
 565                 switch (desc->channel[0].size) {
 566                 case 4:
 567                         switch (desc->nr_channels) {
 568                         case 2:
 569                                 result = V_0280A0_COLOR_4_4;
 570                                 goto out_word4;
 571                         case 4:
 572                                 result = V_0280A0_COLOR_4_4_4_4;
 573                                 goto out_word4;
 574                         }
 575                         goto out_unknown;
 576                 case 8:
 577                         switch (desc->nr_channels) {
 578                         case 1:
 579                                 result = V_0280A0_COLOR_8;
 580                                 goto out_word4;
 581                         case 2:
 582                                 result = V_0280A0_COLOR_8_8;
 583                                 goto out_word4;
 584                         case 4:
 585                                 result = V_0280A0_COLOR_8_8_8_8;
 586                                 goto out_word4;
 587                         }
 588                         goto out_unknown;
 589                 case 16:
 590                         switch (desc->nr_channels) {
 591                         case 1:
 592                                 result = V_0280A0_COLOR_16;
 593                                 goto out_word4;
 594                         case 2:
 595                                 result = V_0280A0_COLOR_16_16;
 596                                 goto out_word4;
 597                         case 4:
 598                                 result = V_0280A0_COLOR_16_16_16_16;
 599                                 goto out_word4;
 600                         }
 601                 }
 602                 goto out_unknown;
 603
 604         case UTIL_FORMAT_TYPE_FLOAT:
 605                 switch (desc->channel[0].size) {
 606                 case 16:
 607                         switch (desc->nr_channels) {
 608                         case 1:
 609                                 result = V_0280A0_COLOR_16_FLOAT;
 610                                 goto out_word4;
 611                         case 2:
 612                                 result = V_0280A0_COLOR_16_16_FLOAT;
 613                                 goto out_word4;
 614                         case 4:
 615                                 result = V_0280A0_COLOR_16_16_16_16_FLOAT;
 616                                 goto out_word4;
 617                         }
 618                         goto out_unknown;
 619                 case 32:
 620                         switch (desc->nr_channels) {
 621                         case 1:
 622                                 result = V_0280A0_COLOR_32_FLOAT;
 623                                 goto out_word4;
 624                         case 2:
 625                                 result = V_0280A0_COLOR_32_32_FLOAT;
 626                                 goto out_word4;
 627                         case 4:
 628                                 result = V_0280A0_COLOR_32_32_32_32_FLOAT;
 629                                 goto out_word4;
 630                         }
 631                 }
 632
 633         }
 634 out_word4:
 635         if (word4_p)
 636                 *word4_p = word4;
 637         if (yuv_format_p)
 638                 *yuv_format_p = yuv_format;
 639         return result;
 640 out_unknown:
 641 //      R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
 642         return ~0;
 643 }
 644
 645 int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 646 {
 647         struct r600_screen *rscreen = r600_screen(ctx->screen);
 648         int r;
 649
 650         if (!rtexture->depth) {
 651                 /* This shouldn't happen maybe print a warning */
 652                 return 0;
 653         }
 654         if (rtexture->uncompressed && !rtexture->dirty) {
 655                 /* Uncompressed bo already in good state */
 656                 return 0;
 657         }
 658
 659         /* allocate uncompressed texture */
 660         if (rtexture->uncompressed == NULL) {
 661                 rtexture->uncompressed = radeon_ws_bo(rscreen->rw, rtexture->size, 4096, 0);
 662                 if (rtexture->uncompressed == NULL) {
 663                         return -ENOMEM;
 664                 }
 665         }
 666
 667         /* render a rectangle covering whole buffer to uncompress depth */
 668         r = r600_blit_uncompress_depth(ctx, rtexture, level);
 669         if (r) {
 670                 return r;
 671         }
 672
 673         rtexture->dirty = 0;
 674         return 0;
 675 }
 676
 677
 678
 679 int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 680 {
 681         struct r600_screen *rscreen = r600_screen(ctx->screen);
 682         struct r600_context *rctx = r600_context(ctx);
 683
 684         if (!rtexture->scissor[level].cpm4) {
 685                 rctx->vtbl->texture_state_scissor(rscreen, rtexture, level);
 686         }
 687         return 0;
 688 }
 689
 690 int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
 691 {
 692         struct r600_screen *rscreen = r600_screen(ctx->screen);
 693         struct r600_context *rctx = r600_context(ctx);
 694
 695         if (!rtexture->cb[cb][level].cpm4) {
 696                 rctx->vtbl->texture_state_cb(rscreen, rtexture, cb, level);
 697         }
 698         return 0;
 699 }
 700
 701 int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 702 {
 703         struct r600_screen *rscreen = r600_screen(ctx->screen);
 704         struct r600_context *rctx = r600_context(ctx);
 705
 706         if (!rtexture->db[level].cpm4) {
 707                 rctx->vtbl->texture_state_db(rscreen, rtexture, level);
 708         }
 709         return 0;
 710 }
 711
 712 int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 713 {
 714         struct r600_screen *rscreen = r600_screen(ctx->screen);
 715         struct r600_context *rctx = r600_context(ctx);
 716
 717         if (!rtexture->viewport[level].cpm4) {
 718                 rctx->vtbl->texture_state_viewport(rscreen, rtexture, level);
 719         }
 720         return 0;
 721 }