src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_math.h>
  31 #include <util/u_inlines.h>
  32 #include <util/u_memory.h>
  33 #include "state_tracker/drm_driver.h"
  34 #include "pipebuffer/pb_buffer.h"
  35 #include "r600_pipe.h"
  36 #include "r600_resource.h"
  37 #include "r600_state_inlines.h"
  38 #include "r600d.h"
  39 #include "r600_formats.h"
  40
  41 extern struct u_resource_vtbl r600_texture_vtbl;
  42
  43 /* Copy from a full GPU texture to a transfer's staging one. */
  44 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  45 {
  46         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  47         struct pipe_resource *texture = transfer->resource;
  48
  49         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  50                                 0, 0, 0, 0, texture, transfer->level,
  51                                 &transfer->box);
  52 }
  53
  54
  55 /* Copy from a transfer's staging texture to a full GPU one. */
  56 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  57 {
  58         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  59         struct pipe_resource *texture = transfer->resource;
  60         struct pipe_box sbox;
  61
  62         sbox.x = sbox.y = sbox.z = 0;
  63         sbox.width = transfer->box.width;
  64         sbox.height = transfer->box.height;
  65         /* XXX that might be wrong */
  66         sbox.depth = 1;
  67         ctx->resource_copy_region(ctx, texture, transfer->level,
  68                                   transfer->box.x, transfer->box.y, transfer->box.z,
  69                                   rtransfer->staging_texture,
  70                                   0, &sbox);
  71
  72         ctx->flush(ctx, 0, NULL);
  73 }
  74
  75 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  76                                         unsigned level, unsigned layer)
  77 {
  78         unsigned offset = rtex->offset[level];
  79
  80         switch (rtex->resource.base.b.target) {
  81         case PIPE_TEXTURE_3D:
  82         case PIPE_TEXTURE_CUBE:
  83                 return offset + layer * rtex->layer_size[level];
  84         default:
  85                 assert(layer == 0);
  86                 return offset;
  87         }
  88 }
  89
  90 static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
  91                                          enum pipe_format format,
  92                                          unsigned array_mode)
  93 {
  94         struct r600_screen* rscreen = (struct r600_screen *)screen;
  95         unsigned pixsize = util_format_get_blocksize(format);
  96         int p_align;
  97
  98         switch(array_mode) {
  99         case V_038000_ARRAY_1D_TILED_THIN1:
 100                 p_align = MAX2(8,
 101                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
 102                 break;
 103         case V_038000_ARRAY_2D_TILED_THIN1:
 104                 p_align = MAX2(rscreen->tiling_info->num_banks,
 105                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 106                                 rscreen->tiling_info->num_banks)) * 8;
 107                 break;
 108         case V_038000_ARRAY_LINEAR_GENERAL:
 109         default:
 110                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 111                 break;
 112         }
 113         return p_align;
 114 }
 115
 116 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 117                                           unsigned array_mode)
 118 {
 119         struct r600_screen* rscreen = (struct r600_screen *)screen;
 120         int h_align;
 121
 122         switch (array_mode) {
 123         case V_038000_ARRAY_2D_TILED_THIN1:
 124                 h_align = rscreen->tiling_info->num_channels * 8;
 125                 break;
 126         case V_038000_ARRAY_1D_TILED_THIN1:
 127                 h_align = 8;
 128                 break;
 129         default:
 130                 h_align = 1;
 131                 break;
 132         }
 133         return h_align;
 134 }
 135
 136 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 137                                         enum pipe_format format,
 138                                         unsigned array_mode)
 139 {
 140         struct r600_screen* rscreen = (struct r600_screen *)screen;
 141         unsigned pixsize = util_format_get_blocksize(format);
 142         int p_align = r600_get_pixel_alignment(screen, format, array_mode);
 143         int h_align = r600_get_height_alignment(screen, array_mode);
 144         int b_align;
 145
 146         switch (array_mode) {
 147         case V_038000_ARRAY_2D_TILED_THIN1:
 148                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 149                                p_align * pixsize * h_align);
 150                 break;
 151         case V_038000_ARRAY_1D_TILED_THIN1:
 152         default:
 153                 b_align = rscreen->tiling_info->group_bytes;
 154                 break;
 155         }
 156         return b_align;
 157 }
 158
 159 static unsigned mip_minify(unsigned size, unsigned level)
 160 {
 161         unsigned val;
 162         val = u_minify(size, level);
 163         if (level > 0)
 164                 val = util_next_power_of_two(val);
 165         return val;
 166 }
 167
 168 static unsigned r600_texture_get_stride(struct pipe_screen *screen,
 169                                         struct r600_resource_texture *rtex,
 170                                         unsigned level)
 171 {
 172         struct pipe_resource *ptex = &rtex->resource.base.b;
 173         unsigned width, stride, tile_width;
 174
 175         if (rtex->pitch_override)
 176                 return rtex->pitch_override;
 177
 178         width = mip_minify(ptex->width0, level);
 179         if (util_format_is_plain(ptex->format)) {
 180                 tile_width = r600_get_pixel_alignment(screen, ptex->format,
 181                                                       rtex->array_mode[level]);
 182                 width = align(width, tile_width);
 183         }
 184         stride = util_format_get_stride(ptex->format, width);
 185
 186         return stride;
 187 }
 188
 189 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 190                                           struct r600_resource_texture *rtex,
 191                                           unsigned level)
 192 {
 193         struct pipe_resource *ptex = &rtex->resource.base.b;
 194         unsigned height, tile_height;
 195
 196         height = mip_minify(ptex->height0, level);
 197         if (util_format_is_plain(ptex->format)) {
 198                 tile_height = r600_get_height_alignment(screen,
 199                                                         rtex->array_mode[level]);
 200                 height = align(height, tile_height);
 201         }
 202         return util_format_get_nblocksy(ptex->format, height);
 203 }
 204
 205 /* Get a width in pixels from a stride in bytes. */
 206 static unsigned pitch_to_width(enum pipe_format format, unsigned pitch_in_bytes)
 207 {
 208         return (pitch_in_bytes / util_format_get_blocksize(format)) *
 209                 util_format_get_blockwidth(format);
 210 }
 211
 212 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 213                                         struct r600_resource_texture *rtex,
 214                                         unsigned level, unsigned array_mode)
 215 {
 216         struct pipe_resource *ptex = &rtex->resource.base.b;
 217
 218         switch (array_mode) {
 219         case V_0280A0_ARRAY_LINEAR_GENERAL:
 220         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 221         case V_0280A0_ARRAY_1D_TILED_THIN1:
 222         default:
 223                 rtex->array_mode[level] = array_mode;
 224                 break;
 225         case V_0280A0_ARRAY_2D_TILED_THIN1:
 226         {
 227                 unsigned w, h, tile_height, tile_width;
 228
 229                 tile_height = r600_get_height_alignment(screen, array_mode);
 230                 tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode);
 231
 232                 w = mip_minify(ptex->width0, level);
 233                 h = mip_minify(ptex->height0, level);
 234                 if (w < tile_width || h < tile_height)
 235                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 236                 else
 237                         rtex->array_mode[level] = array_mode;
 238         }
 239         break;
 240         }
 241 }
 242
 243 static void r600_setup_miptree(struct pipe_screen *screen,
 244                                struct r600_resource_texture *rtex,
 245                                unsigned array_mode)
 246 {
 247         struct pipe_resource *ptex = &rtex->resource.base.b;
 248         struct radeon *radeon = (struct radeon *)screen->winsys;
 249         enum chip_class chipc = r600_get_family_class(radeon);
 250         unsigned pitch, size, layer_size, i, offset;
 251         unsigned nblocksy;
 252
 253         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 254                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 255
 256                 pitch = r600_texture_get_stride(screen, rtex, i);
 257                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 258
 259                 layer_size = pitch * nblocksy;
 260
 261                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 262                         if (chipc >= R700)
 263                                 size = layer_size * 8;
 264                         else
 265                                 size = layer_size * 6;
 266                 }
 267                 else
 268                         size = layer_size * u_minify(ptex->depth0, i);
 269                 /* align base image and start of miptree */
 270                 if ((i == 0) || (i == 1))
 271                         offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
 272                 rtex->offset[i] = offset;
 273                 rtex->layer_size[i] = layer_size;
 274                 rtex->pitch_in_bytes[i] = pitch;
 275                 rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
 276                 offset += size;
 277         }
 278         rtex->size = offset;
 279 }
 280
 281 static struct r600_resource_texture *
 282 r600_texture_create_object(struct pipe_screen *screen,
 283                            const struct pipe_resource *base,
 284                            unsigned array_mode,
 285                            unsigned pitch_in_bytes_override,
 286                            unsigned max_buffer_size,
 287                            struct r600_bo *bo)
 288 {
 289         struct r600_resource_texture *rtex;
 290         struct r600_resource *resource;
 291         struct radeon *radeon = (struct radeon *)screen->winsys;
 292
 293         rtex = CALLOC_STRUCT(r600_resource_texture);
 294         if (rtex == NULL)
 295                 return NULL;
 296
 297         resource = &rtex->resource;
 298         resource->base.b = *base;
 299         resource->base.vtbl = &r600_texture_vtbl;
 300         pipe_reference_init(&resource->base.b.reference, 1);
 301         resource->base.b.screen = screen;
 302         resource->bo = bo;
 303         rtex->pitch_override = pitch_in_bytes_override;
 304
 305         if (util_format_is_depth_or_stencil(base->format))
 306                 rtex->depth = 1;
 307
 308         if (array_mode)
 309                 rtex->tiled = 1;
 310         r600_setup_miptree(screen, rtex, array_mode);
 311
 312         resource->size = rtex->size;
 313
 314         if (!resource->bo) {
 315                 struct pipe_resource *ptex = &rtex->resource.base.b;
 316                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 317
 318                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 319                 if (!resource->bo) {
 320                         FREE(rtex);
 321                         return NULL;
 322                 }
 323         }
 324         return rtex;
 325 }
 326
 327 /* Figure out whether u_blitter will fallback to a transfer operation.
 328  * If so, don't use a staging resource.
 329  */
 330 static boolean permit_hardware_blit(struct pipe_screen *screen,
 331                                         const struct pipe_resource *res)
 332 {
 333         unsigned bind;
 334
 335         if (util_format_is_depth_or_stencil(res->format))
 336                 bind = PIPE_BIND_DEPTH_STENCIL;
 337         else
 338                 bind = PIPE_BIND_RENDER_TARGET;
 339
 340         /* See r600_resource_copy_region: there is something wrong
 341          * with depth resource copies at the moment so avoid them for
 342          * now.
 343          */
 344         if (util_format_get_component_bits(res->format,
 345                                 UTIL_FORMAT_COLORSPACE_ZS,
 346                                 0) != 0)
 347                 return FALSE;
 348
 349         if (!screen->is_format_supported(screen,
 350                                 res->format,
 351                                 res->target,
 352                                 res->nr_samples,
 353                                 bind, 0))
 354                 return FALSE;
 355
 356         if (!screen->is_format_supported(screen,
 357                                 res->format,
 358                                 res->target,
 359                                 res->nr_samples,
 360                                 PIPE_BIND_SAMPLER_VIEW, 0))
 361                 return FALSE;
 362
 363         return TRUE;
 364 }
 365
 366 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 367                                                 const struct pipe_resource *templ)
 368 {
 369         unsigned array_mode = 0;
 370         static int force_tiling = -1;
 371
 372         /* Would like some magic "get_bool_option_once" routine.
 373          */
 374         if (force_tiling == -1)
 375                 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
 376
 377         if (force_tiling && permit_hardware_blit(screen, templ)) {
 378                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 379                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 380                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 381                 }
 382         }
 383
 384         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 385                                                                   0, 0, NULL);
 386
 387 }
 388
 389 static void r600_texture_destroy(struct pipe_screen *screen,
 390                                  struct pipe_resource *ptex)
 391 {
 392         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 393         struct r600_resource *resource = &rtex->resource;
 394         struct radeon *radeon = (struct radeon *)screen->winsys;
 395
 396         if (rtex->flushed_depth_texture)
 397                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 398
 399         if (resource->bo) {
 400                 r600_bo_reference(radeon, &resource->bo, NULL);
 401         }
 402         FREE(rtex);
 403 }
 404
 405 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 406                                         struct pipe_resource *ptex,
 407                                         struct winsys_handle *whandle)
 408 {
 409         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 410         struct r600_resource *resource = &rtex->resource;
 411         struct radeon *radeon = (struct radeon *)screen->winsys;
 412
 413         return r600_bo_get_winsys_handle(radeon, resource->bo,
 414                         rtex->pitch_in_bytes[0], whandle);
 415 }
 416
 417 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 418                                                 struct pipe_resource *texture,
 419                                                 const struct pipe_surface *surf_tmpl)
 420 {
 421         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 422         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 423         unsigned tile_height;
 424         unsigned level = surf_tmpl->u.tex.level;
 425
 426         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 427         if (surface == NULL)
 428                 return NULL;
 429         /* XXX no offset */
 430 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 431         pipe_reference_init(&surface->base.reference, 1);
 432         pipe_resource_reference(&surface->base.texture, texture);
 433         surface->base.context = pipe;
 434         surface->base.format = surf_tmpl->format;
 435         surface->base.width = mip_minify(texture->width0, level);
 436         surface->base.height = mip_minify(texture->height0, level);
 437         surface->base.usage = surf_tmpl->usage;
 438         surface->base.texture = texture;
 439         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 440         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 441         surface->base.u.tex.level = level;
 442
 443         tile_height = r600_get_height_alignment(pipe->screen, rtex->array_mode[level]);
 444         surface->aligned_height = align(surface->base.height, tile_height);
 445         return &surface->base;
 446 }
 447
 448 static void r600_surface_destroy(struct pipe_context *pipe,
 449                                  struct pipe_surface *surface)
 450 {
 451         pipe_resource_reference(&surface->texture, NULL);
 452         FREE(surface);
 453 }
 454
 455
 456 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 457                                                const struct pipe_resource *templ,
 458                                                struct winsys_handle *whandle)
 459 {
 460         struct radeon *rw = (struct radeon*)screen->winsys;
 461         struct r600_bo *bo = NULL;
 462         unsigned array_mode = 0;
 463
 464         /* Support only 2D textures without mipmaps */
 465         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 466               templ->depth0 != 1 || templ->last_level != 0)
 467                 return NULL;
 468
 469         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 470         if (bo == NULL) {
 471                 return NULL;
 472         }
 473
 474         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 475                                                                   whandle->stride,
 476                                                                   0,
 477                                                                   bo);
 478 }
 479
 480 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 481                                                 struct pipe_resource *texture,
 482                                                 unsigned level, int layer)
 483 {
 484         /* FIXME */
 485         return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 486 }
 487
 488 int r600_texture_depth_flush(struct pipe_context *ctx,
 489                              struct pipe_resource *texture)
 490 {
 491         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 492         struct pipe_resource resource;
 493
 494         if (rtex->flushed_depth_texture)
 495                 goto out;
 496
 497         resource.target = PIPE_TEXTURE_2D;
 498         resource.format = texture->format;
 499         resource.width0 = texture->width0;
 500         resource.height0 = texture->height0;
 501         resource.depth0 = 1;
 502         resource.last_level = 0;
 503         resource.nr_samples = 0;
 504         resource.usage = PIPE_USAGE_DYNAMIC;
 505         resource.bind = 0;
 506         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 507
 508         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 509
 510         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 511         if (rtex->flushed_depth_texture == NULL) {
 512                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 513                 return -ENOMEM;
 514         }
 515
 516 out:
 517         /* XXX: only do this if the depth texture has actually changed:
 518          */
 519         r600_blit_uncompress_depth(ctx, rtex);
 520         return 0;
 521 }
 522
 523 /* Needs adjustment for pixelformat:
 524  */
 525 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 526 {
 527         return box->width * box->depth * box->height;
 528 };
 529
 530 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 531                                                 struct pipe_resource *texture,
 532                                                 unsigned level,
 533                                                 unsigned usage,
 534                                                 const struct pipe_box *box)
 535 {
 536         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 537         struct pipe_resource resource;
 538         struct r600_transfer *trans;
 539         int r;
 540         boolean use_staging_texture = FALSE;
 541
 542         /* We cannot map a tiled texture directly because the data is
 543          * in a different order, therefore we do detiling using a blit.
 544          *
 545          * Also, use a temporary in GTT memory for read transfers, as
 546          * the CPU is much happier reading out of cached system memory
 547          * than uncached VRAM.
 548          */
 549         if (rtex->tiled)
 550                 use_staging_texture = TRUE;
 551
 552         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 553                 use_staging_texture = TRUE;
 554
 555         /* XXX: Use a staging texture for uploads if the underlying BO
 556          * is busy.  No interface for checking that currently? so do
 557          * it eagerly whenever the transfer doesn't require a readback
 558          * and might block.
 559          */
 560         if ((usage & PIPE_TRANSFER_WRITE) &&
 561                         !(usage & (PIPE_TRANSFER_READ |
 562                                         PIPE_TRANSFER_DONTBLOCK |
 563                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 564                 use_staging_texture = TRUE;
 565
 566         if (!permit_hardware_blit(ctx->screen, texture) ||
 567                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 568                 use_staging_texture = FALSE;
 569
 570         trans = CALLOC_STRUCT(r600_transfer);
 571         if (trans == NULL)
 572                 return NULL;
 573         pipe_resource_reference(&trans->transfer.resource, texture);
 574         trans->transfer.level = level;
 575         trans->transfer.usage = usage;
 576         trans->transfer.box = *box;
 577         if (rtex->depth) {
 578                 /* XXX: only readback the rectangle which is being mapped?
 579                 */
 580                 /* XXX: when discard is true, no need to read back from depth texture
 581                 */
 582                 r = r600_texture_depth_flush(ctx, texture);
 583                 if (r < 0) {
 584                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 585                         pipe_resource_reference(&trans->transfer.resource, NULL);
 586                         FREE(trans);
 587                         return NULL;
 588                 }
 589         } else if (use_staging_texture) {
 590                 resource.target = PIPE_TEXTURE_2D;
 591                 resource.format = texture->format;
 592                 resource.width0 = box->width;
 593                 resource.height0 = box->height;
 594                 resource.depth0 = 1;
 595                 resource.array_size = 1;
 596                 resource.last_level = 0;
 597                 resource.nr_samples = 0;
 598                 resource.usage = PIPE_USAGE_STAGING;
 599                 resource.bind = 0;
 600                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 601                 /* For texture reading, the temporary (detiled) texture is used as
 602                  * a render target when blitting from a tiled texture. */
 603                 if (usage & PIPE_TRANSFER_READ) {
 604                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 605                 }
 606                 /* For texture writing, the temporary texture is used as a sampler
 607                  * when blitting into a tiled texture. */
 608                 if (usage & PIPE_TRANSFER_WRITE) {
 609                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 610                 }
 611                 /* Create the temporary texture. */
 612                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 613                 if (trans->staging_texture == NULL) {
 614                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 615                         pipe_resource_reference(&trans->transfer.resource, NULL);
 616                         FREE(trans);
 617                         return NULL;
 618                 }
 619
 620                 trans->transfer.stride =
 621                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 622                 if (usage & PIPE_TRANSFER_READ) {
 623                         r600_copy_to_staging_texture(ctx, trans);
 624                         /* Always referenced in the blit. */
 625                         ctx->flush(ctx, 0, NULL);
 626                 }
 627                 return &trans->transfer;
 628         }
 629         trans->transfer.stride = rtex->pitch_in_bytes[level];
 630         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 631         return &trans->transfer;
 632 }
 633
 634 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 635                                    struct pipe_transfer *transfer)
 636 {
 637         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 638
 639         if (rtransfer->staging_texture) {
 640                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 641                         r600_copy_from_staging_texture(ctx, rtransfer);
 642                 }
 643                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 644         }
 645         pipe_resource_reference(&transfer->resource, NULL);
 646         FREE(transfer);
 647 }
 648
 649 void* r600_texture_transfer_map(struct pipe_context *ctx,
 650                                 struct pipe_transfer* transfer)
 651 {
 652         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 653         struct r600_bo *bo;
 654         enum pipe_format format = transfer->resource->format;
 655         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 656         unsigned offset = 0;
 657         unsigned usage = 0;
 658         char *map;
 659
 660         if (rtransfer->staging_texture) {
 661                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 662         } else {
 663                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 664
 665                 if (rtex->flushed_depth_texture)
 666                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 667                 else
 668                         bo = ((struct r600_resource *)transfer->resource)->bo;
 669
 670                 offset = rtransfer->offset +
 671                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 672                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 673         }
 674
 675         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 676                 usage |= PB_USAGE_CPU_WRITE;
 677
 678                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 679                 }
 680
 681                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 682                 }
 683         }
 684
 685         if (transfer->usage & PIPE_TRANSFER_READ) {
 686                 usage |= PB_USAGE_CPU_READ;
 687         }
 688
 689         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 690                 usage |= PB_USAGE_DONTBLOCK;
 691         }
 692
 693         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 694                 usage |= PB_USAGE_UNSYNCHRONIZED;
 695         }
 696
 697         map = r600_bo_map(radeon, bo, usage, ctx);
 698         if (!map) {
 699                 return NULL;
 700         }
 701
 702         return map + offset;
 703 }
 704
 705 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 706                                  struct pipe_transfer* transfer)
 707 {
 708         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 709         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 710         struct r600_bo *bo;
 711
 712         if (rtransfer->staging_texture) {
 713                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 714         } else {
 715                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 716
 717                 if (rtex->flushed_depth_texture) {
 718                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 719                 } else {
 720                         bo = ((struct r600_resource *)transfer->resource)->bo;
 721                 }
 722         }
 723         r600_bo_unmap(radeon, bo);
 724 }
 725
 726 struct u_resource_vtbl r600_texture_vtbl =
 727 {
 728         r600_texture_get_handle,        /* get_handle */
 729         r600_texture_destroy,           /* resource_destroy */
 730         r600_texture_is_referenced,     /* is_resource_referenced */
 731         r600_texture_get_transfer,      /* get_transfer */
 732         r600_texture_transfer_destroy,  /* transfer_destroy */
 733         r600_texture_transfer_map,      /* transfer_map */
 734         u_default_transfer_flush_region,/* transfer_flush_region */
 735         r600_texture_transfer_unmap,    /* transfer_unmap */
 736         u_default_transfer_inline_write /* transfer_inline_write */
 737 };
 738
 739 void r600_init_surface_functions(struct r600_pipe_context *r600)
 740 {
 741         r600->context.create_surface = r600_create_surface;
 742         r600->context.surface_destroy = r600_surface_destroy;
 743 }
 744
 745 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 746                 const unsigned char *swizzle_view)
 747 {
 748         unsigned i;
 749         unsigned char swizzle[4];
 750         unsigned result = 0;
 751         const uint32_t swizzle_shift[4] = {
 752                 16, 19, 22, 25,
 753         };
 754         const uint32_t swizzle_bit[4] = {
 755                 0, 1, 2, 3,
 756         };
 757
 758         if (swizzle_view) {
 759                 /* Combine two sets of swizzles. */
 760                 for (i = 0; i < 4; i++) {
 761                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 762                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 763                 }
 764         } else {
 765                 memcpy(swizzle, swizzle_format, 4);
 766         }
 767
 768         /* Get swizzle. */
 769         for (i = 0; i < 4; i++) {
 770                 switch (swizzle[i]) {
 771                 case UTIL_FORMAT_SWIZZLE_Y:
 772                         result |= swizzle_bit[1] << swizzle_shift[i];
 773                         break;
 774                 case UTIL_FORMAT_SWIZZLE_Z:
 775                         result |= swizzle_bit[2] << swizzle_shift[i];
 776                         break;
 777                 case UTIL_FORMAT_SWIZZLE_W:
 778                         result |= swizzle_bit[3] << swizzle_shift[i];
 779                         break;
 780                 case UTIL_FORMAT_SWIZZLE_0:
 781                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 782                         break;
 783                 case UTIL_FORMAT_SWIZZLE_1:
 784                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 785                         break;
 786                 default: /* UTIL_FORMAT_SWIZZLE_X */
 787                         result |= swizzle_bit[0] << swizzle_shift[i];
 788                 }
 789         }
 790         return result;
 791 }
 792
 793 /* texture format translate */
 794 uint32_t r600_translate_texformat(enum pipe_format format,
 795                                   const unsigned char *swizzle_view,
 796                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 797 {
 798         uint32_t result = 0, word4 = 0, yuv_format = 0;
 799         const struct util_format_description *desc;
 800         boolean uniform = TRUE;
 801         int i;
 802         const uint32_t sign_bit[4] = {
 803                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 804                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 805                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 806                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 807         };
 808         desc = util_format_description(format);
 809
 810         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 811
 812         /* Colorspace (return non-RGB formats directly). */
 813         switch (desc->colorspace) {
 814                 /* Depth stencil formats */
 815         case UTIL_FORMAT_COLORSPACE_ZS:
 816                 switch (format) {
 817                 case PIPE_FORMAT_Z16_UNORM:
 818                         result = FMT_16;
 819                         goto out_word4;
 820                 case PIPE_FORMAT_X24S8_USCALED:
 821                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 822                 case PIPE_FORMAT_Z24X8_UNORM:
 823                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 824                         result = FMT_8_24;
 825                         goto out_word4;
 826                 case PIPE_FORMAT_S8X24_USCALED:
 827                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 828                 case PIPE_FORMAT_X8Z24_UNORM:
 829                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 830                         result = FMT_24_8;
 831                         goto out_word4;
 832                 case PIPE_FORMAT_S8_USCALED:
 833                         result = FMT_8;
 834                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 835                         goto out_word4;
 836                 default:
 837                         goto out_unknown;
 838                 }
 839
 840         case UTIL_FORMAT_COLORSPACE_YUV:
 841                 yuv_format |= (1 << 30);
 842                 switch (format) {
 843                 case PIPE_FORMAT_UYVY:
 844                 case PIPE_FORMAT_YUYV:
 845                 default:
 846                         break;
 847                 }
 848                 goto out_unknown; /* TODO */
 849
 850         case UTIL_FORMAT_COLORSPACE_SRGB:
 851                 word4 |= S_038010_FORCE_DEGAMMA(1);
 852                 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
 853                         goto out_unknown; /* fails for some reason - TODO */
 854                 break;
 855
 856         default:
 857                 break;
 858         }
 859
 860         /* S3TC formats. TODO */
 861         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 862                 static int r600_enable_s3tc = -1;
 863
 864                 if (r600_enable_s3tc == -1)
 865                         r600_enable_s3tc =
 866                                 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 867
 868                 if (!r600_enable_s3tc)
 869                         goto out_unknown;
 870
 871                 switch (format) {
 872                 case PIPE_FORMAT_DXT1_RGB:
 873                 case PIPE_FORMAT_DXT1_RGBA:
 874                         result = FMT_BC1;
 875                         goto out_word4;
 876                 case PIPE_FORMAT_DXT3_RGBA:
 877                         result = FMT_BC2;
 878                         goto out_word4;
 879                 case PIPE_FORMAT_DXT5_RGBA:
 880                         result = FMT_BC3;
 881                         goto out_word4;
 882                 default:
 883                         goto out_unknown;
 884                 }
 885         }
 886
 887
 888         for (i = 0; i < desc->nr_channels; i++) {
 889                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 890                         word4 |= sign_bit[i];
 891                 }
 892         }
 893
 894         /* R8G8Bx_SNORM - TODO CxV8U8 */
 895
 896         /* RGTC - TODO */
 897
 898         /* See whether the components are of the same size. */
 899         for (i = 1; i < desc->nr_channels; i++) {
 900                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 901         }
 902
 903         /* Non-uniform formats. */
 904         if (!uniform) {
 905                 switch(desc->nr_channels) {
 906                 case 3:
 907                         if (desc->channel[0].size == 5 &&
 908                             desc->channel[1].size == 6 &&
 909                             desc->channel[2].size == 5) {
 910                                 result = FMT_5_6_5;
 911                                 goto out_word4;
 912                         }
 913                         goto out_unknown;
 914                 case 4:
 915                         if (desc->channel[0].size == 5 &&
 916                             desc->channel[1].size == 5 &&
 917                             desc->channel[2].size == 5 &&
 918                             desc->channel[3].size == 1) {
 919                                 result = FMT_1_5_5_5;
 920                                 goto out_word4;
 921                         }
 922                         if (desc->channel[0].size == 10 &&
 923                             desc->channel[1].size == 10 &&
 924                             desc->channel[2].size == 10 &&
 925                             desc->channel[3].size == 2) {
 926                                 result = FMT_10_10_10_2;
 927                                 goto out_word4;
 928                         }
 929                         goto out_unknown;
 930                 }
 931                 goto out_unknown;
 932         }
 933
 934         /* Find the first non-VOID channel. */
 935         for (i = 0; i < 4; i++) {
 936                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 937                         break;
 938                 }
 939         }
 940
 941         if (i == 4)
 942                 goto out_unknown;
 943
 944         /* uniform formats */
 945         switch (desc->channel[i].type) {
 946         case UTIL_FORMAT_TYPE_UNSIGNED:
 947         case UTIL_FORMAT_TYPE_SIGNED:
 948                 if (!desc->channel[i].normalized &&
 949                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 950                         goto out_unknown;
 951                 }
 952
 953                 switch (desc->channel[i].size) {
 954                 case 4:
 955                         switch (desc->nr_channels) {
 956                         case 2:
 957                                 result = FMT_4_4;
 958                                 goto out_word4;
 959                         case 4:
 960                                 result = FMT_4_4_4_4;
 961                                 goto out_word4;
 962                         }
 963                         goto out_unknown;
 964                 case 8:
 965                         switch (desc->nr_channels) {
 966                         case 1:
 967                                 result = FMT_8;
 968                                 goto out_word4;
 969                         case 2:
 970                                 result = FMT_8_8;
 971                                 goto out_word4;
 972                         case 4:
 973                                 result = FMT_8_8_8_8;
 974                                 goto out_word4;
 975                         }
 976                         goto out_unknown;
 977                 case 16:
 978                         switch (desc->nr_channels) {
 979                         case 1:
 980                                 result = FMT_16;
 981                                 goto out_word4;
 982                         case 2:
 983                                 result = FMT_16_16;
 984                                 goto out_word4;
 985                         case 4:
 986                                 result = FMT_16_16_16_16;
 987                                 goto out_word4;
 988                         }
 989                 }
 990                 goto out_unknown;
 991
 992         case UTIL_FORMAT_TYPE_FLOAT:
 993                 switch (desc->channel[i].size) {
 994                 case 16:
 995                         switch (desc->nr_channels) {
 996                         case 1:
 997                                 result = FMT_16_FLOAT;
 998                                 goto out_word4;
 999                         case 2:
1000                                 result = FMT_16_16_FLOAT;
1001                                 goto out_word4;
1002                         case 4:
1003                                 result = FMT_16_16_16_16_FLOAT;
1004                                 goto out_word4;
1005                         }
1006                         goto out_unknown;
1007                 case 32:
1008                         switch (desc->nr_channels) {
1009                         case 1:
1010                                 result = FMT_32_FLOAT;
1011                                 goto out_word4;
1012                         case 2:
1013                                 result = FMT_32_32_FLOAT;
1014                                 goto out_word4;
1015                         case 4:
1016                                 result = FMT_32_32_32_32_FLOAT;
1017                                 goto out_word4;
1018                         }
1019                 }
1020
1021         }
1022 out_word4:
1023         if (word4_p)
1024                 *word4_p = word4;
1025         if (yuv_format_p)
1026                 *yuv_format_p = yuv_format;
1027         return result;
1028 out_unknown:
1029 //      R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1030         return ~0;
1031 }