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r600g,radeonsi: consolidate transfer, cmask, and fmask structures
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "evergreen_compute.h"
29 #include "r600d.h"
30
31 #include <errno.h>
32 #include "util/u_format_s3tc.h"
33 #include "util/u_memory.h"
34
35
36 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
37 static void r600_copy_region_with_blit(struct pipe_context *pipe,
38 struct pipe_resource *dst,
39 unsigned dst_level,
40 unsigned dstx, unsigned dsty, unsigned dstz,
41 struct pipe_resource *src,
42 unsigned src_level,
43 const struct pipe_box *src_box)
44 {
45 struct pipe_blit_info blit;
46
47 memset(&blit, 0, sizeof(blit));
48 blit.src.resource = src;
49 blit.src.format = src->format;
50 blit.src.level = src_level;
51 blit.src.box = *src_box;
52 blit.dst.resource = dst;
53 blit.dst.format = dst->format;
54 blit.dst.level = dst_level;
55 blit.dst.box.x = dstx;
56 blit.dst.box.y = dsty;
57 blit.dst.box.z = dstz;
58 blit.dst.box.width = src_box->width;
59 blit.dst.box.height = src_box->height;
60 blit.dst.box.depth = src_box->depth;
61 blit.mask = util_format_get_mask(src->format) &
62 util_format_get_mask(dst->format);
63 blit.filter = PIPE_TEX_FILTER_NEAREST;
64
65 if (blit.mask) {
66 pipe->blit(pipe, &blit);
67 }
68 }
69
70 /* Copy from a full GPU texture to a transfer's staging one. */
71 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
72 {
73 struct r600_context *rctx = (struct r600_context*)ctx;
74 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
75 struct pipe_resource *dst = &rtransfer->staging->b.b;
76 struct pipe_resource *src = transfer->resource;
77
78 if (src->nr_samples > 1) {
79 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
80 src, transfer->level, &transfer->box);
81 return;
82 }
83
84 if (!rctx->screen->dma_blit(ctx, dst, 0, 0, 0, 0,
85 src, transfer->level,
86 &transfer->box)) {
87 ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
88 src, transfer->level, &transfer->box);
89 }
90 }
91
92 /* Copy from a transfer's staging texture to a full GPU one. */
93 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
94 {
95 struct r600_context *rctx = (struct r600_context*)ctx;
96 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
97 struct pipe_resource *dst = transfer->resource;
98 struct pipe_resource *src = &rtransfer->staging->b.b;
99 struct pipe_box sbox;
100
101 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
102
103 if (dst->nr_samples > 1) {
104 r600_copy_region_with_blit(ctx, dst, transfer->level,
105 transfer->box.x, transfer->box.y, transfer->box.z,
106 src, 0, &sbox);
107 return;
108 }
109
110 if (!rctx->screen->dma_blit(ctx, dst, transfer->level,
111 transfer->box.x, transfer->box.y, transfer->box.z,
112 src, 0, &sbox)) {
113 ctx->resource_copy_region(ctx, dst, transfer->level,
114 transfer->box.x, transfer->box.y, transfer->box.z,
115 src, 0, &sbox);
116 }
117 }
118
119 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
120 const struct pipe_box *box)
121 {
122 enum pipe_format format = rtex->resource.b.b.format;
123
124 return rtex->surface.level[level].offset +
125 box->z * rtex->surface.level[level].slice_size +
126 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
127 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
128 }
129
130 static int r600_init_surface(struct r600_screen *rscreen,
131 struct radeon_surface *surface,
132 const struct pipe_resource *ptex,
133 unsigned array_mode,
134 bool is_flushed_depth)
135 {
136 const struct util_format_description *desc =
137 util_format_description(ptex->format);
138 bool is_depth, is_stencil;
139
140 is_depth = util_format_has_depth(desc);
141 is_stencil = util_format_has_stencil(desc);
142
143 surface->npix_x = ptex->width0;
144 surface->npix_y = ptex->height0;
145 surface->npix_z = ptex->depth0;
146 surface->blk_w = util_format_get_blockwidth(ptex->format);
147 surface->blk_h = util_format_get_blockheight(ptex->format);
148 surface->blk_d = 1;
149 surface->array_size = 1;
150 surface->last_level = ptex->last_level;
151
152 if (rscreen->b.chip_class >= EVERGREEN && !is_flushed_depth &&
153 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
154 surface->bpe = 4; /* stencil is allocated separately on evergreen */
155 } else {
156 surface->bpe = util_format_get_blocksize(ptex->format);
157 /* align byte per element on dword */
158 if (surface->bpe == 3) {
159 surface->bpe = 4;
160 }
161 }
162
163 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
164 surface->flags = 0;
165
166 switch (array_mode) {
167 case V_038000_ARRAY_1D_TILED_THIN1:
168 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
169 break;
170 case V_038000_ARRAY_2D_TILED_THIN1:
171 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
172 break;
173 case V_038000_ARRAY_LINEAR_ALIGNED:
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
175 break;
176 case V_038000_ARRAY_LINEAR_GENERAL:
177 default:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
179 break;
180 }
181 switch (ptex->target) {
182 case PIPE_TEXTURE_1D:
183 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
184 break;
185 case PIPE_TEXTURE_RECT:
186 case PIPE_TEXTURE_2D:
187 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
188 break;
189 case PIPE_TEXTURE_3D:
190 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
191 break;
192 case PIPE_TEXTURE_1D_ARRAY:
193 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
194 surface->array_size = ptex->array_size;
195 break;
196 case PIPE_TEXTURE_2D_ARRAY:
197 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d layout for now */
198 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
199 surface->array_size = ptex->array_size;
200 break;
201 case PIPE_TEXTURE_CUBE:
202 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
203 break;
204 case PIPE_BUFFER:
205 default:
206 return -EINVAL;
207 }
208 if (ptex->bind & PIPE_BIND_SCANOUT) {
209 surface->flags |= RADEON_SURF_SCANOUT;
210 }
211
212 if (!is_flushed_depth && is_depth) {
213 surface->flags |= RADEON_SURF_ZBUFFER;
214
215 if (is_stencil) {
216 surface->flags |= RADEON_SURF_SBUFFER |
217 RADEON_SURF_HAS_SBUFFER_MIPTREE;
218 }
219 }
220 return 0;
221 }
222
223 static int r600_setup_surface(struct pipe_screen *screen,
224 struct r600_texture *rtex,
225 unsigned pitch_in_bytes_override)
226 {
227 struct pipe_resource *ptex = &rtex->resource.b.b;
228 struct r600_screen *rscreen = (struct r600_screen*)screen;
229 unsigned i;
230 int r;
231
232 r = rscreen->b.ws->surface_init(rscreen->b.ws, &rtex->surface);
233 if (r) {
234 return r;
235 }
236 rtex->size = rtex->surface.bo_size;
237 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
238 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
239 * for those
240 */
241 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
242 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
243 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
244 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
245 rtex->surface.stencil_offset =
246 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
247 }
248 }
249 for (i = 0; i <= ptex->last_level; i++) {
250 switch (rtex->surface.level[i].mode) {
251 case RADEON_SURF_MODE_LINEAR_ALIGNED:
252 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
253 break;
254 case RADEON_SURF_MODE_1D:
255 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
256 break;
257 case RADEON_SURF_MODE_2D:
258 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
259 break;
260 default:
261 case RADEON_SURF_MODE_LINEAR:
262 rtex->array_mode[i] = 0;
263 break;
264 }
265 }
266 return 0;
267 }
268
269 static boolean r600_texture_get_handle(struct pipe_screen* screen,
270 struct pipe_resource *ptex,
271 struct winsys_handle *whandle)
272 {
273 struct r600_texture *rtex = (struct r600_texture*)ptex;
274 struct r600_resource *resource = &rtex->resource;
275 struct radeon_surface *surface = &rtex->surface;
276 struct r600_screen *rscreen = (struct r600_screen*)screen;
277
278 rscreen->b.ws->buffer_set_tiling(resource->buf,
279 NULL,
280 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
281 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
282 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
283 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
284 surface->bankw, surface->bankh,
285 surface->tile_split,
286 surface->stencil_tile_split,
287 surface->mtilea,
288 rtex->surface.level[0].pitch_bytes);
289
290 return rscreen->b.ws->buffer_get_handle(resource->buf,
291 rtex->surface.level[0].pitch_bytes, whandle);
292 }
293
294 static void r600_texture_destroy(struct pipe_screen *screen,
295 struct pipe_resource *ptex)
296 {
297 struct r600_texture *rtex = (struct r600_texture*)ptex;
298 struct r600_resource *resource = &rtex->resource;
299
300 if (rtex->flushed_depth_texture)
301 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
302
303 pipe_resource_reference((struct pipe_resource**)&rtex->htile, NULL);
304 if (rtex->cmask_buffer != &rtex->resource) {
305 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
306 }
307 pb_reference(&resource->buf, NULL);
308 FREE(rtex);
309 }
310
311 static const struct u_resource_vtbl r600_texture_vtbl;
312
313 /* The number of samples can be specified independently of the texture. */
314 void r600_texture_get_fmask_info(struct r600_screen *rscreen,
315 struct r600_texture *rtex,
316 unsigned nr_samples,
317 struct r600_fmask_info *out)
318 {
319 /* FMASK is allocated like an ordinary texture. */
320 struct radeon_surface fmask = rtex->surface;
321
322 memset(out, 0, sizeof(*out));
323
324 fmask.bo_alignment = 0;
325 fmask.bo_size = 0;
326 fmask.nsamples = 1;
327 fmask.flags |= RADEON_SURF_FMASK;
328
329 switch (nr_samples) {
330 case 2:
331 case 4:
332 fmask.bpe = 1;
333 fmask.bankh = 4;
334 break;
335 case 8:
336 fmask.bpe = 4;
337 break;
338 default:
339 R600_ERR("Invalid sample count for FMASK allocation.\n");
340 return;
341 }
342
343 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
344 * This can be fixed by writing a separate FMASK allocator specifically
345 * for R600-R700 asics. */
346 if (rscreen->b.chip_class <= R700) {
347 fmask.bpe *= 2;
348 }
349
350 if (rscreen->b.ws->surface_init(rscreen->b.ws, &fmask)) {
351 R600_ERR("Got error in surface_init while allocating FMASK.\n");
352 return;
353 }
354
355 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
356
357 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
358 if (out->slice_tile_max)
359 out->slice_tile_max -= 1;
360
361 out->bank_height = fmask.bankh;
362 out->alignment = MAX2(256, fmask.bo_alignment);
363 out->size = fmask.bo_size;
364 }
365
366 static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
367 struct r600_texture *rtex)
368 {
369 struct r600_fmask_info fmask;
370
371 r600_texture_get_fmask_info(rscreen, rtex,
372 rtex->resource.b.b.nr_samples, &fmask);
373
374 rtex->fmask.bank_height = fmask.bank_height;
375 rtex->fmask.slice_tile_max = fmask.slice_tile_max;
376 rtex->fmask.offset = align(rtex->size, fmask.alignment);
377 rtex->fmask.size = fmask.size;
378 rtex->size = rtex->fmask.offset + rtex->fmask.size;
379 #if 0
380 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
381 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
382 #endif
383 }
384
385 void r600_texture_get_cmask_info(struct r600_screen *rscreen,
386 struct r600_texture *rtex,
387 struct r600_cmask_info *out)
388 {
389 unsigned cmask_tile_width = 8;
390 unsigned cmask_tile_height = 8;
391 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
392 unsigned element_bits = 4;
393 unsigned cmask_cache_bits = 1024;
394 unsigned num_pipes = rscreen->tiling_info.num_channels;
395 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
396
397 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
398 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
399 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
400 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
401 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
402
403 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
404 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
405
406 unsigned base_align = num_pipes * pipe_interleave_bytes;
407 unsigned slice_bytes =
408 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
409
410 assert(macro_tile_width % 128 == 0);
411 assert(macro_tile_height % 128 == 0);
412
413 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
414 out->alignment = MAX2(256, base_align);
415 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
416 }
417
418 static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
419 struct r600_texture *rtex)
420 {
421 struct r600_cmask_info cmask;
422
423 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
424
425 rtex->cmask.slice_tile_max = cmask.slice_tile_max;
426 rtex->cmask.offset = align(rtex->size, cmask.alignment);
427 rtex->cmask.size = cmask.size;
428 rtex->size = rtex->cmask.offset + rtex->cmask.size;
429 #if 0
430 printf("CMASK: macro tile width = %u, macro tile height = %u, "
431 "pitch elements = %u, height = %u, slice tile max = %u\n",
432 macro_tile_width, macro_tile_height, pitch_elements, height,
433 rtex->cmask_slice_tile_max);
434 #endif
435 }
436
437 void r600_texture_init_cmask(struct r600_screen *rscreen,
438 struct r600_texture *rtex) {
439 struct r600_cmask_info cmask;
440
441 assert(rtex->cmask.size == 0);
442
443 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
444 rtex->cmask.slice_tile_max = cmask.slice_tile_max;
445 rtex->cmask.offset = 0;
446 rtex->cmask.size = cmask.size;
447 rtex->cmask_buffer = (struct r600_resource *)pipe_buffer_create(&rscreen->b.b,
448 PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, rtex->cmask.size);
449
450 if (rtex->cmask_buffer == NULL) {
451 rtex->cmask.size = 0;
452 }
453 }
454
455 static struct r600_texture *
456 r600_texture_create_object(struct pipe_screen *screen,
457 const struct pipe_resource *base,
458 unsigned pitch_in_bytes_override,
459 struct pb_buffer *buf,
460 struct radeon_surface *surface)
461 {
462 struct r600_texture *rtex;
463 struct r600_resource *resource;
464 struct r600_screen *rscreen = (struct r600_screen*)screen;
465 int r;
466
467 rtex = CALLOC_STRUCT(r600_texture);
468 if (rtex == NULL)
469 return NULL;
470
471 resource = &rtex->resource;
472 resource->b.b = *base;
473 resource->b.vtbl = &r600_texture_vtbl;
474 pipe_reference_init(&resource->b.b.reference, 1);
475 resource->b.b.screen = screen;
476 rtex->pitch_override = pitch_in_bytes_override;
477
478 /* don't include stencil-only formats which we don't support for rendering */
479 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
480
481 rtex->surface = *surface;
482 r = r600_setup_surface(screen, rtex, pitch_in_bytes_override);
483 if (r) {
484 FREE(rtex);
485 return NULL;
486 }
487
488 rtex->cmask_buffer = NULL;
489 if (base->nr_samples > 1 && !rtex->is_depth && !buf) {
490 r600_texture_allocate_fmask(rscreen, rtex);
491 r600_texture_allocate_cmask(rscreen, rtex);
492 rtex->cmask_buffer = &rtex->resource;
493 }
494
495 if (!rtex->is_depth && base->nr_samples > 1 &&
496 (!rtex->fmask.size || !rtex->cmask.size)) {
497 FREE(rtex);
498 return NULL;
499 }
500
501 /* Tiled depth textures utilize the non-displayable tile order. */
502 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
503
504 /* only enable hyperz for PIPE_TEXTURE_2D not for PIPE_TEXTURE_2D_ARRAY
505 * Thought it might still be interessting to use hyperz for texture
506 * array without using fast clear features
507 */
508 rtex->htile = NULL;
509 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER | R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
510 util_format_is_depth_or_stencil(base->format) &&
511 rscreen->b.info.drm_minor >= 26 &&
512 !(rscreen->debug_flags & DBG_NO_HYPERZ) &&
513 base->target == PIPE_TEXTURE_2D &&
514 rtex->surface.level[0].nblk_x >= 32 &&
515 rtex->surface.level[0].nblk_y >= 32) {
516 unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
517 unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
518 unsigned htile_size;
519 unsigned npipes = rscreen->b.info.r600_num_tile_pipes;
520
521 /* this alignment and htile size only apply to linear htile buffer */
522 sw = align(sw, 16 << 3);
523 sh = align(sh, npipes << 3);
524 htile_size = (sw >> 3) * (sh >> 3) * 4;
525 /* must be aligned with 2K * npipes */
526 htile_size = align(htile_size, (2 << 10) * npipes);
527
528 rtex->htile = (struct r600_resource*)pipe_buffer_create(&rscreen->b.b, PIPE_BIND_CUSTOM,
529 PIPE_USAGE_STATIC, htile_size);
530 if (rtex->htile == NULL) {
531 /* this is not a fatal error as we can still keep rendering
532 * without htile buffer
533 */
534 R600_ERR("r600: failed to create bo for htile buffers\n");
535 } else {
536 r600_screen_clear_buffer(rscreen, &rtex->htile->b.b, 0, htile_size, 0);
537 }
538 }
539
540 /* Now create the backing buffer. */
541 if (!buf) {
542 unsigned base_align = rtex->surface.bo_alignment;
543 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
544
545 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
546 FREE(rtex);
547 return NULL;
548 }
549 } else {
550 /* This is usually the window framebuffer. We want it in VRAM, always. */
551 resource->buf = buf;
552 resource->cs_buf = rscreen->b.ws->buffer_get_cs_handle(buf);
553 resource->domains = RADEON_DOMAIN_VRAM;
554 }
555
556 if (rtex->cmask.size) {
557 /* Initialize the cmask to 0xCC (= compressed state). */
558 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
559 rtex->cmask.offset, rtex->cmask.size, 0xCC);
560 }
561
562 if (rscreen->debug_flags & DBG_VM) {
563 fprintf(stderr, "VM start=0x%llX end=0x%llX | Texture %ix%ix%i, %i levels, %i samples, %s\n",
564 r600_resource_va(screen, &rtex->resource.b.b),
565 r600_resource_va(screen, &rtex->resource.b.b) + rtex->resource.buf->size,
566 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
567 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
568 }
569
570 if (rscreen->debug_flags & DBG_TEX_DEPTH && rtex->is_depth && rtex->non_disp_tiling) {
571 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
572 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
573 "bpe=%u, nsamples=%u, flags=%u\n",
574 rtex->surface.npix_x, rtex->surface.npix_y,
575 rtex->surface.npix_z, rtex->surface.blk_w,
576 rtex->surface.blk_h, rtex->surface.blk_d,
577 rtex->surface.array_size, rtex->surface.last_level,
578 rtex->surface.bpe, rtex->surface.nsamples,
579 rtex->surface.flags);
580 if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
581 for (int i = 0; i <= rtex->surface.last_level; i++) {
582 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
583 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
584 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
585 i, (unsigned long long)rtex->surface.level[i].offset,
586 (unsigned long long)rtex->surface.level[i].slice_size,
587 u_minify(rtex->resource.b.b.width0, i),
588 u_minify(rtex->resource.b.b.height0, i),
589 u_minify(rtex->resource.b.b.depth0, i),
590 rtex->surface.level[i].nblk_x,
591 rtex->surface.level[i].nblk_y,
592 rtex->surface.level[i].nblk_z,
593 rtex->surface.level[i].pitch_bytes,
594 rtex->surface.level[i].mode);
595 }
596 }
597 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
598 for (int i = 0; i <= rtex->surface.last_level; i++) {
599 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
600 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
601 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
602 i, (unsigned long long)rtex->surface.stencil_level[i].offset,
603 (unsigned long long)rtex->surface.stencil_level[i].slice_size,
604 u_minify(rtex->resource.b.b.width0, i),
605 u_minify(rtex->resource.b.b.height0, i),
606 u_minify(rtex->resource.b.b.depth0, i),
607 rtex->surface.stencil_level[i].nblk_x,
608 rtex->surface.stencil_level[i].nblk_y,
609 rtex->surface.stencil_level[i].nblk_z,
610 rtex->surface.stencil_level[i].pitch_bytes,
611 rtex->surface.stencil_level[i].mode);
612 }
613 }
614 }
615 return rtex;
616 }
617
618 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
619 const struct pipe_resource *templ)
620 {
621 struct r600_screen *rscreen = (struct r600_screen*)screen;
622 struct radeon_surface surface;
623 const struct util_format_description *desc = util_format_description(templ->format);
624 unsigned array_mode;
625 int r;
626
627 /* Default tiling mode for staging textures. */
628 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
629
630 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
631 * because 422 formats are used for videos, which prefer linear buffers
632 * for fast uploads anyway. */
633 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
634 (desc->layout != UTIL_FORMAT_LAYOUT_SUBSAMPLED) &&
635 !(templ->bind & PIPE_BIND_LINEAR)) {
636 if (templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) {
637 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
638 } else if (!(templ->bind & PIPE_BIND_SCANOUT) &&
639 templ->usage != PIPE_USAGE_STAGING &&
640 templ->usage != PIPE_USAGE_STREAM &&
641 templ->target != PIPE_TEXTURE_1D &&
642 templ->target != PIPE_TEXTURE_1D_ARRAY &&
643 templ->height0 > 3) {
644 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
645 } else if (util_format_is_compressed(templ->format)) {
646 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
647 }
648 }
649
650 r = r600_init_surface(rscreen, &surface, templ, array_mode,
651 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
652 if (r) {
653 return NULL;
654 }
655 r = rscreen->b.ws->surface_best(rscreen->b.ws, &surface);
656 if (r) {
657 return NULL;
658 }
659 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
660 0, NULL, &surface);
661 }
662
663 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
664 struct pipe_resource *texture,
665 const struct pipe_surface *templ,
666 unsigned width, unsigned height)
667 {
668 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
669
670 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
671 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
672 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
673 if (surface == NULL)
674 return NULL;
675 pipe_reference_init(&surface->base.reference, 1);
676 pipe_resource_reference(&surface->base.texture, texture);
677 surface->base.context = pipe;
678 surface->base.format = templ->format;
679 surface->base.width = width;
680 surface->base.height = height;
681 surface->base.u = templ->u;
682 return &surface->base;
683 }
684
685 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
686 struct pipe_resource *tex,
687 const struct pipe_surface *templ)
688 {
689 unsigned level = templ->u.tex.level;
690
691 return r600_create_surface_custom(pipe, tex, templ,
692 u_minify(tex->width0, level),
693 u_minify(tex->height0, level));
694 }
695
696 static void r600_surface_destroy(struct pipe_context *pipe,
697 struct pipe_surface *surface)
698 {
699 struct r600_surface *surf = (struct r600_surface*)surface;
700 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
701 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
702 pipe_resource_reference(&surface->texture, NULL);
703 FREE(surface);
704 }
705
706 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
707 const struct pipe_resource *templ,
708 struct winsys_handle *whandle)
709 {
710 struct r600_screen *rscreen = (struct r600_screen*)screen;
711 struct pb_buffer *buf = NULL;
712 unsigned stride = 0;
713 unsigned array_mode = 0;
714 enum radeon_bo_layout micro, macro;
715 struct radeon_surface surface;
716 int r;
717
718 /* Support only 2D textures without mipmaps */
719 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
720 templ->depth0 != 1 || templ->last_level != 0)
721 return NULL;
722
723 buf = rscreen->b.ws->buffer_from_handle(rscreen->b.ws, whandle, &stride);
724 if (!buf)
725 return NULL;
726
727 rscreen->b.ws->buffer_get_tiling(buf, &micro, &macro,
728 &surface.bankw, &surface.bankh,
729 &surface.tile_split,
730 &surface.stencil_tile_split,
731 &surface.mtilea);
732
733 if (macro == RADEON_LAYOUT_TILED)
734 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
735 else if (micro == RADEON_LAYOUT_TILED)
736 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
737 else
738 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
739
740 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
741 if (r) {
742 return NULL;
743 }
744 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
745 stride, buf, &surface);
746 }
747
748 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
749 struct pipe_resource *texture,
750 struct r600_texture **staging)
751 {
752 struct r600_texture *rtex = (struct r600_texture*)texture;
753 struct pipe_resource resource;
754 struct r600_texture **flushed_depth_texture = staging ?
755 staging : &rtex->flushed_depth_texture;
756
757 if (!staging && rtex->flushed_depth_texture)
758 return true; /* it's ready */
759
760 resource.target = texture->target;
761 resource.format = texture->format;
762 resource.width0 = texture->width0;
763 resource.height0 = texture->height0;
764 resource.depth0 = texture->depth0;
765 resource.array_size = texture->array_size;
766 resource.last_level = texture->last_level;
767 resource.nr_samples = texture->nr_samples;
768 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
769 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
770 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
771
772 if (staging)
773 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
774
775 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
776 if (*flushed_depth_texture == NULL) {
777 R600_ERR("failed to create temporary texture to hold flushed depth\n");
778 return false;
779 }
780
781 (*flushed_depth_texture)->is_flushing_texture = TRUE;
782 (*flushed_depth_texture)->non_disp_tiling = false;
783 return true;
784 }
785
786 /**
787 * Initialize the pipe_resource descriptor to be of the same size as the box,
788 * which is supposed to hold a subregion of the texture "orig" at the given
789 * mipmap level.
790 */
791 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
792 struct pipe_resource *orig,
793 const struct pipe_box *box,
794 unsigned level, unsigned flags)
795 {
796 memset(res, 0, sizeof(*res));
797 res->format = orig->format;
798 res->width0 = box->width;
799 res->height0 = box->height;
800 res->depth0 = 1;
801 res->array_size = 1;
802 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
803 res->flags = flags;
804
805 /* We must set the correct texture target and dimensions for a 3D box. */
806 if (box->depth > 1 && util_max_layer(orig, level) > 0)
807 res->target = orig->target;
808 else
809 res->target = PIPE_TEXTURE_2D;
810
811 switch (res->target) {
812 case PIPE_TEXTURE_1D_ARRAY:
813 case PIPE_TEXTURE_2D_ARRAY:
814 case PIPE_TEXTURE_CUBE_ARRAY:
815 res->array_size = box->depth;
816 break;
817 case PIPE_TEXTURE_3D:
818 res->depth0 = box->depth;
819 break;
820 default:;
821 }
822 }
823
824 static void *r600_texture_transfer_map(struct pipe_context *ctx,
825 struct pipe_resource *texture,
826 unsigned level,
827 unsigned usage,
828 const struct pipe_box *box,
829 struct pipe_transfer **ptransfer)
830 {
831 struct r600_context *rctx = (struct r600_context*)ctx;
832 struct r600_texture *rtex = (struct r600_texture*)texture;
833 struct r600_transfer *trans;
834 boolean use_staging_texture = FALSE;
835 struct r600_resource *buf;
836 unsigned offset = 0;
837 char *map;
838
839 if ((texture->bind & PIPE_BIND_GLOBAL) && texture->target == PIPE_BUFFER) {
840 return r600_compute_global_transfer_map(ctx, texture, level, usage, box, ptransfer);
841 }
842
843 /* We cannot map a tiled texture directly because the data is
844 * in a different order, therefore we do detiling using a blit.
845 *
846 * Also, use a temporary in GTT memory for read transfers, as
847 * the CPU is much happier reading out of cached system memory
848 * than uncached VRAM.
849 */
850 if (R600_TEX_IS_TILED(rtex, level)) {
851 use_staging_texture = TRUE;
852 }
853
854 /* Use a staging texture for uploads if the underlying BO is busy. */
855 if (!(usage & PIPE_TRANSFER_READ) &&
856 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
857 rctx->b.ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
858 use_staging_texture = TRUE;
859 }
860
861 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
862 use_staging_texture = FALSE;
863 }
864
865 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
866 return NULL;
867 }
868
869 trans = CALLOC_STRUCT(r600_transfer);
870 if (trans == NULL)
871 return NULL;
872 trans->transfer.resource = texture;
873 trans->transfer.level = level;
874 trans->transfer.usage = usage;
875 trans->transfer.box = *box;
876
877 if (rtex->is_depth) {
878 struct r600_texture *staging_depth;
879
880 if (rtex->resource.b.b.nr_samples > 1) {
881 /* MSAA depth buffers need to be converted to single sample buffers.
882 *
883 * Mapping MSAA depth buffers can occur if ReadPixels is called
884 * with a multisample GLX visual.
885 *
886 * First downsample the depth buffer to a temporary texture,
887 * then decompress the temporary one to staging.
888 *
889 * Only the region being mapped is transfered.
890 */
891 struct pipe_resource resource;
892
893 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
894
895 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
896 R600_ERR("failed to create temporary texture to hold untiled copy\n");
897 FREE(trans);
898 return NULL;
899 }
900
901 if (usage & PIPE_TRANSFER_READ) {
902 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
903
904 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
905 r600_blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
906 0, 0, 0, box->depth, 0, 0);
907 pipe_resource_reference((struct pipe_resource**)&temp, NULL);
908 }
909 }
910 else {
911 /* XXX: only readback the rectangle which is being mapped? */
912 /* XXX: when discard is true, no need to read back from depth texture */
913 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
914 R600_ERR("failed to create temporary texture to hold untiled copy\n");
915 FREE(trans);
916 return NULL;
917 }
918
919 r600_blit_decompress_depth(ctx, rtex, staging_depth,
920 level, level,
921 box->z, box->z + box->depth - 1,
922 0, 0);
923
924 offset = r600_texture_get_offset(staging_depth, level, box);
925 }
926
927 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
928 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
929 trans->staging = (struct r600_resource*)staging_depth;
930 } else if (use_staging_texture) {
931 struct pipe_resource resource;
932 struct r600_texture *staging;
933
934 r600_init_temp_resource_from_box(&resource, texture, box, level,
935 R600_RESOURCE_FLAG_TRANSFER);
936
937 /* Create the temporary texture. */
938 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
939 if (staging == NULL) {
940 R600_ERR("failed to create temporary texture to hold untiled copy\n");
941 FREE(trans);
942 return NULL;
943 }
944 trans->staging = &staging->resource;
945 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
946 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
947 if (usage & PIPE_TRANSFER_READ) {
948 r600_copy_to_staging_texture(ctx, trans);
949 }
950 } else {
951 /* the resource is mapped directly */
952 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
953 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
954 offset = r600_texture_get_offset(rtex, level, box);
955 }
956
957 if (trans->staging) {
958 buf = trans->staging;
959 } else {
960 buf = &rtex->resource;
961 }
962
963 if (!(map = r600_buffer_mmap_sync_with_rings(rctx, buf, usage))) {
964 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
965 FREE(trans);
966 return NULL;
967 }
968
969 *ptransfer = &trans->transfer;
970 return map + offset;
971 }
972
973 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
974 struct pipe_transfer* transfer)
975 {
976 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
977 struct r600_context *rctx = (struct r600_context*)ctx;
978 struct radeon_winsys_cs_handle *buf;
979 struct pipe_resource *texture = transfer->resource;
980 struct r600_texture *rtex = (struct r600_texture*)texture;
981
982 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
983 return r600_compute_global_transfer_unmap(ctx, transfer);
984 }
985
986 if (rtransfer->staging) {
987 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
988 } else {
989 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
990 }
991 rctx->b.ws->buffer_unmap(buf);
992
993 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
994 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
995 ctx->resource_copy_region(ctx, texture, transfer->level,
996 transfer->box.x, transfer->box.y, transfer->box.z,
997 &rtransfer->staging->b.b, transfer->level,
998 &transfer->box);
999 } else {
1000 r600_copy_from_staging_texture(ctx, rtransfer);
1001 }
1002 }
1003
1004 if (rtransfer->staging)
1005 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1006
1007 FREE(transfer);
1008 }
1009
1010 void r600_init_surface_functions(struct r600_context *r600)
1011 {
1012 r600->b.b.create_surface = r600_create_surface;
1013 r600->b.b.surface_destroy = r600_surface_destroy;
1014 }
1015
1016 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
1017 const unsigned char *swizzle_view,
1018 boolean vtx)
1019 {
1020 unsigned i;
1021 unsigned char swizzle[4];
1022 unsigned result = 0;
1023 const uint32_t tex_swizzle_shift[4] = {
1024 16, 19, 22, 25,
1025 };
1026 const uint32_t vtx_swizzle_shift[4] = {
1027 3, 6, 9, 12,
1028 };
1029 const uint32_t swizzle_bit[4] = {
1030 0, 1, 2, 3,
1031 };
1032 const uint32_t *swizzle_shift = tex_swizzle_shift;
1033
1034 if (vtx)
1035 swizzle_shift = vtx_swizzle_shift;
1036
1037 if (swizzle_view) {
1038 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1039 } else {
1040 memcpy(swizzle, swizzle_format, 4);
1041 }
1042
1043 /* Get swizzle. */
1044 for (i = 0; i < 4; i++) {
1045 switch (swizzle[i]) {
1046 case UTIL_FORMAT_SWIZZLE_Y:
1047 result |= swizzle_bit[1] << swizzle_shift[i];
1048 break;
1049 case UTIL_FORMAT_SWIZZLE_Z:
1050 result |= swizzle_bit[2] << swizzle_shift[i];
1051 break;
1052 case UTIL_FORMAT_SWIZZLE_W:
1053 result |= swizzle_bit[3] << swizzle_shift[i];
1054 break;
1055 case UTIL_FORMAT_SWIZZLE_0:
1056 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1057 break;
1058 case UTIL_FORMAT_SWIZZLE_1:
1059 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1060 break;
1061 default: /* UTIL_FORMAT_SWIZZLE_X */
1062 result |= swizzle_bit[0] << swizzle_shift[i];
1063 }
1064 }
1065 return result;
1066 }
1067
1068 /* texture format translate */
1069 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1070 enum pipe_format format,
1071 const unsigned char *swizzle_view,
1072 uint32_t *word4_p, uint32_t *yuv_format_p)
1073 {
1074 struct r600_screen *rscreen = (struct r600_screen *)screen;
1075 uint32_t result = 0, word4 = 0, yuv_format = 0;
1076 const struct util_format_description *desc;
1077 boolean uniform = TRUE;
1078 bool enable_s3tc = rscreen->b.info.drm_minor >= 9;
1079 bool is_srgb_valid = FALSE;
1080 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
1081 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
1082
1083 int i;
1084 const uint32_t sign_bit[4] = {
1085 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1086 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1087 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1088 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1089 };
1090 desc = util_format_description(format);
1091
1092 /* Depth and stencil swizzling is handled separately. */
1093 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
1094 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1095 }
1096
1097 /* Colorspace (return non-RGB formats directly). */
1098 switch (desc->colorspace) {
1099 /* Depth stencil formats */
1100 case UTIL_FORMAT_COLORSPACE_ZS:
1101 switch (format) {
1102 /* Depth sampler formats. */
1103 case PIPE_FORMAT_Z16_UNORM:
1104 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1105 result = FMT_16;
1106 goto out_word4;
1107 case PIPE_FORMAT_Z24X8_UNORM:
1108 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1109 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1110 result = FMT_8_24;
1111 goto out_word4;
1112 case PIPE_FORMAT_X8Z24_UNORM:
1113 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1114 if (rscreen->b.chip_class < EVERGREEN)
1115 goto out_unknown;
1116 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1117 result = FMT_24_8;
1118 goto out_word4;
1119 case PIPE_FORMAT_Z32_FLOAT:
1120 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1121 result = FMT_32_FLOAT;
1122 goto out_word4;
1123 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1124 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1125 result = FMT_X24_8_32_FLOAT;
1126 goto out_word4;
1127 /* Stencil sampler formats. */
1128 case PIPE_FORMAT_S8_UINT:
1129 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1130 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1131 result = FMT_8;
1132 goto out_word4;
1133 case PIPE_FORMAT_X24S8_UINT:
1134 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1135 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1136 result = FMT_8_24;
1137 goto out_word4;
1138 case PIPE_FORMAT_S8X24_UINT:
1139 if (rscreen->b.chip_class < EVERGREEN)
1140 goto out_unknown;
1141 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1142 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1143 result = FMT_24_8;
1144 goto out_word4;
1145 case PIPE_FORMAT_X32_S8X24_UINT:
1146 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1147 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1148 result = FMT_X24_8_32_FLOAT;
1149 goto out_word4;
1150 default:
1151 goto out_unknown;
1152 }
1153
1154 case UTIL_FORMAT_COLORSPACE_YUV:
1155 yuv_format |= (1 << 30);
1156 switch (format) {
1157 case PIPE_FORMAT_UYVY:
1158 case PIPE_FORMAT_YUYV:
1159 default:
1160 break;
1161 }
1162 goto out_unknown; /* XXX */
1163
1164 case UTIL_FORMAT_COLORSPACE_SRGB:
1165 word4 |= S_038010_FORCE_DEGAMMA(1);
1166 break;
1167
1168 default:
1169 break;
1170 }
1171
1172 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1173 if (!enable_s3tc)
1174 goto out_unknown;
1175
1176 switch (format) {
1177 case PIPE_FORMAT_RGTC1_SNORM:
1178 case PIPE_FORMAT_LATC1_SNORM:
1179 word4 |= sign_bit[0];
1180 case PIPE_FORMAT_RGTC1_UNORM:
1181 case PIPE_FORMAT_LATC1_UNORM:
1182 result = FMT_BC4;
1183 goto out_word4;
1184 case PIPE_FORMAT_RGTC2_SNORM:
1185 case PIPE_FORMAT_LATC2_SNORM:
1186 word4 |= sign_bit[0] | sign_bit[1];
1187 case PIPE_FORMAT_RGTC2_UNORM:
1188 case PIPE_FORMAT_LATC2_UNORM:
1189 result = FMT_BC5;
1190 goto out_word4;
1191 default:
1192 goto out_unknown;
1193 }
1194 }
1195
1196 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1197
1198 if (!enable_s3tc)
1199 goto out_unknown;
1200
1201 if (!util_format_s3tc_enabled) {
1202 goto out_unknown;
1203 }
1204
1205 switch (format) {
1206 case PIPE_FORMAT_DXT1_RGB:
1207 case PIPE_FORMAT_DXT1_RGBA:
1208 case PIPE_FORMAT_DXT1_SRGB:
1209 case PIPE_FORMAT_DXT1_SRGBA:
1210 result = FMT_BC1;
1211 is_srgb_valid = TRUE;
1212 goto out_word4;
1213 case PIPE_FORMAT_DXT3_RGBA:
1214 case PIPE_FORMAT_DXT3_SRGBA:
1215 result = FMT_BC2;
1216 is_srgb_valid = TRUE;
1217 goto out_word4;
1218 case PIPE_FORMAT_DXT5_RGBA:
1219 case PIPE_FORMAT_DXT5_SRGBA:
1220 result = FMT_BC3;
1221 is_srgb_valid = TRUE;
1222 goto out_word4;
1223 default:
1224 goto out_unknown;
1225 }
1226 }
1227
1228 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1229 switch (format) {
1230 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1231 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1232 result = FMT_GB_GR;
1233 goto out_word4;
1234 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1235 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1236 result = FMT_BG_RG;
1237 goto out_word4;
1238 default:
1239 goto out_unknown;
1240 }
1241 }
1242
1243 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1244 result = FMT_5_9_9_9_SHAREDEXP;
1245 goto out_word4;
1246 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1247 result = FMT_10_11_11_FLOAT;
1248 goto out_word4;
1249 }
1250
1251
1252 for (i = 0; i < desc->nr_channels; i++) {
1253 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1254 word4 |= sign_bit[i];
1255 }
1256 }
1257
1258 /* R8G8Bx_SNORM - XXX CxV8U8 */
1259
1260 /* See whether the components are of the same size. */
1261 for (i = 1; i < desc->nr_channels; i++) {
1262 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1263 }
1264
1265 /* Non-uniform formats. */
1266 if (!uniform) {
1267 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1268 desc->channel[0].pure_integer)
1269 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1270 switch(desc->nr_channels) {
1271 case 3:
1272 if (desc->channel[0].size == 5 &&
1273 desc->channel[1].size == 6 &&
1274 desc->channel[2].size == 5) {
1275 result = FMT_5_6_5;
1276 goto out_word4;
1277 }
1278 goto out_unknown;
1279 case 4:
1280 if (desc->channel[0].size == 5 &&
1281 desc->channel[1].size == 5 &&
1282 desc->channel[2].size == 5 &&
1283 desc->channel[3].size == 1) {
1284 result = FMT_1_5_5_5;
1285 goto out_word4;
1286 }
1287 if (desc->channel[0].size == 10 &&
1288 desc->channel[1].size == 10 &&
1289 desc->channel[2].size == 10 &&
1290 desc->channel[3].size == 2) {
1291 result = FMT_2_10_10_10;
1292 goto out_word4;
1293 }
1294 goto out_unknown;
1295 }
1296 goto out_unknown;
1297 }
1298
1299 /* Find the first non-VOID channel. */
1300 for (i = 0; i < 4; i++) {
1301 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1302 break;
1303 }
1304 }
1305
1306 if (i == 4)
1307 goto out_unknown;
1308
1309 /* uniform formats */
1310 switch (desc->channel[i].type) {
1311 case UTIL_FORMAT_TYPE_UNSIGNED:
1312 case UTIL_FORMAT_TYPE_SIGNED:
1313 #if 0
1314 if (!desc->channel[i].normalized &&
1315 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1316 goto out_unknown;
1317 }
1318 #endif
1319 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1320 desc->channel[i].pure_integer)
1321 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1322
1323 switch (desc->channel[i].size) {
1324 case 4:
1325 switch (desc->nr_channels) {
1326 case 2:
1327 result = FMT_4_4;
1328 goto out_word4;
1329 case 4:
1330 result = FMT_4_4_4_4;
1331 goto out_word4;
1332 }
1333 goto out_unknown;
1334 case 8:
1335 switch (desc->nr_channels) {
1336 case 1:
1337 result = FMT_8;
1338 goto out_word4;
1339 case 2:
1340 result = FMT_8_8;
1341 goto out_word4;
1342 case 4:
1343 result = FMT_8_8_8_8;
1344 is_srgb_valid = TRUE;
1345 goto out_word4;
1346 }
1347 goto out_unknown;
1348 case 16:
1349 switch (desc->nr_channels) {
1350 case 1:
1351 result = FMT_16;
1352 goto out_word4;
1353 case 2:
1354 result = FMT_16_16;
1355 goto out_word4;
1356 case 4:
1357 result = FMT_16_16_16_16;
1358 goto out_word4;
1359 }
1360 goto out_unknown;
1361 case 32:
1362 switch (desc->nr_channels) {
1363 case 1:
1364 result = FMT_32;
1365 goto out_word4;
1366 case 2:
1367 result = FMT_32_32;
1368 goto out_word4;
1369 case 4:
1370 result = FMT_32_32_32_32;
1371 goto out_word4;
1372 }
1373 }
1374 goto out_unknown;
1375
1376 case UTIL_FORMAT_TYPE_FLOAT:
1377 switch (desc->channel[i].size) {
1378 case 16:
1379 switch (desc->nr_channels) {
1380 case 1:
1381 result = FMT_16_FLOAT;
1382 goto out_word4;
1383 case 2:
1384 result = FMT_16_16_FLOAT;
1385 goto out_word4;
1386 case 4:
1387 result = FMT_16_16_16_16_FLOAT;
1388 goto out_word4;
1389 }
1390 goto out_unknown;
1391 case 32:
1392 switch (desc->nr_channels) {
1393 case 1:
1394 result = FMT_32_FLOAT;
1395 goto out_word4;
1396 case 2:
1397 result = FMT_32_32_FLOAT;
1398 goto out_word4;
1399 case 4:
1400 result = FMT_32_32_32_32_FLOAT;
1401 goto out_word4;
1402 }
1403 }
1404 goto out_unknown;
1405 }
1406
1407 out_word4:
1408
1409 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1410 return ~0;
1411 if (word4_p)
1412 *word4_p = word4;
1413 if (yuv_format_p)
1414 *yuv_format_p = yuv_format;
1415 return result;
1416 out_unknown:
1417 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1418 return ~0;
1419 }
1420
1421 static const struct u_resource_vtbl r600_texture_vtbl =
1422 {
1423 r600_texture_get_handle, /* get_handle */
1424 r600_texture_destroy, /* resource_destroy */
1425 r600_texture_transfer_map, /* transfer_map */
1426 NULL, /* transfer_flush_region */
1427 r600_texture_transfer_unmap, /* transfer_unmap */
1428 NULL /* transfer_inline_write */
1429 };