2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_math.h>
31 #include <util/u_inlines.h>
32 #include <util/u_memory.h>
33 #include "state_tracker/drm_driver.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
39 #include "r600_formats.h"
41 extern struct u_resource_vtbl r600_texture_vtbl
;
43 /* Copy from a full GPU texture to a transfer's staging one. */
44 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
46 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
47 struct pipe_resource
*texture
= transfer
->resource
;
49 ctx
->resource_copy_region(ctx
, rtransfer
->staging_texture
,
50 0, 0, 0, 0, texture
, transfer
->level
,
55 /* Copy from a transfer's staging texture to a full GPU one. */
56 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
58 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
59 struct pipe_resource
*texture
= transfer
->resource
;
62 sbox
.x
= sbox
.y
= sbox
.z
= 0;
63 sbox
.width
= transfer
->box
.width
;
64 sbox
.height
= transfer
->box
.height
;
65 /* XXX that might be wrong */
67 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
68 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
69 rtransfer
->staging_texture
,
72 ctx
->flush(ctx
, 0, NULL
);
75 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
76 unsigned level
, unsigned layer
)
78 unsigned offset
= rtex
->offset
[level
];
80 switch (rtex
->resource
.base
.b
.target
) {
82 case PIPE_TEXTURE_CUBE
:
83 return offset
+ layer
* rtex
->layer_size
[level
];
90 static unsigned r600_get_pixel_alignment(struct pipe_screen
*screen
,
91 enum pipe_format format
,
94 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
95 unsigned pixsize
= util_format_get_blocksize(format
);
99 case V_038000_ARRAY_1D_TILED_THIN1
:
101 ((rscreen
->tiling_info
->group_bytes
/ 8 / pixsize
)));
103 case V_038000_ARRAY_2D_TILED_THIN1
:
104 p_align
= MAX2(rscreen
->tiling_info
->num_banks
,
105 (((rscreen
->tiling_info
->group_bytes
/ 8 / pixsize
)) *
106 rscreen
->tiling_info
->num_banks
)) * 8;
108 case V_038000_ARRAY_LINEAR_GENERAL
:
110 p_align
= rscreen
->tiling_info
->group_bytes
/ pixsize
;
116 static unsigned r600_get_height_alignment(struct pipe_screen
*screen
,
119 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
122 switch (array_mode
) {
123 case V_038000_ARRAY_2D_TILED_THIN1
:
124 h_align
= rscreen
->tiling_info
->num_channels
* 8;
126 case V_038000_ARRAY_1D_TILED_THIN1
:
136 static unsigned r600_get_base_alignment(struct pipe_screen
*screen
,
137 enum pipe_format format
,
140 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
141 unsigned pixsize
= util_format_get_blocksize(format
);
142 int p_align
= r600_get_pixel_alignment(screen
, format
, array_mode
);
143 int h_align
= r600_get_height_alignment(screen
, array_mode
);
146 switch (array_mode
) {
147 case V_038000_ARRAY_2D_TILED_THIN1
:
148 b_align
= MAX2(rscreen
->tiling_info
->num_banks
* rscreen
->tiling_info
->num_channels
* 8 * 8 * pixsize
,
149 p_align
* pixsize
* h_align
);
151 case V_038000_ARRAY_1D_TILED_THIN1
:
153 b_align
= rscreen
->tiling_info
->group_bytes
;
159 static unsigned mip_minify(unsigned size
, unsigned level
)
162 val
= u_minify(size
, level
);
164 val
= util_next_power_of_two(val
);
168 static unsigned r600_texture_get_stride(struct pipe_screen
*screen
,
169 struct r600_resource_texture
*rtex
,
172 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
173 unsigned width
, stride
, tile_width
;
175 if (rtex
->pitch_override
)
176 return rtex
->pitch_override
;
178 width
= mip_minify(ptex
->width0
, level
);
179 if (util_format_is_plain(ptex
->format
)) {
180 tile_width
= r600_get_pixel_alignment(screen
, ptex
->format
,
181 rtex
->array_mode
[level
]);
182 width
= align(width
, tile_width
);
184 stride
= util_format_get_stride(ptex
->format
, width
);
189 static unsigned r600_texture_get_nblocksy(struct pipe_screen
*screen
,
190 struct r600_resource_texture
*rtex
,
193 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
194 unsigned height
, tile_height
;
196 height
= mip_minify(ptex
->height0
, level
);
197 if (util_format_is_plain(ptex
->format
)) {
198 tile_height
= r600_get_height_alignment(screen
,
199 rtex
->array_mode
[level
]);
200 height
= align(height
, tile_height
);
202 return util_format_get_nblocksy(ptex
->format
, height
);
205 /* Get a width in pixels from a stride in bytes. */
206 static unsigned pitch_to_width(enum pipe_format format
, unsigned pitch_in_bytes
)
208 return (pitch_in_bytes
/ util_format_get_blocksize(format
)) *
209 util_format_get_blockwidth(format
);
212 static void r600_texture_set_array_mode(struct pipe_screen
*screen
,
213 struct r600_resource_texture
*rtex
,
214 unsigned level
, unsigned array_mode
)
216 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
218 switch (array_mode
) {
219 case V_0280A0_ARRAY_LINEAR_GENERAL
:
220 case V_0280A0_ARRAY_LINEAR_ALIGNED
:
221 case V_0280A0_ARRAY_1D_TILED_THIN1
:
223 rtex
->array_mode
[level
] = array_mode
;
225 case V_0280A0_ARRAY_2D_TILED_THIN1
:
227 unsigned w
, h
, tile_height
, tile_width
;
229 tile_height
= r600_get_height_alignment(screen
, array_mode
);
230 tile_width
= r600_get_pixel_alignment(screen
, ptex
->format
, array_mode
);
232 w
= mip_minify(ptex
->width0
, level
);
233 h
= mip_minify(ptex
->height0
, level
);
234 if (w
< tile_width
|| h
< tile_height
)
235 rtex
->array_mode
[level
] = V_0280A0_ARRAY_1D_TILED_THIN1
;
237 rtex
->array_mode
[level
] = array_mode
;
243 static void r600_setup_miptree(struct pipe_screen
*screen
,
244 struct r600_resource_texture
*rtex
,
247 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
248 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
249 enum chip_class chipc
= r600_get_family_class(radeon
);
250 unsigned pitch
, size
, layer_size
, i
, offset
;
253 for (i
= 0, offset
= 0; i
<= ptex
->last_level
; i
++) {
254 r600_texture_set_array_mode(screen
, rtex
, i
, array_mode
);
256 pitch
= r600_texture_get_stride(screen
, rtex
, i
);
257 nblocksy
= r600_texture_get_nblocksy(screen
, rtex
, i
);
259 layer_size
= pitch
* nblocksy
;
261 if (ptex
->target
== PIPE_TEXTURE_CUBE
) {
263 size
= layer_size
* 8;
265 size
= layer_size
* 6;
268 size
= layer_size
* u_minify(ptex
->depth0
, i
);
269 /* align base image and start of miptree */
270 if ((i
== 0) || (i
== 1))
271 offset
= align(offset
, r600_get_base_alignment(screen
, ptex
->format
, array_mode
));
272 rtex
->offset
[i
] = offset
;
273 rtex
->layer_size
[i
] = layer_size
;
274 rtex
->pitch_in_bytes
[i
] = pitch
;
275 rtex
->pitch_in_pixels
[i
] = pitch_to_width(ptex
->format
, pitch
);
281 /* Figure out whether u_blitter will fallback to a transfer operation.
282 * If so, don't use a staging resource.
284 static boolean
permit_hardware_blit(struct pipe_screen
*screen
,
285 const struct pipe_resource
*res
)
289 if (util_format_is_depth_or_stencil(res
->format
))
290 bind
= PIPE_BIND_DEPTH_STENCIL
;
292 bind
= PIPE_BIND_RENDER_TARGET
;
294 /* See r600_resource_copy_region: there is something wrong
295 * with depth resource copies at the moment so avoid them for
298 if (util_format_get_component_bits(res
->format
,
299 UTIL_FORMAT_COLORSPACE_ZS
,
303 if (!screen
->is_format_supported(screen
,
310 if (!screen
->is_format_supported(screen
,
314 PIPE_BIND_SAMPLER_VIEW
, 0))
320 static struct r600_resource_texture
*
321 r600_texture_create_object(struct pipe_screen
*screen
,
322 const struct pipe_resource
*base
,
324 unsigned pitch_in_bytes_override
,
325 unsigned max_buffer_size
,
328 struct r600_resource_texture
*rtex
;
329 struct r600_resource
*resource
;
330 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
332 rtex
= CALLOC_STRUCT(r600_resource_texture
);
336 resource
= &rtex
->resource
;
337 resource
->base
.b
= *base
;
338 resource
->base
.vtbl
= &r600_texture_vtbl
;
339 pipe_reference_init(&resource
->base
.b
.reference
, 1);
340 resource
->base
.b
.screen
= screen
;
342 rtex
->pitch_override
= pitch_in_bytes_override
;
343 /* only mark depth textures the HW can hit as depth textures */
344 if (util_format_is_depth_or_stencil(base
->format
) && permit_hardware_blit(screen
, base
))
349 r600_setup_miptree(screen
, rtex
, array_mode
);
351 resource
->size
= rtex
->size
;
354 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
355 int base_align
= r600_get_base_alignment(screen
, ptex
->format
, array_mode
);
357 resource
->bo
= r600_bo(radeon
, rtex
->size
, base_align
, base
->bind
, base
->usage
);
366 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
367 const struct pipe_resource
*templ
)
369 unsigned array_mode
= 0;
370 static int force_tiling
= -1;
372 /* Would like some magic "get_bool_option_once" routine.
374 if (force_tiling
== -1)
375 force_tiling
= debug_get_bool_option("R600_FORCE_TILING", FALSE
);
377 if (force_tiling
&& permit_hardware_blit(screen
, templ
)) {
378 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
379 !(templ
->bind
& PIPE_BIND_SCANOUT
)) {
380 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
384 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
389 static void r600_texture_destroy(struct pipe_screen
*screen
,
390 struct pipe_resource
*ptex
)
392 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
393 struct r600_resource
*resource
= &rtex
->resource
;
394 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
396 if (rtex
->flushed_depth_texture
)
397 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
400 r600_bo_reference(radeon
, &resource
->bo
, NULL
);
405 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
406 struct pipe_resource
*ptex
,
407 struct winsys_handle
*whandle
)
409 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
410 struct r600_resource
*resource
= &rtex
->resource
;
411 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
413 return r600_bo_get_winsys_handle(radeon
, resource
->bo
,
414 rtex
->pitch_in_bytes
[0], whandle
);
417 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
418 struct pipe_resource
*texture
,
419 const struct pipe_surface
*surf_tmpl
)
421 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
422 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
423 unsigned tile_height
;
424 unsigned level
= surf_tmpl
->u
.tex
.level
;
426 assert(surf_tmpl
->u
.tex
.first_layer
== surf_tmpl
->u
.tex
.last_layer
);
430 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
431 pipe_reference_init(&surface
->base
.reference
, 1);
432 pipe_resource_reference(&surface
->base
.texture
, texture
);
433 surface
->base
.context
= pipe
;
434 surface
->base
.format
= surf_tmpl
->format
;
435 surface
->base
.width
= mip_minify(texture
->width0
, level
);
436 surface
->base
.height
= mip_minify(texture
->height0
, level
);
437 surface
->base
.usage
= surf_tmpl
->usage
;
438 surface
->base
.texture
= texture
;
439 surface
->base
.u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
440 surface
->base
.u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
441 surface
->base
.u
.tex
.level
= level
;
443 tile_height
= r600_get_height_alignment(pipe
->screen
, rtex
->array_mode
[level
]);
444 surface
->aligned_height
= align(surface
->base
.height
, tile_height
);
445 return &surface
->base
;
448 static void r600_surface_destroy(struct pipe_context
*pipe
,
449 struct pipe_surface
*surface
)
451 pipe_resource_reference(&surface
->texture
, NULL
);
456 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
457 const struct pipe_resource
*templ
,
458 struct winsys_handle
*whandle
)
460 struct radeon
*rw
= (struct radeon
*)screen
->winsys
;
461 struct r600_bo
*bo
= NULL
;
462 unsigned array_mode
= 0;
464 /* Support only 2D textures without mipmaps */
465 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
466 templ
->depth0
!= 1 || templ
->last_level
!= 0)
469 bo
= r600_bo_handle(rw
, whandle
->handle
, &array_mode
);
474 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
480 static unsigned int r600_texture_is_referenced(struct pipe_context
*context
,
481 struct pipe_resource
*texture
,
482 unsigned level
, int layer
)
485 return PIPE_REFERENCED_FOR_READ
| PIPE_REFERENCED_FOR_WRITE
;
488 int r600_texture_depth_flush(struct pipe_context
*ctx
,
489 struct pipe_resource
*texture
)
491 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
492 struct pipe_resource resource
;
494 if (rtex
->flushed_depth_texture
)
497 resource
.target
= PIPE_TEXTURE_2D
;
498 resource
.format
= texture
->format
;
499 resource
.width0
= texture
->width0
;
500 resource
.height0
= texture
->height0
;
502 resource
.last_level
= 0;
503 resource
.nr_samples
= 0;
504 resource
.usage
= PIPE_USAGE_DYNAMIC
;
506 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
508 resource
.bind
|= PIPE_BIND_DEPTH_STENCIL
;
510 rtex
->flushed_depth_texture
= (struct r600_resource_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
511 if (rtex
->flushed_depth_texture
== NULL
) {
512 R600_ERR("failed to create temporary texture to hold untiled copy\n");
516 ((struct r600_resource_texture
*)rtex
->flushed_depth_texture
)->is_flushing_texture
= TRUE
;
518 /* XXX: only do this if the depth texture has actually changed:
520 r600_blit_uncompress_depth(ctx
, rtex
);
524 /* Needs adjustment for pixelformat:
526 static INLINE
unsigned u_box_volume( const struct pipe_box
*box
)
528 return box
->width
* box
->depth
* box
->height
;
531 struct pipe_transfer
* r600_texture_get_transfer(struct pipe_context
*ctx
,
532 struct pipe_resource
*texture
,
535 const struct pipe_box
*box
)
537 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
538 struct pipe_resource resource
;
539 struct r600_transfer
*trans
;
541 boolean use_staging_texture
= FALSE
;
543 /* We cannot map a tiled texture directly because the data is
544 * in a different order, therefore we do detiling using a blit.
546 * Also, use a temporary in GTT memory for read transfers, as
547 * the CPU is much happier reading out of cached system memory
548 * than uncached VRAM.
551 use_staging_texture
= TRUE
;
553 if ((usage
& PIPE_TRANSFER_READ
) && u_box_volume(box
) > 1024)
554 use_staging_texture
= TRUE
;
556 /* XXX: Use a staging texture for uploads if the underlying BO
557 * is busy. No interface for checking that currently? so do
558 * it eagerly whenever the transfer doesn't require a readback
561 if ((usage
& PIPE_TRANSFER_WRITE
) &&
562 !(usage
& (PIPE_TRANSFER_READ
|
563 PIPE_TRANSFER_DONTBLOCK
|
564 PIPE_TRANSFER_UNSYNCHRONIZED
)))
565 use_staging_texture
= TRUE
;
567 if (!permit_hardware_blit(ctx
->screen
, texture
) ||
568 (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
))
569 use_staging_texture
= FALSE
;
571 trans
= CALLOC_STRUCT(r600_transfer
);
574 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
575 trans
->transfer
.level
= level
;
576 trans
->transfer
.usage
= usage
;
577 trans
->transfer
.box
= *box
;
579 /* XXX: only readback the rectangle which is being mapped?
581 /* XXX: when discard is true, no need to read back from depth texture
583 r
= r600_texture_depth_flush(ctx
, texture
);
585 R600_ERR("failed to create temporary texture to hold untiled copy\n");
586 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
590 trans
->transfer
.stride
= rtex
->flushed_depth_texture
->pitch_in_bytes
[level
];
591 trans
->offset
= r600_texture_get_offset(rtex
->flushed_depth_texture
, level
, box
->z
);
592 return &trans
->transfer
;
593 } else if (use_staging_texture
) {
594 resource
.target
= PIPE_TEXTURE_2D
;
595 resource
.format
= texture
->format
;
596 resource
.width0
= box
->width
;
597 resource
.height0
= box
->height
;
599 resource
.array_size
= 1;
600 resource
.last_level
= 0;
601 resource
.nr_samples
= 0;
602 resource
.usage
= PIPE_USAGE_STAGING
;
604 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
605 /* For texture reading, the temporary (detiled) texture is used as
606 * a render target when blitting from a tiled texture. */
607 if (usage
& PIPE_TRANSFER_READ
) {
608 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
610 /* For texture writing, the temporary texture is used as a sampler
611 * when blitting into a tiled texture. */
612 if (usage
& PIPE_TRANSFER_WRITE
) {
613 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
615 /* Create the temporary texture. */
616 trans
->staging_texture
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
617 if (trans
->staging_texture
== NULL
) {
618 R600_ERR("failed to create temporary texture to hold untiled copy\n");
619 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
624 trans
->transfer
.stride
=
625 ((struct r600_resource_texture
*)trans
->staging_texture
)->pitch_in_bytes
[0];
626 if (usage
& PIPE_TRANSFER_READ
) {
627 r600_copy_to_staging_texture(ctx
, trans
);
628 /* Always referenced in the blit. */
629 ctx
->flush(ctx
, 0, NULL
);
631 return &trans
->transfer
;
633 trans
->transfer
.stride
= rtex
->pitch_in_bytes
[level
];
634 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
635 return &trans
->transfer
;
638 void r600_texture_transfer_destroy(struct pipe_context
*ctx
,
639 struct pipe_transfer
*transfer
)
641 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
643 if (rtransfer
->staging_texture
) {
644 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
645 r600_copy_from_staging_texture(ctx
, rtransfer
);
647 pipe_resource_reference(&rtransfer
->staging_texture
, NULL
);
649 pipe_resource_reference(&transfer
->resource
, NULL
);
653 void* r600_texture_transfer_map(struct pipe_context
*ctx
,
654 struct pipe_transfer
* transfer
)
656 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
658 enum pipe_format format
= transfer
->resource
->format
;
659 struct radeon
*radeon
= (struct radeon
*)ctx
->screen
->winsys
;
664 if (rtransfer
->staging_texture
) {
665 bo
= ((struct r600_resource
*)rtransfer
->staging_texture
)->bo
;
667 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
669 if (rtex
->flushed_depth_texture
)
670 bo
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->bo
;
672 bo
= ((struct r600_resource
*)transfer
->resource
)->bo
;
674 offset
= rtransfer
->offset
+
675 transfer
->box
.y
/ util_format_get_blockheight(format
) * transfer
->stride
+
676 transfer
->box
.x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
679 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
680 usage
|= PB_USAGE_CPU_WRITE
;
682 if (transfer
->usage
& PIPE_TRANSFER_DISCARD
) {
685 if (transfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
) {
689 if (transfer
->usage
& PIPE_TRANSFER_READ
) {
690 usage
|= PB_USAGE_CPU_READ
;
693 if (transfer
->usage
& PIPE_TRANSFER_DONTBLOCK
) {
694 usage
|= PB_USAGE_DONTBLOCK
;
697 if (transfer
->usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
698 usage
|= PB_USAGE_UNSYNCHRONIZED
;
701 map
= r600_bo_map(radeon
, bo
, usage
, ctx
);
709 void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
710 struct pipe_transfer
* transfer
)
712 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
713 struct radeon
*radeon
= (struct radeon
*)ctx
->screen
->winsys
;
716 if (rtransfer
->staging_texture
) {
717 bo
= ((struct r600_resource
*)rtransfer
->staging_texture
)->bo
;
719 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
721 if (rtex
->flushed_depth_texture
) {
722 bo
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->bo
;
724 bo
= ((struct r600_resource
*)transfer
->resource
)->bo
;
727 r600_bo_unmap(radeon
, bo
);
730 struct u_resource_vtbl r600_texture_vtbl
=
732 r600_texture_get_handle
, /* get_handle */
733 r600_texture_destroy
, /* resource_destroy */
734 r600_texture_is_referenced
, /* is_resource_referenced */
735 r600_texture_get_transfer
, /* get_transfer */
736 r600_texture_transfer_destroy
, /* transfer_destroy */
737 r600_texture_transfer_map
, /* transfer_map */
738 u_default_transfer_flush_region
,/* transfer_flush_region */
739 r600_texture_transfer_unmap
, /* transfer_unmap */
740 u_default_transfer_inline_write
/* transfer_inline_write */
743 void r600_init_surface_functions(struct r600_pipe_context
*r600
)
745 r600
->context
.create_surface
= r600_create_surface
;
746 r600
->context
.surface_destroy
= r600_surface_destroy
;
749 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
750 const unsigned char *swizzle_view
)
753 unsigned char swizzle
[4];
755 const uint32_t swizzle_shift
[4] = {
758 const uint32_t swizzle_bit
[4] = {
763 /* Combine two sets of swizzles. */
764 for (i
= 0; i
< 4; i
++) {
765 swizzle
[i
] = swizzle_view
[i
] <= UTIL_FORMAT_SWIZZLE_W
?
766 swizzle_format
[swizzle_view
[i
]] : swizzle_view
[i
];
769 memcpy(swizzle
, swizzle_format
, 4);
773 for (i
= 0; i
< 4; i
++) {
774 switch (swizzle
[i
]) {
775 case UTIL_FORMAT_SWIZZLE_Y
:
776 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
778 case UTIL_FORMAT_SWIZZLE_Z
:
779 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
781 case UTIL_FORMAT_SWIZZLE_W
:
782 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
784 case UTIL_FORMAT_SWIZZLE_0
:
785 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
787 case UTIL_FORMAT_SWIZZLE_1
:
788 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
790 default: /* UTIL_FORMAT_SWIZZLE_X */
791 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
797 /* texture format translate */
798 uint32_t r600_translate_texformat(enum pipe_format format
,
799 const unsigned char *swizzle_view
,
800 uint32_t *word4_p
, uint32_t *yuv_format_p
)
802 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
803 const struct util_format_description
*desc
;
804 boolean uniform
= TRUE
;
806 const uint32_t sign_bit
[4] = {
807 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
808 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
809 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
810 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
812 desc
= util_format_description(format
);
814 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
816 /* Colorspace (return non-RGB formats directly). */
817 switch (desc
->colorspace
) {
818 /* Depth stencil formats */
819 case UTIL_FORMAT_COLORSPACE_ZS
:
821 case PIPE_FORMAT_Z16_UNORM
:
824 case PIPE_FORMAT_X24S8_USCALED
:
825 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
826 case PIPE_FORMAT_Z24X8_UNORM
:
827 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
830 case PIPE_FORMAT_S8X24_USCALED
:
831 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
832 case PIPE_FORMAT_X8Z24_UNORM
:
833 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
836 case PIPE_FORMAT_S8_USCALED
:
838 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
844 case UTIL_FORMAT_COLORSPACE_YUV
:
845 yuv_format
|= (1 << 30);
847 case PIPE_FORMAT_UYVY
:
848 case PIPE_FORMAT_YUYV
:
852 goto out_unknown
; /* TODO */
854 case UTIL_FORMAT_COLORSPACE_SRGB
:
855 word4
|= S_038010_FORCE_DEGAMMA(1);
856 if (format
== PIPE_FORMAT_L8A8_SRGB
|| format
== PIPE_FORMAT_L8_SRGB
)
857 goto out_unknown
; /* fails for some reason - TODO */
864 /* S3TC formats. TODO */
865 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
866 static int r600_enable_s3tc
= -1;
868 if (r600_enable_s3tc
== -1)
870 debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
872 if (!r600_enable_s3tc
)
876 case PIPE_FORMAT_DXT1_RGB
:
877 case PIPE_FORMAT_DXT1_RGBA
:
880 case PIPE_FORMAT_DXT3_RGBA
:
883 case PIPE_FORMAT_DXT5_RGBA
:
892 for (i
= 0; i
< desc
->nr_channels
; i
++) {
893 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
894 word4
|= sign_bit
[i
];
898 /* R8G8Bx_SNORM - TODO CxV8U8 */
902 /* See whether the components are of the same size. */
903 for (i
= 1; i
< desc
->nr_channels
; i
++) {
904 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
907 /* Non-uniform formats. */
909 switch(desc
->nr_channels
) {
911 if (desc
->channel
[0].size
== 5 &&
912 desc
->channel
[1].size
== 6 &&
913 desc
->channel
[2].size
== 5) {
919 if (desc
->channel
[0].size
== 5 &&
920 desc
->channel
[1].size
== 5 &&
921 desc
->channel
[2].size
== 5 &&
922 desc
->channel
[3].size
== 1) {
923 result
= FMT_1_5_5_5
;
926 if (desc
->channel
[0].size
== 10 &&
927 desc
->channel
[1].size
== 10 &&
928 desc
->channel
[2].size
== 10 &&
929 desc
->channel
[3].size
== 2) {
930 result
= FMT_2_10_10_10
;
938 /* Find the first non-VOID channel. */
939 for (i
= 0; i
< 4; i
++) {
940 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
948 /* uniform formats */
949 switch (desc
->channel
[i
].type
) {
950 case UTIL_FORMAT_TYPE_UNSIGNED
:
951 case UTIL_FORMAT_TYPE_SIGNED
:
952 if (!desc
->channel
[i
].normalized
&&
953 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
957 switch (desc
->channel
[i
].size
) {
959 switch (desc
->nr_channels
) {
964 result
= FMT_4_4_4_4
;
969 switch (desc
->nr_channels
) {
977 result
= FMT_8_8_8_8
;
982 switch (desc
->nr_channels
) {
990 result
= FMT_16_16_16_16
;
996 case UTIL_FORMAT_TYPE_FLOAT
:
997 switch (desc
->channel
[i
].size
) {
999 switch (desc
->nr_channels
) {
1001 result
= FMT_16_FLOAT
;
1004 result
= FMT_16_16_FLOAT
;
1007 result
= FMT_16_16_16_16_FLOAT
;
1012 switch (desc
->nr_channels
) {
1014 result
= FMT_32_FLOAT
;
1017 result
= FMT_32_32_FLOAT
;
1020 result
= FMT_32_32_32_32_FLOAT
;
1030 *yuv_format_p
= yuv_format
;
1033 // R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));