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r600g: add htile support v16
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34
35 /* Copy from a full GPU texture to a transfer's staging one. */
36 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
37 {
38 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
39 struct pipe_resource *dst = &rtransfer->staging->b.b;
40 struct pipe_resource *src = transfer->resource;
41
42 if (src->nr_samples <= 1) {
43 ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
44 src, transfer->level, &transfer->box);
45 } else {
46 /* Resolve the resource. */
47 struct pipe_blit_info blit;
48
49 memset(&blit, 0, sizeof(blit));
50 blit.src.resource = src;
51 blit.src.format = src->format;
52 blit.src.level = transfer->level;
53 blit.src.box = transfer->box;
54 blit.dst.resource = dst;
55 blit.dst.format = dst->format;
56 blit.dst.box.width = transfer->box.width;
57 blit.dst.box.height = transfer->box.height;
58 blit.dst.box.depth = transfer->box.depth;
59 blit.mask = PIPE_MASK_RGBA;
60 blit.filter = PIPE_TEX_FILTER_NEAREST;
61
62 ctx->blit(ctx, &blit);
63 }
64 }
65
66 /* Copy from a transfer's staging texture to a full GPU one. */
67 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
68 {
69 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
70 struct pipe_resource *texture = transfer->resource;
71 struct pipe_box sbox;
72
73 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
74
75 ctx->resource_copy_region(ctx, texture, transfer->level,
76 transfer->box.x, transfer->box.y, transfer->box.z,
77 &rtransfer->staging->b.b,
78 0, &sbox);
79 }
80
81 unsigned r600_texture_get_offset(struct r600_texture *rtex,
82 unsigned level, unsigned layer)
83 {
84 return rtex->surface.level[level].offset +
85 layer * rtex->surface.level[level].slice_size;
86 }
87
88 static int r600_init_surface(struct r600_screen *rscreen,
89 struct radeon_surface *surface,
90 const struct pipe_resource *ptex,
91 unsigned array_mode,
92 bool is_flushed_depth)
93 {
94 const struct util_format_description *desc =
95 util_format_description(ptex->format);
96 bool is_depth, is_stencil;
97
98 is_depth = util_format_has_depth(desc);
99 is_stencil = util_format_has_stencil(desc);
100
101 surface->npix_x = ptex->width0;
102 surface->npix_y = ptex->height0;
103 surface->npix_z = ptex->depth0;
104 surface->blk_w = util_format_get_blockwidth(ptex->format);
105 surface->blk_h = util_format_get_blockheight(ptex->format);
106 surface->blk_d = 1;
107 surface->array_size = 1;
108 surface->last_level = ptex->last_level;
109
110 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
111 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
112 surface->bpe = 4; /* stencil is allocated separately on evergreen */
113 } else {
114 surface->bpe = util_format_get_blocksize(ptex->format);
115 /* align byte per element on dword */
116 if (surface->bpe == 3) {
117 surface->bpe = 4;
118 }
119 }
120
121 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
122 surface->flags = 0;
123
124 switch (array_mode) {
125 case V_038000_ARRAY_1D_TILED_THIN1:
126 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
127 break;
128 case V_038000_ARRAY_2D_TILED_THIN1:
129 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
130 break;
131 case V_038000_ARRAY_LINEAR_ALIGNED:
132 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
133 break;
134 case V_038000_ARRAY_LINEAR_GENERAL:
135 default:
136 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
137 break;
138 }
139 switch (ptex->target) {
140 case PIPE_TEXTURE_1D:
141 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
142 break;
143 case PIPE_TEXTURE_RECT:
144 case PIPE_TEXTURE_2D:
145 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
146 break;
147 case PIPE_TEXTURE_3D:
148 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
149 break;
150 case PIPE_TEXTURE_1D_ARRAY:
151 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
152 surface->array_size = ptex->array_size;
153 break;
154 case PIPE_TEXTURE_2D_ARRAY:
155 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d layout for now */
156 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
157 surface->array_size = ptex->array_size;
158 break;
159 case PIPE_TEXTURE_CUBE:
160 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
161 break;
162 case PIPE_BUFFER:
163 default:
164 return -EINVAL;
165 }
166 if (ptex->bind & PIPE_BIND_SCANOUT) {
167 surface->flags |= RADEON_SURF_SCANOUT;
168 }
169
170 if (!is_flushed_depth && is_depth) {
171 surface->flags |= RADEON_SURF_ZBUFFER;
172
173 if (is_stencil) {
174 surface->flags |= RADEON_SURF_SBUFFER |
175 RADEON_SURF_HAS_SBUFFER_MIPTREE;
176 }
177 }
178 return 0;
179 }
180
181 static int r600_setup_surface(struct pipe_screen *screen,
182 struct r600_texture *rtex,
183 unsigned pitch_in_bytes_override)
184 {
185 struct pipe_resource *ptex = &rtex->resource.b.b;
186 struct r600_screen *rscreen = (struct r600_screen*)screen;
187 unsigned i;
188 int r;
189
190 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
191 if (r) {
192 return r;
193 }
194 rtex->size = rtex->surface.bo_size;
195 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
196 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
197 * for those
198 */
199 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
200 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
201 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
202 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
203 rtex->surface.stencil_offset =
204 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
205 }
206 }
207 for (i = 0; i <= ptex->last_level; i++) {
208 switch (rtex->surface.level[i].mode) {
209 case RADEON_SURF_MODE_LINEAR_ALIGNED:
210 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
211 break;
212 case RADEON_SURF_MODE_1D:
213 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
214 break;
215 case RADEON_SURF_MODE_2D:
216 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
217 break;
218 default:
219 case RADEON_SURF_MODE_LINEAR:
220 rtex->array_mode[i] = 0;
221 break;
222 }
223 }
224 return 0;
225 }
226
227 static boolean r600_texture_get_handle(struct pipe_screen* screen,
228 struct pipe_resource *ptex,
229 struct winsys_handle *whandle)
230 {
231 struct r600_texture *rtex = (struct r600_texture*)ptex;
232 struct r600_resource *resource = &rtex->resource;
233 struct radeon_surface *surface = &rtex->surface;
234 struct r600_screen *rscreen = (struct r600_screen*)screen;
235
236 rscreen->ws->buffer_set_tiling(resource->buf,
237 NULL,
238 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
239 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
240 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
241 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
242 surface->bankw, surface->bankh,
243 surface->tile_split,
244 surface->stencil_tile_split,
245 surface->mtilea,
246 rtex->surface.level[0].pitch_bytes);
247
248 return rscreen->ws->buffer_get_handle(resource->buf,
249 rtex->surface.level[0].pitch_bytes, whandle);
250 }
251
252 static void r600_texture_destroy(struct pipe_screen *screen,
253 struct pipe_resource *ptex)
254 {
255 struct r600_texture *rtex = (struct r600_texture*)ptex;
256 struct r600_resource *resource = &rtex->resource;
257
258 if (rtex->flushed_depth_texture)
259 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
260
261 pb_reference(&resource->buf, NULL);
262 FREE(rtex);
263 }
264
265 static const struct u_resource_vtbl r600_texture_vtbl;
266
267 /* The number of samples can be specified independently of the texture. */
268 void r600_texture_get_fmask_info(struct r600_screen *rscreen,
269 struct r600_texture *rtex,
270 unsigned nr_samples,
271 struct r600_fmask_info *out)
272 {
273 /* FMASK is allocated pretty much like an ordinary texture.
274 * Here we use bpe in the units of bits, not bytes. */
275 struct radeon_surface fmask = rtex->surface;
276
277 switch (nr_samples) {
278 case 2:
279 /* This should be 8,1, but we should set nsamples > 1
280 * for the allocator to treat it as a multisample surface.
281 * Let's set 4,2 then. */
282 case 4:
283 fmask.bpe = 4;
284 fmask.nsamples = 2;
285 break;
286 case 8:
287 fmask.bpe = 8;
288 fmask.nsamples = 4;
289 break;
290 case 16:
291 fmask.bpe = 16;
292 fmask.nsamples = 4;
293 break;
294 default:
295 R600_ERR("Invalid sample count for FMASK allocation.\n");
296 return;
297 }
298
299 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
300 if (rscreen->chip_class <= R700) {
301 fmask.bpe *= 2;
302 }
303
304 if (rscreen->chip_class >= EVERGREEN) {
305 fmask.bankh = nr_samples <= 4 ? 4 : 1;
306 }
307
308 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
309 R600_ERR("Got error in surface_init while allocating FMASK.\n");
310 return;
311 }
312 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
313
314 out->bank_height = fmask.bankh;
315 out->alignment = MAX2(256, fmask.bo_alignment);
316 out->size = (fmask.bo_size + 7) / 8;
317 }
318
319 static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
320 struct r600_texture *rtex)
321 {
322 struct r600_fmask_info fmask;
323
324 r600_texture_get_fmask_info(rscreen, rtex,
325 rtex->resource.b.b.nr_samples, &fmask);
326
327 /* Reserve space for FMASK while converting bits back to bytes. */
328 rtex->fmask_bank_height = fmask.bank_height;
329 rtex->fmask_offset = align(rtex->size, fmask.alignment);
330 rtex->fmask_size = fmask.size;
331 rtex->size = rtex->fmask_offset + rtex->fmask_size;
332 #if 0
333 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
334 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
335 #endif
336 }
337
338 void r600_texture_get_cmask_info(struct r600_screen *rscreen,
339 struct r600_texture *rtex,
340 struct r600_cmask_info *out)
341 {
342 unsigned cmask_tile_width = 8;
343 unsigned cmask_tile_height = 8;
344 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
345 unsigned element_bits = 4;
346 unsigned cmask_cache_bits = 1024;
347 unsigned num_pipes = rscreen->tiling_info.num_channels;
348 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
349
350 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
351 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
352 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
353 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
354 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
355
356 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
357 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
358
359 unsigned base_align = num_pipes * pipe_interleave_bytes;
360 unsigned slice_bytes =
361 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
362
363 assert(macro_tile_width % 128 == 0);
364 assert(macro_tile_height % 128 == 0);
365
366 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
367 out->alignment = MAX2(256, base_align);
368 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
369 }
370
371 static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
372 struct r600_texture *rtex)
373 {
374 struct r600_cmask_info cmask;
375
376 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
377
378 rtex->cmask_slice_tile_max = cmask.slice_tile_max;
379 rtex->cmask_offset = align(rtex->size, cmask.alignment);
380 rtex->cmask_size = cmask.size;
381 rtex->size = rtex->cmask_offset + rtex->cmask_size;
382 #if 0
383 printf("CMASK: macro tile width = %u, macro tile height = %u, "
384 "pitch elements = %u, height = %u, slice tile max = %u\n",
385 macro_tile_width, macro_tile_height, pitch_elements, height,
386 rtex->cmask_slice_tile_max);
387 #endif
388 }
389
390 DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "R600_PRINT_TEXDEPTH", FALSE);
391
392 static struct r600_texture *
393 r600_texture_create_object(struct pipe_screen *screen,
394 const struct pipe_resource *base,
395 unsigned pitch_in_bytes_override,
396 struct pb_buffer *buf,
397 boolean alloc_bo,
398 struct radeon_surface *surface)
399 {
400 struct r600_texture *rtex;
401 struct r600_resource *resource;
402 struct r600_screen *rscreen = (struct r600_screen*)screen;
403 int r;
404
405 rtex = CALLOC_STRUCT(r600_texture);
406 if (rtex == NULL)
407 return NULL;
408
409 resource = &rtex->resource;
410 resource->b.b = *base;
411 resource->b.vtbl = &r600_texture_vtbl;
412 pipe_reference_init(&resource->b.b.reference, 1);
413 resource->b.b.screen = screen;
414 rtex->pitch_override = pitch_in_bytes_override;
415
416 /* don't include stencil-only formats which we don't support for rendering */
417 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
418
419 rtex->surface = *surface;
420 r = r600_setup_surface(screen, rtex,
421 pitch_in_bytes_override);
422 if (r) {
423 FREE(rtex);
424 return NULL;
425 }
426
427 if (base->nr_samples > 1 && !rtex->is_depth && alloc_bo) {
428 r600_texture_allocate_cmask(rscreen, rtex);
429 r600_texture_allocate_fmask(rscreen, rtex);
430 }
431
432 if (!rtex->is_depth && base->nr_samples > 1 &&
433 (!rtex->fmask_size || !rtex->cmask_size)) {
434 FREE(rtex);
435 return NULL;
436 }
437
438 /* Tiled depth textures utilize the non-displayable tile order. */
439 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
440
441 /* only enable hyperz for PIPE_TEXTURE_2D not for PIPE_TEXTURE_2D_ARRAY
442 * Thought it might still be interessting to use hyperz for texture
443 * array without using fast clear features
444 */
445 rtex->htile = NULL;
446 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER | R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
447 util_format_is_depth_or_stencil(base->format) &&
448 rscreen->use_hyperz &&
449 base->target == PIPE_TEXTURE_2D &&
450 rtex->surface.level[0].nblk_x >= 32 &&
451 rtex->surface.level[0].nblk_y >= 32) {
452 unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
453 unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
454 unsigned htile_size;
455 unsigned npipes = rscreen->info.r600_num_tile_pipes;
456
457 /* this alignment and htile size only apply to linear htile buffer */
458 sw = align(sw, 16 << 3);
459 sh = align(sh, npipes << 3);
460 htile_size = (sw >> 3) * (sh >> 3) * 4;
461 /* must be aligned with 2K * npipes */
462 htile_size = align(htile_size, (2 << 10) * npipes);
463
464 rtex->htile = (struct r600_resource*)pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
465 PIPE_USAGE_STATIC, htile_size);
466 if (rtex->htile == NULL) {
467 /* this is not a fatal error as we can still keep rendering
468 * without htile buffer
469 */
470 R600_ERR("r600: failed to create bo for htile buffers\n");
471 } else {
472 void *ptr;
473 ptr = rscreen->ws->buffer_map(rtex->htile->cs_buf, NULL, PIPE_TRANSFER_WRITE);
474 memset(ptr, 0x0, htile_size);
475 rscreen->ws->buffer_unmap(rtex->htile->cs_buf);
476 }
477 }
478
479 /* Now create the backing buffer. */
480 if (!buf && alloc_bo) {
481 unsigned base_align = rtex->surface.bo_alignment;
482 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
483
484 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
485 FREE(rtex);
486 return NULL;
487 }
488 } else if (buf) {
489 /* This is usually the window framebuffer. We want it in VRAM, always. */
490 resource->buf = buf;
491 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
492 resource->domains = RADEON_DOMAIN_VRAM;
493 }
494
495 if (rtex->cmask_size) {
496 /* Initialize the cmask to 0xCC (= compressed state). */
497 char *ptr = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE);
498 memset(ptr + rtex->cmask_offset, 0xCC, rtex->cmask_size);
499 rscreen->ws->buffer_unmap(resource->cs_buf);
500 }
501
502 if (debug_get_option_print_texdepth() && rtex->is_depth && rtex->non_disp_tiling) {
503 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
504 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
505 "bpe=%u, nsamples=%u, flags=%u\n",
506 rtex->surface.npix_x, rtex->surface.npix_y,
507 rtex->surface.npix_z, rtex->surface.blk_w,
508 rtex->surface.blk_h, rtex->surface.blk_d,
509 rtex->surface.array_size, rtex->surface.last_level,
510 rtex->surface.bpe, rtex->surface.nsamples,
511 rtex->surface.flags);
512 if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
513 for (int i = 0; i <= rtex->surface.last_level; i++) {
514 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
515 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
516 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
517 i, (unsigned long long)rtex->surface.level[i].offset,
518 (unsigned long long)rtex->surface.level[i].slice_size,
519 rtex->surface.level[i].npix_x,
520 rtex->surface.level[i].npix_y,
521 rtex->surface.level[i].npix_z,
522 rtex->surface.level[i].nblk_x,
523 rtex->surface.level[i].nblk_y,
524 rtex->surface.level[i].nblk_z,
525 rtex->surface.level[i].pitch_bytes,
526 rtex->surface.level[i].mode);
527 }
528 }
529 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
530 for (int i = 0; i <= rtex->surface.last_level; i++) {
531 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
532 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
533 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
534 i, (unsigned long long)rtex->surface.stencil_level[i].offset,
535 (unsigned long long)rtex->surface.stencil_level[i].slice_size,
536 rtex->surface.stencil_level[i].npix_x,
537 rtex->surface.stencil_level[i].npix_y,
538 rtex->surface.stencil_level[i].npix_z,
539 rtex->surface.stencil_level[i].nblk_x,
540 rtex->surface.stencil_level[i].nblk_y,
541 rtex->surface.stencil_level[i].nblk_z,
542 rtex->surface.stencil_level[i].pitch_bytes,
543 rtex->surface.stencil_level[i].mode);
544 }
545 }
546 }
547 return rtex;
548 }
549
550 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
551 const struct pipe_resource *templ)
552 {
553 struct r600_screen *rscreen = (struct r600_screen*)screen;
554 struct radeon_surface surface;
555 const struct util_format_description *desc = util_format_description(templ->format);
556 unsigned array_mode;
557 int r;
558
559 /* Default tiling mode for staging textures. */
560 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
561
562 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
563 * because 422 formats are used for videos, which prefer linear buffers
564 * for fast uploads anyway. */
565 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
566 desc->layout != UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
567 if (!(templ->bind & PIPE_BIND_SCANOUT) &&
568 templ->usage != PIPE_USAGE_STAGING &&
569 templ->usage != PIPE_USAGE_STREAM &&
570 templ->target != PIPE_TEXTURE_1D &&
571 templ->target != PIPE_TEXTURE_1D_ARRAY &&
572 templ->height0 > 3) {
573 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
574 } else if (util_format_is_compressed(templ->format)) {
575 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
576 }
577 }
578
579 r = r600_init_surface(rscreen, &surface, templ, array_mode,
580 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
581 if (r) {
582 return NULL;
583 }
584 r = rscreen->ws->surface_best(rscreen->ws, &surface);
585 if (r) {
586 return NULL;
587 }
588 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
589 0, NULL, TRUE, &surface);
590 }
591
592 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
593 struct pipe_resource *texture,
594 const struct pipe_surface *templ,
595 unsigned width, unsigned height)
596 {
597 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
598
599 assert(templ->u.tex.first_layer <= u_max_layer(texture, templ->u.tex.level));
600 assert(templ->u.tex.last_layer <= u_max_layer(texture, templ->u.tex.level));
601 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
602 if (surface == NULL)
603 return NULL;
604 pipe_reference_init(&surface->base.reference, 1);
605 pipe_resource_reference(&surface->base.texture, texture);
606 surface->base.context = pipe;
607 surface->base.format = templ->format;
608 surface->base.width = width;
609 surface->base.height = height;
610 surface->base.u = templ->u;
611 return &surface->base;
612 }
613
614 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
615 struct pipe_resource *texture,
616 const struct pipe_surface *templ)
617 {
618 struct r600_texture *rtex = (struct r600_texture*)texture;
619 unsigned level = templ->u.tex.level;
620
621 return r600_create_surface_custom(pipe, texture, templ,
622 rtex->surface.level[level].npix_x,
623 rtex->surface.level[level].npix_y);
624 }
625
626 static void r600_surface_destroy(struct pipe_context *pipe,
627 struct pipe_surface *surface)
628 {
629 struct r600_surface *surf = (struct r600_surface*)surface;
630 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
631 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
632 pipe_resource_reference(&surface->texture, NULL);
633 FREE(surface);
634 }
635
636 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
637 const struct pipe_resource *templ,
638 struct winsys_handle *whandle)
639 {
640 struct r600_screen *rscreen = (struct r600_screen*)screen;
641 struct pb_buffer *buf = NULL;
642 unsigned stride = 0;
643 unsigned array_mode = 0;
644 enum radeon_bo_layout micro, macro;
645 struct radeon_surface surface;
646 int r;
647
648 /* Support only 2D textures without mipmaps */
649 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
650 templ->depth0 != 1 || templ->last_level != 0)
651 return NULL;
652
653 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
654 if (!buf)
655 return NULL;
656
657 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
658 &surface.bankw, &surface.bankh,
659 &surface.tile_split,
660 &surface.stencil_tile_split,
661 &surface.mtilea);
662
663 if (macro == RADEON_LAYOUT_TILED)
664 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
665 else if (micro == RADEON_LAYOUT_TILED)
666 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
667 else
668 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
669
670 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
671 if (r) {
672 return NULL;
673 }
674 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
675 stride, buf, FALSE, &surface);
676 }
677
678 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
679 struct pipe_resource *texture,
680 struct r600_texture **staging)
681 {
682 struct r600_texture *rtex = (struct r600_texture*)texture;
683 struct pipe_resource resource;
684 struct r600_texture **flushed_depth_texture = staging ?
685 staging : &rtex->flushed_depth_texture;
686
687 if (!staging && rtex->flushed_depth_texture)
688 return true; /* it's ready */
689
690 resource.target = texture->target;
691 resource.format = texture->format;
692 resource.width0 = texture->width0;
693 resource.height0 = texture->height0;
694 resource.depth0 = texture->depth0;
695 resource.array_size = texture->array_size;
696 resource.last_level = texture->last_level;
697 resource.nr_samples = texture->nr_samples;
698 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
699 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
700 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
701
702 if (staging)
703 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
704
705 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
706 if (*flushed_depth_texture == NULL) {
707 R600_ERR("failed to create temporary texture to hold flushed depth\n");
708 return false;
709 }
710
711 (*flushed_depth_texture)->is_flushing_texture = TRUE;
712 (*flushed_depth_texture)->non_disp_tiling = false;
713 return true;
714 }
715
716 static void *r600_texture_transfer_map(struct pipe_context *ctx,
717 struct pipe_resource *texture,
718 unsigned level,
719 unsigned usage,
720 const struct pipe_box *box,
721 struct pipe_transfer **ptransfer)
722 {
723 struct r600_context *rctx = (struct r600_context*)ctx;
724 struct r600_texture *rtex = (struct r600_texture*)texture;
725 struct pipe_resource resource;
726 struct r600_transfer *trans;
727 boolean use_staging_texture = FALSE;
728 enum pipe_format format = texture->format;
729 struct radeon_winsys_cs_handle *buf;
730 unsigned offset = 0;
731 char *map;
732
733 if ((texture->bind & PIPE_BIND_GLOBAL) && texture->target == PIPE_BUFFER) {
734 return r600_compute_global_transfer_map(ctx, texture, level, usage, box, ptransfer);
735 }
736
737 /* We cannot map a tiled texture directly because the data is
738 * in a different order, therefore we do detiling using a blit.
739 *
740 * Also, use a temporary in GTT memory for read transfers, as
741 * the CPU is much happier reading out of cached system memory
742 * than uncached VRAM.
743 */
744 if (R600_TEX_IS_TILED(rtex, level)) {
745 use_staging_texture = TRUE;
746 }
747
748 /* Use a staging texture for uploads if the underlying BO is busy. */
749 if (!(usage & PIPE_TRANSFER_READ) &&
750 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
751 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
752 use_staging_texture = TRUE;
753 }
754
755 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
756 use_staging_texture = FALSE;
757 }
758
759 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
760 return NULL;
761 }
762
763 trans = CALLOC_STRUCT(r600_transfer);
764 if (trans == NULL)
765 return NULL;
766 trans->transfer.resource = texture;
767 trans->transfer.level = level;
768 trans->transfer.usage = usage;
769 trans->transfer.box = *box;
770 if (rtex->is_depth) {
771 /* XXX: only readback the rectangle which is being mapped?
772 */
773 /* XXX: when discard is true, no need to read back from depth texture
774 */
775 struct r600_texture *staging_depth;
776
777 assert(rtex->resource.b.b.nr_samples <= 1);
778 if (rtex->resource.b.b.nr_samples > 1) {
779 R600_ERR("mapping MSAA zbuffer unimplemented\n");
780 FREE(trans);
781 return NULL;
782 }
783
784 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
785 R600_ERR("failed to create temporary texture to hold untiled copy\n");
786 FREE(trans);
787 return NULL;
788 }
789
790 r600_blit_decompress_depth(ctx, rtex, staging_depth,
791 level, level,
792 box->z, box->z + box->depth - 1,
793 0, 0);
794
795 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
796 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
797 trans->staging = (struct r600_resource*)staging_depth;
798 } else if (use_staging_texture) {
799 resource.target = PIPE_TEXTURE_2D;
800 resource.format = texture->format;
801 resource.width0 = box->width;
802 resource.height0 = box->height;
803 resource.depth0 = 1;
804 resource.array_size = 1;
805 resource.last_level = 0;
806 resource.nr_samples = 0;
807 resource.usage = PIPE_USAGE_STAGING;
808 resource.bind = 0;
809 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
810 /* For texture reading, the temporary (detiled) texture is used as
811 * a render target when blitting from a tiled texture. */
812 if (usage & PIPE_TRANSFER_READ) {
813 resource.bind |= PIPE_BIND_RENDER_TARGET;
814 }
815 /* For texture writing, the temporary texture is used as a sampler
816 * when blitting into a tiled texture. */
817 if (usage & PIPE_TRANSFER_WRITE) {
818 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
819 }
820 /* Create the temporary texture. */
821 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
822 if (trans->staging == NULL) {
823 R600_ERR("failed to create temporary texture to hold untiled copy\n");
824 FREE(trans);
825 return NULL;
826 }
827
828 trans->transfer.stride =
829 ((struct r600_texture *)trans->staging)->surface.level[0].pitch_bytes;
830 if (usage & PIPE_TRANSFER_READ) {
831 r600_copy_to_staging_texture(ctx, trans);
832 /* Always referenced in the blit. */
833 r600_flush(ctx, NULL, 0);
834 }
835 } else {
836 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
837 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
838 trans->offset = r600_texture_get_offset(rtex, level, box->z);
839 }
840
841 if (trans->staging) {
842 buf = ((struct r600_resource *)trans->staging)->cs_buf;
843 } else {
844 buf = ((struct r600_resource *)texture)->cs_buf;
845 }
846
847 if (rtex->is_depth || !trans->staging)
848 offset = trans->offset +
849 box->y / util_format_get_blockheight(format) * trans->transfer.stride +
850 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
851
852 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) {
853 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
854 FREE(trans);
855 return NULL;
856 }
857
858 *ptransfer = &trans->transfer;
859 return map + offset;
860 }
861
862 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
863 struct pipe_transfer* transfer)
864 {
865 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
866 struct r600_context *rctx = (struct r600_context*)ctx;
867 struct radeon_winsys_cs_handle *buf;
868 struct pipe_resource *texture = transfer->resource;
869 struct r600_texture *rtex = (struct r600_texture*)texture;
870
871 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
872 return r600_compute_global_transfer_unmap(ctx, transfer);
873 }
874
875 if (rtransfer->staging) {
876 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
877 } else {
878 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
879 }
880 rctx->ws->buffer_unmap(buf);
881
882 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
883 if (rtex->is_depth) {
884 ctx->resource_copy_region(ctx, texture, transfer->level,
885 transfer->box.x, transfer->box.y, transfer->box.z,
886 &rtransfer->staging->b.b, transfer->level,
887 &transfer->box);
888 } else {
889 r600_copy_from_staging_texture(ctx, rtransfer);
890 }
891 }
892
893 if (rtransfer->staging)
894 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
895
896 FREE(transfer);
897 }
898
899 void r600_init_surface_functions(struct r600_context *r600)
900 {
901 r600->context.create_surface = r600_create_surface;
902 r600->context.surface_destroy = r600_surface_destroy;
903 }
904
905 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
906 const unsigned char *swizzle_view)
907 {
908 unsigned i;
909 unsigned char swizzle[4];
910 unsigned result = 0;
911 const uint32_t swizzle_shift[4] = {
912 16, 19, 22, 25,
913 };
914 const uint32_t swizzle_bit[4] = {
915 0, 1, 2, 3,
916 };
917
918 if (swizzle_view) {
919 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
920 } else {
921 memcpy(swizzle, swizzle_format, 4);
922 }
923
924 /* Get swizzle. */
925 for (i = 0; i < 4; i++) {
926 switch (swizzle[i]) {
927 case UTIL_FORMAT_SWIZZLE_Y:
928 result |= swizzle_bit[1] << swizzle_shift[i];
929 break;
930 case UTIL_FORMAT_SWIZZLE_Z:
931 result |= swizzle_bit[2] << swizzle_shift[i];
932 break;
933 case UTIL_FORMAT_SWIZZLE_W:
934 result |= swizzle_bit[3] << swizzle_shift[i];
935 break;
936 case UTIL_FORMAT_SWIZZLE_0:
937 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
938 break;
939 case UTIL_FORMAT_SWIZZLE_1:
940 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
941 break;
942 default: /* UTIL_FORMAT_SWIZZLE_X */
943 result |= swizzle_bit[0] << swizzle_shift[i];
944 }
945 }
946 return result;
947 }
948
949 /* texture format translate */
950 uint32_t r600_translate_texformat(struct pipe_screen *screen,
951 enum pipe_format format,
952 const unsigned char *swizzle_view,
953 uint32_t *word4_p, uint32_t *yuv_format_p)
954 {
955 uint32_t result = 0, word4 = 0, yuv_format = 0;
956 const struct util_format_description *desc;
957 boolean uniform = TRUE;
958 static int r600_enable_s3tc = -1;
959 bool is_srgb_valid = FALSE;
960
961 int i;
962 const uint32_t sign_bit[4] = {
963 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
964 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
965 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
966 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
967 };
968 desc = util_format_description(format);
969
970 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
971
972 /* Colorspace (return non-RGB formats directly). */
973 switch (desc->colorspace) {
974 /* Depth stencil formats */
975 case UTIL_FORMAT_COLORSPACE_ZS:
976 switch (format) {
977 case PIPE_FORMAT_Z16_UNORM:
978 result = FMT_16;
979 goto out_word4;
980 case PIPE_FORMAT_X24S8_UINT:
981 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
982 case PIPE_FORMAT_Z24X8_UNORM:
983 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
984 result = FMT_8_24;
985 goto out_word4;
986 case PIPE_FORMAT_S8X24_UINT:
987 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
988 case PIPE_FORMAT_X8Z24_UNORM:
989 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
990 result = FMT_24_8;
991 goto out_word4;
992 case PIPE_FORMAT_S8_UINT:
993 result = FMT_8;
994 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
995 goto out_word4;
996 case PIPE_FORMAT_Z32_FLOAT:
997 result = FMT_32_FLOAT;
998 goto out_word4;
999 case PIPE_FORMAT_X32_S8X24_UINT:
1000 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1001 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1002 result = FMT_X24_8_32_FLOAT;
1003 goto out_word4;
1004 default:
1005 goto out_unknown;
1006 }
1007
1008 case UTIL_FORMAT_COLORSPACE_YUV:
1009 yuv_format |= (1 << 30);
1010 switch (format) {
1011 case PIPE_FORMAT_UYVY:
1012 case PIPE_FORMAT_YUYV:
1013 default:
1014 break;
1015 }
1016 goto out_unknown; /* XXX */
1017
1018 case UTIL_FORMAT_COLORSPACE_SRGB:
1019 word4 |= S_038010_FORCE_DEGAMMA(1);
1020 break;
1021
1022 default:
1023 break;
1024 }
1025
1026 if (r600_enable_s3tc == -1) {
1027 struct r600_screen *rscreen = (struct r600_screen *)screen;
1028 if (rscreen->info.drm_minor >= 9)
1029 r600_enable_s3tc = 1;
1030 else
1031 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
1032 }
1033
1034 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1035 if (!r600_enable_s3tc)
1036 goto out_unknown;
1037
1038 switch (format) {
1039 case PIPE_FORMAT_RGTC1_SNORM:
1040 case PIPE_FORMAT_LATC1_SNORM:
1041 word4 |= sign_bit[0];
1042 case PIPE_FORMAT_RGTC1_UNORM:
1043 case PIPE_FORMAT_LATC1_UNORM:
1044 result = FMT_BC4;
1045 goto out_word4;
1046 case PIPE_FORMAT_RGTC2_SNORM:
1047 case PIPE_FORMAT_LATC2_SNORM:
1048 word4 |= sign_bit[0] | sign_bit[1];
1049 case PIPE_FORMAT_RGTC2_UNORM:
1050 case PIPE_FORMAT_LATC2_UNORM:
1051 result = FMT_BC5;
1052 goto out_word4;
1053 default:
1054 goto out_unknown;
1055 }
1056 }
1057
1058 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1059
1060 if (!r600_enable_s3tc)
1061 goto out_unknown;
1062
1063 if (!util_format_s3tc_enabled) {
1064 goto out_unknown;
1065 }
1066
1067 switch (format) {
1068 case PIPE_FORMAT_DXT1_RGB:
1069 case PIPE_FORMAT_DXT1_RGBA:
1070 case PIPE_FORMAT_DXT1_SRGB:
1071 case PIPE_FORMAT_DXT1_SRGBA:
1072 result = FMT_BC1;
1073 is_srgb_valid = TRUE;
1074 goto out_word4;
1075 case PIPE_FORMAT_DXT3_RGBA:
1076 case PIPE_FORMAT_DXT3_SRGBA:
1077 result = FMT_BC2;
1078 is_srgb_valid = TRUE;
1079 goto out_word4;
1080 case PIPE_FORMAT_DXT5_RGBA:
1081 case PIPE_FORMAT_DXT5_SRGBA:
1082 result = FMT_BC3;
1083 is_srgb_valid = TRUE;
1084 goto out_word4;
1085 default:
1086 goto out_unknown;
1087 }
1088 }
1089
1090 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1091 switch (format) {
1092 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1093 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1094 result = FMT_GB_GR;
1095 goto out_word4;
1096 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1097 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1098 result = FMT_BG_RG;
1099 goto out_word4;
1100 default:
1101 goto out_unknown;
1102 }
1103 }
1104
1105 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1106 result = FMT_5_9_9_9_SHAREDEXP;
1107 goto out_word4;
1108 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1109 result = FMT_10_11_11_FLOAT;
1110 goto out_word4;
1111 }
1112
1113
1114 for (i = 0; i < desc->nr_channels; i++) {
1115 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1116 word4 |= sign_bit[i];
1117 }
1118 }
1119
1120 /* R8G8Bx_SNORM - XXX CxV8U8 */
1121
1122 /* See whether the components are of the same size. */
1123 for (i = 1; i < desc->nr_channels; i++) {
1124 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1125 }
1126
1127 /* Non-uniform formats. */
1128 if (!uniform) {
1129 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1130 desc->channel[0].pure_integer)
1131 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1132 switch(desc->nr_channels) {
1133 case 3:
1134 if (desc->channel[0].size == 5 &&
1135 desc->channel[1].size == 6 &&
1136 desc->channel[2].size == 5) {
1137 result = FMT_5_6_5;
1138 goto out_word4;
1139 }
1140 goto out_unknown;
1141 case 4:
1142 if (desc->channel[0].size == 5 &&
1143 desc->channel[1].size == 5 &&
1144 desc->channel[2].size == 5 &&
1145 desc->channel[3].size == 1) {
1146 result = FMT_1_5_5_5;
1147 goto out_word4;
1148 }
1149 if (desc->channel[0].size == 10 &&
1150 desc->channel[1].size == 10 &&
1151 desc->channel[2].size == 10 &&
1152 desc->channel[3].size == 2) {
1153 result = FMT_2_10_10_10;
1154 goto out_word4;
1155 }
1156 goto out_unknown;
1157 }
1158 goto out_unknown;
1159 }
1160
1161 /* Find the first non-VOID channel. */
1162 for (i = 0; i < 4; i++) {
1163 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1164 break;
1165 }
1166 }
1167
1168 if (i == 4)
1169 goto out_unknown;
1170
1171 /* uniform formats */
1172 switch (desc->channel[i].type) {
1173 case UTIL_FORMAT_TYPE_UNSIGNED:
1174 case UTIL_FORMAT_TYPE_SIGNED:
1175 #if 0
1176 if (!desc->channel[i].normalized &&
1177 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1178 goto out_unknown;
1179 }
1180 #endif
1181 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1182 desc->channel[i].pure_integer)
1183 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1184
1185 switch (desc->channel[i].size) {
1186 case 4:
1187 switch (desc->nr_channels) {
1188 case 2:
1189 result = FMT_4_4;
1190 goto out_word4;
1191 case 4:
1192 result = FMT_4_4_4_4;
1193 goto out_word4;
1194 }
1195 goto out_unknown;
1196 case 8:
1197 switch (desc->nr_channels) {
1198 case 1:
1199 result = FMT_8;
1200 goto out_word4;
1201 case 2:
1202 result = FMT_8_8;
1203 goto out_word4;
1204 case 4:
1205 result = FMT_8_8_8_8;
1206 is_srgb_valid = TRUE;
1207 goto out_word4;
1208 }
1209 goto out_unknown;
1210 case 16:
1211 switch (desc->nr_channels) {
1212 case 1:
1213 result = FMT_16;
1214 goto out_word4;
1215 case 2:
1216 result = FMT_16_16;
1217 goto out_word4;
1218 case 4:
1219 result = FMT_16_16_16_16;
1220 goto out_word4;
1221 }
1222 goto out_unknown;
1223 case 32:
1224 switch (desc->nr_channels) {
1225 case 1:
1226 result = FMT_32;
1227 goto out_word4;
1228 case 2:
1229 result = FMT_32_32;
1230 goto out_word4;
1231 case 4:
1232 result = FMT_32_32_32_32;
1233 goto out_word4;
1234 }
1235 }
1236 goto out_unknown;
1237
1238 case UTIL_FORMAT_TYPE_FLOAT:
1239 switch (desc->channel[i].size) {
1240 case 16:
1241 switch (desc->nr_channels) {
1242 case 1:
1243 result = FMT_16_FLOAT;
1244 goto out_word4;
1245 case 2:
1246 result = FMT_16_16_FLOAT;
1247 goto out_word4;
1248 case 4:
1249 result = FMT_16_16_16_16_FLOAT;
1250 goto out_word4;
1251 }
1252 goto out_unknown;
1253 case 32:
1254 switch (desc->nr_channels) {
1255 case 1:
1256 result = FMT_32_FLOAT;
1257 goto out_word4;
1258 case 2:
1259 result = FMT_32_32_FLOAT;
1260 goto out_word4;
1261 case 4:
1262 result = FMT_32_32_32_32_FLOAT;
1263 goto out_word4;
1264 }
1265 }
1266 goto out_unknown;
1267 }
1268
1269 out_word4:
1270
1271 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1272 return ~0;
1273 if (word4_p)
1274 *word4_p = word4;
1275 if (yuv_format_p)
1276 *yuv_format_p = yuv_format;
1277 return result;
1278 out_unknown:
1279 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1280 return ~0;
1281 }
1282
1283 static const struct u_resource_vtbl r600_texture_vtbl =
1284 {
1285 r600_texture_get_handle, /* get_handle */
1286 r600_texture_destroy, /* resource_destroy */
1287 r600_texture_transfer_map, /* transfer_map */
1288 NULL, /* transfer_flush_region */
1289 r600_texture_transfer_unmap, /* transfer_unmap */
1290 NULL /* transfer_inline_write */
1291 };