src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_math.h>
  31 #include <util/u_inlines.h>
  32 #include <util/u_memory.h>
  33 #include "state_tracker/drm_driver.h"
  34 #include "pipebuffer/pb_buffer.h"
  35 #include "r600_pipe.h"
  36 #include "r600_resource.h"
  37 #include "r600_state_inlines.h"
  38 #include "r600d.h"
  39 #include "r600_formats.h"
  40
  41 extern struct u_resource_vtbl r600_texture_vtbl;
  42
  43 /* Copy from a full GPU texture to a transfer's staging one. */
  44 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  45 {
  46         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  47         struct pipe_resource *texture = transfer->resource;
  48         struct pipe_subresource subdst;
  49
  50         subdst.face = 0;
  51         subdst.level = 0;
  52         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  53                                 subdst, 0, 0, 0, texture, transfer->sr,
  54                                 transfer->box.x, transfer->box.y, transfer->box.z,
  55                                 transfer->box.width, transfer->box.height);
  56 }
  57
  58
  59 /* Copy from a transfer's staging texture to a full GPU one. */
  60 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  61 {
  62         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  63         struct pipe_resource *texture = transfer->resource;
  64         struct pipe_subresource subsrc;
  65
  66         subsrc.face = 0;
  67         subsrc.level = 0;
  68         ctx->resource_copy_region(ctx, texture, transfer->sr,
  69                                   transfer->box.x, transfer->box.y, transfer->box.z,
  70                                   rtransfer->staging_texture, subsrc,
  71                                   0, 0, 0,
  72                                   transfer->box.width, transfer->box.height);
  73
  74         ctx->flush(ctx, 0, NULL);
  75 }
  76
  77 static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  78                                         unsigned level, unsigned zslice,
  79                                         unsigned face)
  80 {
  81         unsigned offset = rtex->offset[level];
  82
  83         switch (rtex->resource.base.b.target) {
  84         case PIPE_TEXTURE_3D:
  85                 assert(face == 0);
  86                 return offset + zslice * rtex->layer_size[level];
  87         case PIPE_TEXTURE_CUBE:
  88                 assert(zslice == 0);
  89                 return offset + face * rtex->layer_size[level];
  90         default:
  91                 assert(zslice == 0 && face == 0);
  92                 return offset;
  93         }
  94 }
  95
  96 static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
  97                                          enum pipe_format format,
  98                                          unsigned array_mode)
  99 {
 100         struct r600_screen* rscreen = (struct r600_screen *)screen;
 101         unsigned pixsize = util_format_get_blocksize(format);
 102         int p_align;
 103
 104         switch(array_mode) {
 105         case V_038000_ARRAY_1D_TILED_THIN1:
 106                 p_align = MAX2(8,
 107                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
 108                 break;
 109         case V_038000_ARRAY_2D_TILED_THIN1:
 110                 p_align = MAX2(rscreen->tiling_info->num_banks,
 111                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 112                                 rscreen->tiling_info->num_banks));
 113                 break;
 114         case 0:
 115         default:
 116                 p_align = 64;
 117                 break;
 118         }
 119         return p_align;
 120 }
 121
 122 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 123                                           unsigned array_mode)
 124 {
 125         struct r600_screen* rscreen = (struct r600_screen *)screen;
 126         int h_align;
 127
 128         switch (array_mode) {
 129         case V_038000_ARRAY_2D_TILED_THIN1:
 130                 h_align = rscreen->tiling_info->num_channels * 8;
 131                 break;
 132         case V_038000_ARRAY_1D_TILED_THIN1:
 133                 h_align = 8;
 134                 break;
 135         default:
 136                 h_align = 1;
 137                 break;
 138         }
 139         return h_align;
 140 }
 141
 142 static unsigned mip_minify(unsigned size, unsigned level)
 143 {
 144         unsigned val;
 145         val = u_minify(size, level);
 146         if (level > 0)
 147                 val = util_next_power_of_two(val);
 148         return val;
 149 }
 150
 151 static unsigned r600_texture_get_stride(struct pipe_screen *screen,
 152                                         struct r600_resource_texture *rtex,
 153                                         unsigned level)
 154 {
 155         struct pipe_resource *ptex = &rtex->resource.base.b;
 156         struct radeon *radeon = (struct radeon *)screen->winsys;
 157         enum chip_class chipc = r600_get_family_class(radeon);
 158         unsigned width, stride, tile_width;
 159
 160         if (rtex->pitch_override)
 161                 return rtex->pitch_override;
 162
 163         width = mip_minify(ptex->width0, level);
 164         if (util_format_is_plain(ptex->format)) {
 165                 tile_width = r600_get_pixel_alignment(screen, ptex->format,
 166                                                       rtex->array_mode[level]);
 167                 width = align(width, tile_width);
 168         }
 169         stride = util_format_get_stride(ptex->format, width);
 170         if (chipc == EVERGREEN)
 171                 stride = align(stride, 512);
 172         return stride;
 173 }
 174
 175 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 176                                           struct r600_resource_texture *rtex,
 177                                           unsigned level)
 178 {
 179         struct pipe_resource *ptex = &rtex->resource.base.b;
 180         unsigned height, tile_height;
 181
 182         height = mip_minify(ptex->height0, level);
 183         if (util_format_is_plain(ptex->format)) {
 184                 tile_height = r600_get_height_alignment(screen,
 185                                                         rtex->array_mode[level]);
 186                 height = align(height, tile_height);
 187         }
 188         return util_format_get_nblocksy(ptex->format, height);
 189 }
 190
 191 /* Get a width in pixels from a stride in bytes. */
 192 static unsigned pitch_to_width(enum pipe_format format,
 193                                 unsigned pitch_in_bytes)
 194 {
 195     return (pitch_in_bytes / util_format_get_blocksize(format)) *
 196             util_format_get_blockwidth(format);
 197 }
 198
 199 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 200                                         struct r600_resource_texture *rtex,
 201                                         unsigned level, unsigned array_mode)
 202 {
 203         struct pipe_resource *ptex = &rtex->resource.base.b;
 204
 205         switch (array_mode) {
 206         case V_0280A0_ARRAY_LINEAR_GENERAL:
 207         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 208         case V_0280A0_ARRAY_1D_TILED_THIN1:
 209         default:
 210                 rtex->array_mode[level] = array_mode;
 211                 break;
 212         case V_0280A0_ARRAY_2D_TILED_THIN1:
 213         {
 214                 unsigned w, h, tile_height, tile_width;
 215
 216                 tile_height = r600_get_height_alignment(screen, array_mode);
 217                 tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode);
 218
 219                 w = mip_minify(ptex->width0, level);
 220                 h = mip_minify(ptex->height0, level);
 221                 if (w < tile_width || h < tile_height)
 222                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 223                 else
 224                         rtex->array_mode[level] = array_mode;
 225         }
 226         break;
 227         }
 228 }
 229
 230 static void r600_setup_miptree(struct pipe_screen *screen,
 231                                struct r600_resource_texture *rtex,
 232                                unsigned array_mode)
 233 {
 234         struct pipe_resource *ptex = &rtex->resource.base.b;
 235         struct radeon *radeon = (struct radeon *)screen->winsys;
 236         enum chip_class chipc = r600_get_family_class(radeon);
 237         unsigned pitch, size, layer_size, i, offset;
 238         unsigned nblocksy;
 239
 240         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 241                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 242
 243                 pitch = r600_texture_get_stride(screen, rtex, i);
 244                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 245
 246                 layer_size = pitch * nblocksy;
 247
 248                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 249                         if (chipc >= R700)
 250                                 size = layer_size * 8;
 251                         else
 252                                 size = layer_size * 6;
 253                 }
 254                 else
 255                         size = layer_size * u_minify(ptex->depth0, i);
 256                 rtex->offset[i] = offset;
 257                 rtex->layer_size[i] = layer_size;
 258                 rtex->pitch_in_bytes[i] = pitch;
 259                 rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
 260                 offset += size;
 261         }
 262         rtex->size = offset;
 263 }
 264
 265 static struct r600_resource_texture *
 266 r600_texture_create_object(struct pipe_screen *screen,
 267                            const struct pipe_resource *base,
 268                            unsigned array_mode,
 269                            unsigned pitch_in_bytes_override,
 270                            unsigned max_buffer_size,
 271                            struct r600_bo *bo)
 272 {
 273         struct r600_resource_texture *rtex;
 274         struct r600_resource *resource;
 275         struct radeon *radeon = (struct radeon *)screen->winsys;
 276
 277         rtex = CALLOC_STRUCT(r600_resource_texture);
 278         if (rtex == NULL)
 279                 return NULL;
 280
 281         resource = &rtex->resource;
 282         resource->base.b = *base;
 283         resource->base.vtbl = &r600_texture_vtbl;
 284         pipe_reference_init(&resource->base.b.reference, 1);
 285         resource->base.b.screen = screen;
 286         resource->bo = bo;
 287         rtex->pitch_override = pitch_in_bytes_override;
 288
 289         if (array_mode)
 290                 rtex->tiled = 1;
 291         r600_setup_miptree(screen, rtex, array_mode);
 292
 293         resource->size = rtex->size;
 294
 295         if (!resource->bo) {
 296                 resource->bo = r600_bo(radeon, rtex->size, 4096, base->bind, base->usage);
 297                 if (!resource->bo) {
 298                         FREE(rtex);
 299                         return NULL;
 300                 }
 301         }
 302         return rtex;
 303 }
 304
 305 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 306                                                 const struct pipe_resource *templ)
 307 {
 308         unsigned array_mode = 0;
 309         static int force_tiling = -1;
 310
 311         /* Would like some magic "get_bool_option_once" routine.
 312          */
 313         if (force_tiling == -1)
 314                 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
 315
 316         if (force_tiling) {
 317                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 318                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 319                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 320                 }
 321         }
 322
 323         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 324                                                                   0, 0, NULL);
 325
 326 }
 327
 328 static void r600_texture_destroy(struct pipe_screen *screen,
 329                                  struct pipe_resource *ptex)
 330 {
 331         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 332         struct r600_resource *resource = &rtex->resource;
 333         struct radeon *radeon = (struct radeon *)screen->winsys;
 334
 335         if (rtex->flushed_depth_texture)
 336                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 337
 338         if (resource->bo) {
 339                 r600_bo_reference(radeon, &resource->bo, NULL);
 340         }
 341         FREE(rtex);
 342 }
 343
 344 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 345                                        struct pipe_resource *ptex,
 346                                        struct winsys_handle *whandle)
 347 {
 348         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 349         struct r600_resource *resource = &rtex->resource;
 350         struct radeon *radeon = (struct radeon *)screen->winsys;
 351
 352         return r600_bo_get_winsys_handle(radeon, resource->bo,
 353                         rtex->pitch_in_bytes[0], whandle);
 354 }
 355
 356 static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen,
 357                                                 struct pipe_resource *texture,
 358                                                 unsigned face, unsigned level,
 359                                                 unsigned zslice, unsigned flags)
 360 {
 361         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 362         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 363         unsigned offset, tile_height;
 364
 365         if (surface == NULL)
 366                 return NULL;
 367         offset = r600_texture_get_offset(rtex, level, zslice, face);
 368         pipe_reference_init(&surface->base.reference, 1);
 369         pipe_resource_reference(&surface->base.texture, texture);
 370         surface->base.format = texture->format;
 371         surface->base.width = mip_minify(texture->width0, level);
 372         surface->base.height = mip_minify(texture->height0, level);
 373         surface->base.offset = offset;
 374         surface->base.usage = flags;
 375         surface->base.zslice = zslice;
 376         surface->base.texture = texture;
 377         surface->base.face = face;
 378         surface->base.level = level;
 379
 380         tile_height = r600_get_height_alignment(screen, rtex->array_mode[level]);
 381         surface->aligned_height = align(surface->base.height, tile_height);
 382         return &surface->base;
 383 }
 384
 385 static void r600_tex_surface_destroy(struct pipe_surface *surface)
 386 {
 387         pipe_resource_reference(&surface->texture, NULL);
 388         FREE(surface);
 389 }
 390
 391
 392 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 393                                                const struct pipe_resource *templ,
 394                                                struct winsys_handle *whandle)
 395 {
 396         struct radeon *rw = (struct radeon*)screen->winsys;
 397         struct r600_bo *bo = NULL;
 398         unsigned array_mode = 0;
 399
 400         /* Support only 2D textures without mipmaps */
 401         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 402               templ->depth0 != 1 || templ->last_level != 0)
 403                 return NULL;
 404
 405         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 406         if (bo == NULL) {
 407                 return NULL;
 408         }
 409
 410         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 411                                                                   whandle->stride,
 412                                                                   0,
 413                                                                   bo);
 414 }
 415
 416 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 417                                                 struct pipe_resource *texture,
 418                                                 unsigned face, unsigned level)
 419 {
 420         /* FIXME */
 421         return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 422 }
 423
 424 int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct r600_resource_texture *texture);
 425
 426 int r600_texture_depth_flush(struct pipe_context *ctx,
 427                              struct pipe_resource *texture)
 428 {
 429         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 430         struct pipe_resource resource;
 431
 432         if (rtex->flushed_depth_texture)
 433                 goto out;
 434
 435         resource.target = PIPE_TEXTURE_2D;
 436         resource.format = texture->format;
 437         resource.width0 = texture->width0;
 438         resource.height0 = texture->height0;
 439         resource.depth0 = 1;
 440         resource.last_level = 0;
 441         resource.nr_samples = 0;
 442         resource.usage = PIPE_USAGE_DYNAMIC;
 443         resource.bind = 0;
 444         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 445
 446         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 447
 448         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 449         if (rtex->flushed_depth_texture == NULL) {
 450                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 451                 return -ENOMEM;
 452         }
 453
 454 out:
 455         /* XXX: only do this if the depth texture has actually changed:
 456          */
 457         r600_blit_uncompress_depth_ptr(ctx, rtex);
 458         return 0;
 459 }
 460
 461 /* Needs adjustment for pixelformat:
 462  */
 463 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 464 {
 465         return box->width * box->depth * box->height;
 466 };
 467
 468
 469 /* Figure out whether u_blitter will fallback to a transfer operation.
 470  * If so, don't use a staging resource.
 471  */
 472 static boolean permit_hardware_blit(struct pipe_screen *screen,
 473                                     struct pipe_resource *res)
 474 {
 475         unsigned bind;
 476
 477         if (util_format_is_depth_or_stencil(res->format))
 478                 bind = PIPE_BIND_DEPTH_STENCIL;
 479         else
 480                 bind = PIPE_BIND_RENDER_TARGET;
 481
 482         if (!screen->is_format_supported(screen,
 483                                          res->format,
 484                                          res->target,
 485                                          res->nr_samples,
 486                                          bind, 0))
 487                 return FALSE;
 488
 489         if (!screen->is_format_supported(screen,
 490                                          res->format,
 491                                          res->target,
 492                                          res->nr_samples,
 493                                          PIPE_BIND_SAMPLER_VIEW, 0))
 494                 return FALSE;
 495
 496         return TRUE;
 497 }
 498
 499 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 500                                                 struct pipe_resource *texture,
 501                                                 struct pipe_subresource sr,
 502                                                 unsigned usage,
 503                                                 const struct pipe_box *box)
 504 {
 505         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 506         struct pipe_resource resource;
 507         struct r600_transfer *trans;
 508         int r;
 509         boolean use_staging_texture = FALSE;
 510
 511         /* We cannot map a tiled texture directly because the data is
 512          * in a different order, therefore we do detiling using a blit.
 513          *
 514          * Also, use a temporary in GTT memory for read transfers, as
 515          * the CPU is much happier reading out of cached system memory
 516          * than uncached VRAM.
 517          */
 518         if (rtex->tiled)
 519                 use_staging_texture = TRUE;
 520
 521         if ((usage & PIPE_TRANSFER_READ) &&
 522             u_box_volume(box) > 1024)
 523                 use_staging_texture = TRUE;
 524
 525         /* XXX: Use a staging texture for uploads if the underlying BO
 526          * is busy.  No interface for checking that currently? so do
 527          * it eagerly whenever the transfer doesn't require a readback
 528          * and might block.
 529          */
 530         if ((usage & PIPE_TRANSFER_WRITE) &&
 531             !(usage & (PIPE_TRANSFER_READ |
 532                        PIPE_TRANSFER_DONTBLOCK |
 533                        PIPE_TRANSFER_UNSYNCHRONIZED)))
 534                 use_staging_texture = TRUE;
 535
 536         if (!permit_hardware_blit(ctx->screen, texture) ||
 537             (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 538                 use_staging_texture = FALSE;
 539
 540         trans = CALLOC_STRUCT(r600_transfer);
 541         if (trans == NULL)
 542                 return NULL;
 543         pipe_resource_reference(&trans->transfer.resource, texture);
 544         trans->transfer.sr = sr;
 545         trans->transfer.usage = usage;
 546         trans->transfer.box = *box;
 547         if (rtex->depth) {
 548                 /* XXX: only readback the rectangle which is being mapped?
 549                  */
 550                 /* XXX: when discard is true, no need to read back from depth texture
 551                  */
 552                 r = r600_texture_depth_flush(ctx, texture);
 553                 if (r < 0) {
 554                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 555                         pipe_resource_reference(&trans->transfer.resource, NULL);
 556                         FREE(trans);
 557                         return NULL;
 558                 }
 559         } else if (use_staging_texture) {
 560                 resource.target = PIPE_TEXTURE_2D;
 561                 resource.format = texture->format;
 562                 resource.width0 = box->width;
 563                 resource.height0 = box->height;
 564                 resource.depth0 = 1;
 565                 resource.last_level = 0;
 566                 resource.nr_samples = 0;
 567                 resource.usage = PIPE_USAGE_STAGING;
 568                 resource.bind = 0;
 569                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 570                 /* For texture reading, the temporary (detiled) texture is used as
 571                  * a render target when blitting from a tiled texture. */
 572                 if (usage & PIPE_TRANSFER_READ) {
 573                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 574                 }
 575                 /* For texture writing, the temporary texture is used as a sampler
 576                  * when blitting into a tiled texture. */
 577                 if (usage & PIPE_TRANSFER_WRITE) {
 578                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 579                 }
 580                 /* Create the temporary texture. */
 581                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 582                 if (trans->staging_texture == NULL) {
 583                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 584                         pipe_resource_reference(&trans->transfer.resource, NULL);
 585                         FREE(trans);
 586                         return NULL;
 587                 }
 588
 589                 trans->transfer.stride =
 590                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 591                 if (usage & PIPE_TRANSFER_READ) {
 592                         r600_copy_to_staging_texture(ctx, trans);
 593                         /* Always referenced in the blit. */
 594                         ctx->flush(ctx, 0, NULL);
 595                 }
 596                 return &trans->transfer;
 597         }
 598         trans->transfer.stride = rtex->pitch_in_bytes[sr.level];
 599         trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
 600         return &trans->transfer;
 601 }
 602
 603 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 604                                    struct pipe_transfer *transfer)
 605 {
 606         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 607         struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 608
 609         if (rtransfer->staging_texture) {
 610                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 611                         r600_copy_from_staging_texture(ctx, rtransfer);
 612                 }
 613                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 614         }
 615         if (rtex->flushed_depth_texture) {
 616                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 617         }
 618         pipe_resource_reference(&transfer->resource, NULL);
 619         FREE(transfer);
 620 }
 621
 622 void* r600_texture_transfer_map(struct pipe_context *ctx,
 623                                 struct pipe_transfer* transfer)
 624 {
 625         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 626         struct r600_bo *bo;
 627         enum pipe_format format = transfer->resource->format;
 628         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 629         unsigned offset = 0;
 630         unsigned usage = 0;
 631         char *map;
 632
 633         if (rtransfer->staging_texture) {
 634                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 635         } else {
 636                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 637
 638                 if (rtex->flushed_depth_texture)
 639                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 640                 else
 641                         bo = ((struct r600_resource *)transfer->resource)->bo;
 642
 643                 offset = rtransfer->offset +
 644                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 645                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 646         }
 647
 648         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 649                 usage |= PB_USAGE_CPU_WRITE;
 650
 651                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 652                 }
 653
 654                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 655                 }
 656         }
 657
 658         if (transfer->usage & PIPE_TRANSFER_READ) {
 659                 usage |= PB_USAGE_CPU_READ;
 660         }
 661
 662         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 663                 usage |= PB_USAGE_DONTBLOCK;
 664         }
 665
 666         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 667                 usage |= PB_USAGE_UNSYNCHRONIZED;
 668         }
 669
 670         map = r600_bo_map(radeon, bo, usage, ctx);
 671         if (!map) {
 672                 return NULL;
 673         }
 674
 675         return map + offset;
 676 }
 677
 678 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 679                                  struct pipe_transfer* transfer)
 680 {
 681         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 682         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 683         struct r600_bo *bo;
 684
 685         if (rtransfer->staging_texture) {
 686                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 687         } else {
 688                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 689
 690                 if (rtex->flushed_depth_texture) {
 691                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 692                 } else {
 693                         bo = ((struct r600_resource *)transfer->resource)->bo;
 694                 }
 695         }
 696         r600_bo_unmap(radeon, bo);
 697 }
 698
 699 struct u_resource_vtbl r600_texture_vtbl =
 700 {
 701         r600_texture_get_handle,        /* get_handle */
 702         r600_texture_destroy,           /* resource_destroy */
 703         r600_texture_is_referenced,     /* is_resource_referenced */
 704         r600_texture_get_transfer,      /* get_transfer */
 705         r600_texture_transfer_destroy,  /* transfer_destroy */
 706         r600_texture_transfer_map,      /* transfer_map */
 707         u_default_transfer_flush_region,/* transfer_flush_region */
 708         r600_texture_transfer_unmap,    /* transfer_unmap */
 709         u_default_transfer_inline_write /* transfer_inline_write */
 710 };
 711
 712 void r600_init_screen_texture_functions(struct pipe_screen *screen)
 713 {
 714         screen->get_tex_surface = r600_get_tex_surface;
 715         screen->tex_surface_destroy = r600_tex_surface_destroy;
 716 }
 717
 718 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 719                 const unsigned char *swizzle_view)
 720 {
 721         unsigned i;
 722         unsigned char swizzle[4];
 723         unsigned result = 0;
 724         const uint32_t swizzle_shift[4] = {
 725                 16, 19, 22, 25,
 726         };
 727         const uint32_t swizzle_bit[4] = {
 728                 0, 1, 2, 3,
 729         };
 730
 731         if (swizzle_view) {
 732                 /* Combine two sets of swizzles. */
 733                 for (i = 0; i < 4; i++) {
 734                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 735                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 736                 }
 737         } else {
 738                 memcpy(swizzle, swizzle_format, 4);
 739         }
 740
 741         /* Get swizzle. */
 742         for (i = 0; i < 4; i++) {
 743                 switch (swizzle[i]) {
 744                 case UTIL_FORMAT_SWIZZLE_Y:
 745                         result |= swizzle_bit[1] << swizzle_shift[i];
 746                         break;
 747                 case UTIL_FORMAT_SWIZZLE_Z:
 748                         result |= swizzle_bit[2] << swizzle_shift[i];
 749                         break;
 750                 case UTIL_FORMAT_SWIZZLE_W:
 751                         result |= swizzle_bit[3] << swizzle_shift[i];
 752                         break;
 753                 case UTIL_FORMAT_SWIZZLE_0:
 754                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 755                         break;
 756                 case UTIL_FORMAT_SWIZZLE_1:
 757                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 758                         break;
 759                 default: /* UTIL_FORMAT_SWIZZLE_X */
 760                         result |= swizzle_bit[0] << swizzle_shift[i];
 761                 }
 762         }
 763         return result;
 764 }
 765
 766 /* texture format translate */
 767 uint32_t r600_translate_texformat(enum pipe_format format,
 768                                   const unsigned char *swizzle_view,
 769                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 770 {
 771         uint32_t result = 0, word4 = 0, yuv_format = 0;
 772         const struct util_format_description *desc;
 773         boolean uniform = TRUE;
 774         int i;
 775         const uint32_t sign_bit[4] = {
 776                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 777                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 778                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 779                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 780         };
 781         desc = util_format_description(format);
 782
 783         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 784
 785         /* Colorspace (return non-RGB formats directly). */
 786         switch (desc->colorspace) {
 787                 /* Depth stencil formats */
 788         case UTIL_FORMAT_COLORSPACE_ZS:
 789                 switch (format) {
 790                 case PIPE_FORMAT_Z16_UNORM:
 791                         result = FMT_16;
 792                         goto out_word4;
 793                 case PIPE_FORMAT_X24S8_USCALED:
 794                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 795                 case PIPE_FORMAT_Z24X8_UNORM:
 796                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 797                         result = FMT_8_24;
 798                         goto out_word4;
 799                 case PIPE_FORMAT_S8X24_USCALED:
 800                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 801                 case PIPE_FORMAT_X8Z24_UNORM:
 802                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 803                         result = FMT_24_8;
 804                         goto out_word4;
 805                 case PIPE_FORMAT_S8_USCALED:
 806                         result = FMT_8;
 807                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 808                         goto out_word4;
 809                 default:
 810                         goto out_unknown;
 811                 }
 812
 813         case UTIL_FORMAT_COLORSPACE_YUV:
 814                 yuv_format |= (1 << 30);
 815                 switch (format) {
 816                 case PIPE_FORMAT_UYVY:
 817                 case PIPE_FORMAT_YUYV:
 818                 default:
 819                         break;
 820                 }
 821                 goto out_unknown; /* TODO */
 822
 823         case UTIL_FORMAT_COLORSPACE_SRGB:
 824                 word4 |= S_038010_FORCE_DEGAMMA(1);
 825                 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
 826                         goto out_unknown; /* fails for some reason - TODO */
 827                 break;
 828
 829         default:
 830                 break;
 831         }
 832
 833         /* S3TC formats. TODO */
 834         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 835                 static int r600_enable_s3tc = -1;
 836
 837                 if (r600_enable_s3tc == -1)
 838                         r600_enable_s3tc =
 839                                 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 840
 841                 if (!r600_enable_s3tc)
 842                         goto out_unknown;
 843
 844                 switch (format) {
 845                 case PIPE_FORMAT_DXT1_RGB:
 846                 case PIPE_FORMAT_DXT1_RGBA:
 847                         result = FMT_BC1;
 848                         goto out_word4;
 849                 case PIPE_FORMAT_DXT3_RGBA:
 850                         result = FMT_BC2;
 851                         goto out_word4;
 852                 case PIPE_FORMAT_DXT5_RGBA:
 853                         result = FMT_BC3;
 854                         goto out_word4;
 855                 default:
 856                         goto out_unknown;
 857                 }
 858         }
 859
 860
 861         for (i = 0; i < desc->nr_channels; i++) {
 862                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 863                         word4 |= sign_bit[i];
 864                 }
 865         }
 866
 867         /* R8G8Bx_SNORM - TODO CxV8U8 */
 868
 869         /* RGTC - TODO */
 870
 871         /* See whether the components are of the same size. */
 872         for (i = 1; i < desc->nr_channels; i++) {
 873                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 874         }
 875
 876         /* Non-uniform formats. */
 877         if (!uniform) {
 878                 switch(desc->nr_channels) {
 879                 case 3:
 880                         if (desc->channel[0].size == 5 &&
 881                             desc->channel[1].size == 6 &&
 882                             desc->channel[2].size == 5) {
 883                                 result = FMT_5_6_5;
 884                                 goto out_word4;
 885                         }
 886                         goto out_unknown;
 887                 case 4:
 888                         if (desc->channel[0].size == 5 &&
 889                             desc->channel[1].size == 5 &&
 890                             desc->channel[2].size == 5 &&
 891                             desc->channel[3].size == 1) {
 892                                 result = FMT_1_5_5_5;
 893                                 goto out_word4;
 894                         }
 895                         if (desc->channel[0].size == 10 &&
 896                             desc->channel[1].size == 10 &&
 897                             desc->channel[2].size == 10 &&
 898                             desc->channel[3].size == 2) {
 899                                 result = FMT_10_10_10_2;
 900                                 goto out_word4;
 901                         }
 902                         goto out_unknown;
 903                 }
 904                 goto out_unknown;
 905         }
 906
 907         /* Find the first non-VOID channel. */
 908         for (i = 0; i < 4; i++) {
 909                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 910                         break;
 911                 }
 912         }
 913
 914         if (i == 4)
 915                 goto out_unknown;
 916
 917         /* uniform formats */
 918         switch (desc->channel[i].type) {
 919         case UTIL_FORMAT_TYPE_UNSIGNED:
 920         case UTIL_FORMAT_TYPE_SIGNED:
 921                 if (!desc->channel[i].normalized &&
 922                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 923                         goto out_unknown;
 924                 }
 925
 926                 switch (desc->channel[i].size) {
 927                 case 4:
 928                         switch (desc->nr_channels) {
 929                         case 2:
 930                                 result = FMT_4_4;
 931                                 goto out_word4;
 932                         case 4:
 933                                 result = FMT_4_4_4_4;
 934                                 goto out_word4;
 935                         }
 936                         goto out_unknown;
 937                 case 8:
 938                         switch (desc->nr_channels) {
 939                         case 1:
 940                                 result = FMT_8;
 941                                 goto out_word4;
 942                         case 2:
 943                                 result = FMT_8_8;
 944                                 goto out_word4;
 945                         case 4:
 946                                 result = FMT_8_8_8_8;
 947                                 goto out_word4;
 948                         }
 949                         goto out_unknown;
 950                 case 16:
 951                         switch (desc->nr_channels) {
 952                         case 1:
 953                                 result = FMT_16;
 954                                 goto out_word4;
 955                         case 2:
 956                                 result = FMT_16_16;
 957                                 goto out_word4;
 958                         case 4:
 959                                 result = FMT_16_16_16_16;
 960                                 goto out_word4;
 961                         }
 962                 }
 963                 goto out_unknown;
 964
 965         case UTIL_FORMAT_TYPE_FLOAT:
 966                 switch (desc->channel[i].size) {
 967                 case 16:
 968                         switch (desc->nr_channels) {
 969                         case 1:
 970                                 result = FMT_16_FLOAT;
 971                                 goto out_word4;
 972                         case 2:
 973                                 result = FMT_16_16_FLOAT;
 974                                 goto out_word4;
 975                         case 4:
 976                                 result = FMT_16_16_16_16_FLOAT;
 977                                 goto out_word4;
 978                         }
 979                         goto out_unknown;
 980                 case 32:
 981                         switch (desc->nr_channels) {
 982                         case 1:
 983                                 result = FMT_32_FLOAT;
 984                                 goto out_word4;
 985                         case 2:
 986                                 result = FMT_32_32_FLOAT;
 987                                 goto out_word4;
 988                         case 4:
 989                                 result = FMT_32_32_32_32_FLOAT;
 990                                 goto out_word4;
 991                         }
 992                 }
 993
 994         }
 995 out_word4:
 996         if (word4_p)
 997                 *word4_p = word4;
 998         if (yuv_format_p)
 999                 *yuv_format_p = yuv_format;
1000         return result;
1001 out_unknown:
1002 //      R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1003         return ~0;
1004 }