2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_format_s3tc.h>
31 #include <util/u_math.h>
32 #include <util/u_inlines.h>
33 #include <util/u_memory.h>
34 #include "state_tracker/drm_driver.h"
35 #include "pipebuffer/pb_buffer.h"
36 #include "r600_pipe.h"
37 #include "r600_resource.h"
38 #include "r600_state_inlines.h"
40 #include "r600_formats.h"
42 /* Copy from a full GPU texture to a transfer's staging one. */
43 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
45 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
46 struct pipe_resource
*texture
= transfer
->resource
;
48 ctx
->resource_copy_region(ctx
, rtransfer
->staging_texture
,
49 0, 0, 0, 0, texture
, transfer
->level
,
54 /* Copy from a transfer's staging texture to a full GPU one. */
55 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
57 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
58 struct pipe_resource
*texture
= transfer
->resource
;
61 sbox
.x
= sbox
.y
= sbox
.z
= 0;
62 sbox
.width
= transfer
->box
.width
;
63 sbox
.height
= transfer
->box
.height
;
64 /* XXX that might be wrong */
66 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
67 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
68 rtransfer
->staging_texture
,
71 ctx
->flush(ctx
, NULL
);
74 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
75 unsigned level
, unsigned layer
)
77 unsigned offset
= rtex
->offset
[level
];
79 switch (rtex
->resource
.b
.b
.b
.target
) {
81 case PIPE_TEXTURE_CUBE
:
83 return offset
+ layer
* rtex
->layer_size
[level
];
87 static unsigned r600_get_block_alignment(struct pipe_screen
*screen
,
88 enum pipe_format format
,
91 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
92 unsigned pixsize
= util_format_get_blocksize(format
);
96 case V_038000_ARRAY_1D_TILED_THIN1
:
98 ((rscreen
->tiling_info
->group_bytes
/ 8 / pixsize
)));
100 case V_038000_ARRAY_2D_TILED_THIN1
:
101 p_align
= MAX2(rscreen
->tiling_info
->num_banks
,
102 (((rscreen
->tiling_info
->group_bytes
/ 8 / pixsize
)) *
103 rscreen
->tiling_info
->num_banks
)) * 8;
105 case V_038000_ARRAY_LINEAR_ALIGNED
:
106 p_align
= MAX2(64, rscreen
->tiling_info
->group_bytes
/ pixsize
);
108 case V_038000_ARRAY_LINEAR_GENERAL
:
110 p_align
= rscreen
->tiling_info
->group_bytes
/ pixsize
;
116 static unsigned r600_get_height_alignment(struct pipe_screen
*screen
,
119 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
122 switch (array_mode
) {
123 case V_038000_ARRAY_2D_TILED_THIN1
:
124 h_align
= rscreen
->tiling_info
->num_channels
* 8;
126 case V_038000_ARRAY_1D_TILED_THIN1
:
127 case V_038000_ARRAY_LINEAR_ALIGNED
:
130 case V_038000_ARRAY_LINEAR_GENERAL
:
138 static unsigned r600_get_base_alignment(struct pipe_screen
*screen
,
139 enum pipe_format format
,
142 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
143 unsigned pixsize
= util_format_get_blocksize(format
);
144 int p_align
= r600_get_block_alignment(screen
, format
, array_mode
);
145 int h_align
= r600_get_height_alignment(screen
, array_mode
);
148 switch (array_mode
) {
149 case V_038000_ARRAY_2D_TILED_THIN1
:
150 b_align
= MAX2(rscreen
->tiling_info
->num_banks
* rscreen
->tiling_info
->num_channels
* 8 * 8 * pixsize
,
151 p_align
* pixsize
* h_align
);
153 case V_038000_ARRAY_1D_TILED_THIN1
:
154 case V_038000_ARRAY_LINEAR_ALIGNED
:
155 case V_038000_ARRAY_LINEAR_GENERAL
:
157 b_align
= rscreen
->tiling_info
->group_bytes
;
163 static unsigned mip_minify(unsigned size
, unsigned level
)
166 val
= u_minify(size
, level
);
168 val
= util_next_power_of_two(val
);
172 static unsigned r600_texture_get_nblocksx(struct pipe_screen
*screen
,
173 struct r600_resource_texture
*rtex
,
176 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
177 unsigned nblocksx
, block_align
, width
;
178 unsigned blocksize
= util_format_get_blocksize(ptex
->format
);
180 if (rtex
->pitch_override
)
181 return rtex
->pitch_override
/ blocksize
;
183 width
= mip_minify(ptex
->width0
, level
);
184 nblocksx
= util_format_get_nblocksx(ptex
->format
, width
);
186 block_align
= r600_get_block_alignment(screen
, ptex
->format
,
187 rtex
->array_mode
[level
]);
188 nblocksx
= align(nblocksx
, block_align
);
192 static unsigned r600_texture_get_nblocksy(struct pipe_screen
*screen
,
193 struct r600_resource_texture
*rtex
,
196 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
197 unsigned height
, tile_height
;
199 height
= mip_minify(ptex
->height0
, level
);
200 height
= util_format_get_nblocksy(ptex
->format
, height
);
201 tile_height
= r600_get_height_alignment(screen
,
202 rtex
->array_mode
[level
]);
203 height
= align(height
, tile_height
);
207 static void r600_texture_set_array_mode(struct pipe_screen
*screen
,
208 struct r600_resource_texture
*rtex
,
209 unsigned level
, unsigned array_mode
)
211 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
213 switch (array_mode
) {
214 case V_0280A0_ARRAY_LINEAR_GENERAL
:
215 case V_0280A0_ARRAY_LINEAR_ALIGNED
:
216 case V_0280A0_ARRAY_1D_TILED_THIN1
:
218 rtex
->array_mode
[level
] = array_mode
;
220 case V_0280A0_ARRAY_2D_TILED_THIN1
:
222 unsigned w
, h
, tile_height
, tile_width
;
224 tile_height
= r600_get_height_alignment(screen
, array_mode
);
225 tile_width
= r600_get_block_alignment(screen
, ptex
->format
, array_mode
);
227 w
= mip_minify(ptex
->width0
, level
);
228 h
= mip_minify(ptex
->height0
, level
);
229 if (w
<= tile_width
|| h
<= tile_height
)
230 rtex
->array_mode
[level
] = V_0280A0_ARRAY_1D_TILED_THIN1
;
232 rtex
->array_mode
[level
] = array_mode
;
238 static void r600_setup_miptree(struct pipe_screen
*screen
,
239 struct r600_resource_texture
*rtex
,
242 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
243 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
244 enum chip_class chipc
= r600_get_family_class(radeon
);
245 unsigned size
, layer_size
, i
, offset
;
246 unsigned nblocksx
, nblocksy
;
248 for (i
= 0, offset
= 0; i
<= ptex
->last_level
; i
++) {
249 unsigned blocksize
= util_format_get_blocksize(ptex
->format
);
251 r600_texture_set_array_mode(screen
, rtex
, i
, array_mode
);
253 nblocksx
= r600_texture_get_nblocksx(screen
, rtex
, i
);
254 nblocksy
= r600_texture_get_nblocksy(screen
, rtex
, i
);
256 layer_size
= nblocksx
* nblocksy
* blocksize
;
257 if (ptex
->target
== PIPE_TEXTURE_CUBE
) {
259 size
= layer_size
* 8;
261 size
= layer_size
* 6;
263 else if (ptex
->target
== PIPE_TEXTURE_3D
)
264 size
= layer_size
* u_minify(ptex
->depth0
, i
);
266 size
= layer_size
* ptex
->array_size
;
268 /* align base image and start of miptree */
269 if ((i
== 0) || (i
== 1))
270 offset
= align(offset
, r600_get_base_alignment(screen
, ptex
->format
, array_mode
));
271 rtex
->offset
[i
] = offset
;
272 rtex
->layer_size
[i
] = layer_size
;
273 rtex
->pitch_in_blocks
[i
] = nblocksx
; /* CB talks in elements */
274 rtex
->pitch_in_bytes
[i
] = nblocksx
* blocksize
;
281 /* Figure out whether u_blitter will fallback to a transfer operation.
282 * If so, don't use a staging resource.
284 static boolean
permit_hardware_blit(struct pipe_screen
*screen
,
285 const struct pipe_resource
*res
)
289 if (util_format_is_depth_or_stencil(res
->format
))
290 bind
= PIPE_BIND_DEPTH_STENCIL
;
292 bind
= PIPE_BIND_RENDER_TARGET
;
294 /* hackaround for S3TC */
295 if (util_format_is_compressed(res
->format
))
298 if (!screen
->is_format_supported(screen
,
305 if (!screen
->is_format_supported(screen
,
309 PIPE_BIND_SAMPLER_VIEW
))
315 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
316 struct pipe_resource
*ptex
,
317 struct winsys_handle
*whandle
)
319 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
320 struct r600_resource
*resource
= &rtex
->resource
;
321 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
323 return r600_bo_get_winsys_handle(radeon
, resource
->bo
,
324 rtex
->pitch_in_bytes
[0], whandle
);
327 static void r600_texture_destroy(struct pipe_screen
*screen
,
328 struct pipe_resource
*ptex
)
330 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
331 struct r600_resource
*resource
= &rtex
->resource
;
332 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
334 if (rtex
->flushed_depth_texture
)
335 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
338 r600_bo_reference(radeon
, &resource
->bo
, NULL
);
343 static const struct u_resource_vtbl r600_texture_vtbl
=
345 r600_texture_get_handle
, /* get_handle */
346 r600_texture_destroy
, /* resource_destroy */
347 r600_texture_get_transfer
, /* get_transfer */
348 r600_texture_transfer_destroy
, /* transfer_destroy */
349 r600_texture_transfer_map
, /* transfer_map */
350 u_default_transfer_flush_region
,/* transfer_flush_region */
351 r600_texture_transfer_unmap
, /* transfer_unmap */
352 u_default_transfer_inline_write
/* transfer_inline_write */
355 static struct r600_resource_texture
*
356 r600_texture_create_object(struct pipe_screen
*screen
,
357 const struct pipe_resource
*base
,
359 unsigned pitch_in_bytes_override
,
360 unsigned max_buffer_size
,
363 struct r600_resource_texture
*rtex
;
364 struct r600_resource
*resource
;
365 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
367 rtex
= CALLOC_STRUCT(r600_resource_texture
);
371 resource
= &rtex
->resource
;
372 resource
->b
.b
.b
= *base
;
373 resource
->b
.b
.vtbl
= &r600_texture_vtbl
;
374 pipe_reference_init(&resource
->b
.b
.b
.reference
, 1);
375 resource
->b
.b
.b
.screen
= screen
;
377 rtex
->pitch_override
= pitch_in_bytes_override
;
378 /* only mark depth textures the HW can hit as depth textures */
379 if (util_format_is_depth_or_stencil(base
->format
) && permit_hardware_blit(screen
, base
))
382 r600_setup_miptree(screen
, rtex
, array_mode
);
384 resource
->size
= rtex
->size
;
387 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
.b
;
388 int base_align
= r600_get_base_alignment(screen
, ptex
->format
, array_mode
);
390 resource
->bo
= r600_bo(radeon
, rtex
->size
, base_align
, base
->bind
, base
->usage
);
399 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
400 const struct pipe_resource
*templ
)
402 unsigned array_mode
= 0;
403 static int force_tiling
= -1;
405 /* Would like some magic "get_bool_option_once" routine.
407 if (force_tiling
== -1) {
409 /* reenable when 2D tiling is fixed better */
410 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
411 if (r600_get_minor_version(rscreen
->radeon
) >= 9)
412 force_tiling
= debug_get_bool_option("R600_TILING", TRUE
);
414 force_tiling
= debug_get_bool_option("R600_TILING", FALSE
);
417 if (force_tiling
&& permit_hardware_blit(screen
, templ
)) {
418 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
419 !(templ
->bind
& PIPE_BIND_SCANOUT
)) {
420 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
424 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
425 util_format_is_compressed(templ
->format
))
426 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
428 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
433 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
434 struct pipe_resource
*texture
,
435 const struct pipe_surface
*surf_tmpl
)
437 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
438 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
439 unsigned level
= surf_tmpl
->u
.tex
.level
;
441 assert(surf_tmpl
->u
.tex
.first_layer
== surf_tmpl
->u
.tex
.last_layer
);
445 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
446 pipe_reference_init(&surface
->base
.reference
, 1);
447 pipe_resource_reference(&surface
->base
.texture
, texture
);
448 surface
->base
.context
= pipe
;
449 surface
->base
.format
= surf_tmpl
->format
;
450 surface
->base
.width
= mip_minify(texture
->width0
, level
);
451 surface
->base
.height
= mip_minify(texture
->height0
, level
);
452 surface
->base
.usage
= surf_tmpl
->usage
;
453 surface
->base
.texture
= texture
;
454 surface
->base
.u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
455 surface
->base
.u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
456 surface
->base
.u
.tex
.level
= level
;
458 surface
->aligned_height
= r600_texture_get_nblocksy(pipe
->screen
,
460 return &surface
->base
;
463 static void r600_surface_destroy(struct pipe_context
*pipe
,
464 struct pipe_surface
*surface
)
466 pipe_resource_reference(&surface
->texture
, NULL
);
471 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
472 const struct pipe_resource
*templ
,
473 struct winsys_handle
*whandle
)
475 struct radeon
*rw
= (struct radeon
*)screen
->winsys
;
476 struct r600_bo
*bo
= NULL
;
477 unsigned array_mode
= 0;
479 /* Support only 2D textures without mipmaps */
480 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
481 templ
->depth0
!= 1 || templ
->last_level
!= 0)
484 bo
= r600_bo_handle(rw
, whandle
->handle
, &array_mode
);
489 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
495 int r600_texture_depth_flush(struct pipe_context
*ctx
,
496 struct pipe_resource
*texture
, boolean just_create
)
498 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
499 struct pipe_resource resource
;
501 if (rtex
->flushed_depth_texture
)
504 resource
.target
= PIPE_TEXTURE_2D
;
505 resource
.format
= texture
->format
;
506 resource
.width0
= texture
->width0
;
507 resource
.height0
= texture
->height0
;
509 resource
.array_size
= 1;
510 resource
.last_level
= texture
->last_level
;
511 resource
.nr_samples
= 0;
512 resource
.usage
= PIPE_USAGE_DYNAMIC
;
514 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
516 resource
.bind
|= PIPE_BIND_DEPTH_STENCIL
;
518 rtex
->flushed_depth_texture
= (struct r600_resource_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
519 if (rtex
->flushed_depth_texture
== NULL
) {
520 R600_ERR("failed to create temporary texture to hold untiled copy\n");
524 ((struct r600_resource_texture
*)rtex
->flushed_depth_texture
)->is_flushing_texture
= TRUE
;
529 /* XXX: only do this if the depth texture has actually changed:
531 r600_blit_uncompress_depth(ctx
, rtex
);
535 /* Needs adjustment for pixelformat:
537 static INLINE
unsigned u_box_volume( const struct pipe_box
*box
)
539 return box
->width
* box
->depth
* box
->height
;
542 struct pipe_transfer
* r600_texture_get_transfer(struct pipe_context
*ctx
,
543 struct pipe_resource
*texture
,
546 const struct pipe_box
*box
)
548 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
549 struct pipe_resource resource
;
550 struct r600_transfer
*trans
;
552 boolean use_staging_texture
= FALSE
;
554 /* We cannot map a tiled texture directly because the data is
555 * in a different order, therefore we do detiling using a blit.
557 * Also, use a temporary in GTT memory for read transfers, as
558 * the CPU is much happier reading out of cached system memory
559 * than uncached VRAM.
561 if (R600_TEX_IS_TILED(rtex
, level
))
562 use_staging_texture
= TRUE
;
564 if ((usage
& PIPE_TRANSFER_READ
) && u_box_volume(box
) > 1024)
565 use_staging_texture
= TRUE
;
567 /* XXX: Use a staging texture for uploads if the underlying BO
568 * is busy. No interface for checking that currently? so do
569 * it eagerly whenever the transfer doesn't require a readback
572 if ((usage
& PIPE_TRANSFER_WRITE
) &&
573 !(usage
& (PIPE_TRANSFER_READ
|
574 PIPE_TRANSFER_DONTBLOCK
|
575 PIPE_TRANSFER_UNSYNCHRONIZED
)))
576 use_staging_texture
= TRUE
;
578 if (!permit_hardware_blit(ctx
->screen
, texture
) ||
579 (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
))
580 use_staging_texture
= FALSE
;
582 trans
= CALLOC_STRUCT(r600_transfer
);
585 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
586 trans
->transfer
.level
= level
;
587 trans
->transfer
.usage
= usage
;
588 trans
->transfer
.box
= *box
;
590 /* XXX: only readback the rectangle which is being mapped?
592 /* XXX: when discard is true, no need to read back from depth texture
594 r
= r600_texture_depth_flush(ctx
, texture
, FALSE
);
596 R600_ERR("failed to create temporary texture to hold untiled copy\n");
597 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
601 trans
->transfer
.stride
= rtex
->flushed_depth_texture
->pitch_in_bytes
[level
];
602 trans
->offset
= r600_texture_get_offset(rtex
->flushed_depth_texture
, level
, box
->z
);
603 return &trans
->transfer
;
604 } else if (use_staging_texture
) {
605 resource
.target
= PIPE_TEXTURE_2D
;
606 resource
.format
= texture
->format
;
607 resource
.width0
= box
->width
;
608 resource
.height0
= box
->height
;
610 resource
.array_size
= 1;
611 resource
.last_level
= 0;
612 resource
.nr_samples
= 0;
613 resource
.usage
= PIPE_USAGE_STAGING
;
615 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
616 /* For texture reading, the temporary (detiled) texture is used as
617 * a render target when blitting from a tiled texture. */
618 if (usage
& PIPE_TRANSFER_READ
) {
619 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
621 /* For texture writing, the temporary texture is used as a sampler
622 * when blitting into a tiled texture. */
623 if (usage
& PIPE_TRANSFER_WRITE
) {
624 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
626 /* Create the temporary texture. */
627 trans
->staging_texture
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
628 if (trans
->staging_texture
== NULL
) {
629 R600_ERR("failed to create temporary texture to hold untiled copy\n");
630 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
635 trans
->transfer
.stride
=
636 ((struct r600_resource_texture
*)trans
->staging_texture
)->pitch_in_bytes
[0];
637 if (usage
& PIPE_TRANSFER_READ
) {
638 r600_copy_to_staging_texture(ctx
, trans
);
639 /* Always referenced in the blit. */
640 ctx
->flush(ctx
, NULL
);
642 return &trans
->transfer
;
644 trans
->transfer
.stride
= rtex
->pitch_in_bytes
[level
];
645 trans
->transfer
.layer_stride
= rtex
->layer_size
[level
];
646 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
647 return &trans
->transfer
;
650 void r600_texture_transfer_destroy(struct pipe_context
*ctx
,
651 struct pipe_transfer
*transfer
)
653 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
654 struct pipe_resource
*texture
= transfer
->resource
;
655 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
657 if (rtransfer
->staging_texture
) {
658 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
659 r600_copy_from_staging_texture(ctx
, rtransfer
);
661 pipe_resource_reference(&rtransfer
->staging_texture
, NULL
);
664 if (rtex
->depth
&& !rtex
->is_flushing_texture
) {
665 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtex
->flushed_depth_texture
)
666 r600_blit_push_depth(ctx
, rtex
);
669 pipe_resource_reference(&transfer
->resource
, NULL
);
673 void* r600_texture_transfer_map(struct pipe_context
*ctx
,
674 struct pipe_transfer
* transfer
)
676 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
678 enum pipe_format format
= transfer
->resource
->format
;
679 struct radeon
*radeon
= (struct radeon
*)ctx
->screen
->winsys
;
684 if (rtransfer
->staging_texture
) {
685 bo
= ((struct r600_resource
*)rtransfer
->staging_texture
)->bo
;
687 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
689 if (rtex
->flushed_depth_texture
)
690 bo
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->bo
;
692 bo
= ((struct r600_resource
*)transfer
->resource
)->bo
;
694 offset
= rtransfer
->offset
+
695 transfer
->box
.y
/ util_format_get_blockheight(format
) * transfer
->stride
+
696 transfer
->box
.x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
699 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
700 usage
|= PB_USAGE_CPU_WRITE
;
702 if (transfer
->usage
& PIPE_TRANSFER_DISCARD
) {
705 if (transfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
) {
709 if (transfer
->usage
& PIPE_TRANSFER_READ
) {
710 usage
|= PB_USAGE_CPU_READ
;
713 if (transfer
->usage
& PIPE_TRANSFER_DONTBLOCK
) {
714 usage
|= PB_USAGE_DONTBLOCK
;
717 if (transfer
->usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
718 usage
|= PB_USAGE_UNSYNCHRONIZED
;
721 map
= r600_bo_map(radeon
, bo
, usage
, ctx
);
729 void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
730 struct pipe_transfer
* transfer
)
732 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
733 struct radeon
*radeon
= (struct radeon
*)ctx
->screen
->winsys
;
736 if (rtransfer
->staging_texture
) {
737 bo
= ((struct r600_resource
*)rtransfer
->staging_texture
)->bo
;
739 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
741 if (rtex
->flushed_depth_texture
) {
742 bo
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->bo
;
744 bo
= ((struct r600_resource
*)transfer
->resource
)->bo
;
747 r600_bo_unmap(radeon
, bo
);
750 void r600_init_surface_functions(struct r600_pipe_context
*r600
)
752 r600
->context
.create_surface
= r600_create_surface
;
753 r600
->context
.surface_destroy
= r600_surface_destroy
;
756 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
757 const unsigned char *swizzle_view
)
760 unsigned char swizzle
[4];
762 const uint32_t swizzle_shift
[4] = {
765 const uint32_t swizzle_bit
[4] = {
770 /* Combine two sets of swizzles. */
771 for (i
= 0; i
< 4; i
++) {
772 swizzle
[i
] = swizzle_view
[i
] <= UTIL_FORMAT_SWIZZLE_W
?
773 swizzle_format
[swizzle_view
[i
]] : swizzle_view
[i
];
776 memcpy(swizzle
, swizzle_format
, 4);
780 for (i
= 0; i
< 4; i
++) {
781 switch (swizzle
[i
]) {
782 case UTIL_FORMAT_SWIZZLE_Y
:
783 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
785 case UTIL_FORMAT_SWIZZLE_Z
:
786 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
788 case UTIL_FORMAT_SWIZZLE_W
:
789 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
791 case UTIL_FORMAT_SWIZZLE_0
:
792 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
794 case UTIL_FORMAT_SWIZZLE_1
:
795 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
797 default: /* UTIL_FORMAT_SWIZZLE_X */
798 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
804 /* texture format translate */
805 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
806 enum pipe_format format
,
807 const unsigned char *swizzle_view
,
808 uint32_t *word4_p
, uint32_t *yuv_format_p
)
810 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
811 const struct util_format_description
*desc
;
812 boolean uniform
= TRUE
;
813 static int r600_enable_s3tc
= -1;
816 const uint32_t sign_bit
[4] = {
817 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
818 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
819 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
820 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
822 desc
= util_format_description(format
);
824 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
826 /* Colorspace (return non-RGB formats directly). */
827 switch (desc
->colorspace
) {
828 /* Depth stencil formats */
829 case UTIL_FORMAT_COLORSPACE_ZS
:
831 case PIPE_FORMAT_Z16_UNORM
:
834 case PIPE_FORMAT_X24S8_USCALED
:
835 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
836 case PIPE_FORMAT_Z24X8_UNORM
:
837 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
840 case PIPE_FORMAT_S8X24_USCALED
:
841 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
842 case PIPE_FORMAT_X8Z24_UNORM
:
843 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
846 case PIPE_FORMAT_S8_USCALED
:
848 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
854 case UTIL_FORMAT_COLORSPACE_YUV
:
855 yuv_format
|= (1 << 30);
857 case PIPE_FORMAT_UYVY
:
858 case PIPE_FORMAT_YUYV
:
862 goto out_unknown
; /* TODO */
864 case UTIL_FORMAT_COLORSPACE_SRGB
:
865 word4
|= S_038010_FORCE_DEGAMMA(1);
872 if (r600_enable_s3tc
== -1) {
873 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
874 if (r600_get_minor_version(rscreen
->radeon
) >= 9)
875 r600_enable_s3tc
= 1;
877 r600_enable_s3tc
= debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
880 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
881 if (!r600_enable_s3tc
)
885 case PIPE_FORMAT_RGTC1_SNORM
:
886 case PIPE_FORMAT_LATC1_SNORM
:
887 word4
|= sign_bit
[0];
888 case PIPE_FORMAT_RGTC1_UNORM
:
889 case PIPE_FORMAT_LATC1_UNORM
:
892 case PIPE_FORMAT_RGTC2_SNORM
:
893 case PIPE_FORMAT_LATC2_SNORM
:
894 word4
|= sign_bit
[0] | sign_bit
[1];
895 case PIPE_FORMAT_RGTC2_UNORM
:
896 case PIPE_FORMAT_LATC2_UNORM
:
904 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
906 if (!r600_enable_s3tc
)
909 if (!util_format_s3tc_enabled
) {
914 case PIPE_FORMAT_DXT1_RGB
:
915 case PIPE_FORMAT_DXT1_RGBA
:
916 case PIPE_FORMAT_DXT1_SRGB
:
917 case PIPE_FORMAT_DXT1_SRGBA
:
920 case PIPE_FORMAT_DXT3_RGBA
:
921 case PIPE_FORMAT_DXT3_SRGBA
:
924 case PIPE_FORMAT_DXT5_RGBA
:
925 case PIPE_FORMAT_DXT5_SRGBA
:
933 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
934 result
= FMT_5_9_9_9_SHAREDEXP
;
936 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
937 result
= FMT_10_11_11_FLOAT
;
942 for (i
= 0; i
< desc
->nr_channels
; i
++) {
943 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
944 word4
|= sign_bit
[i
];
948 /* R8G8Bx_SNORM - TODO CxV8U8 */
950 /* See whether the components are of the same size. */
951 for (i
= 1; i
< desc
->nr_channels
; i
++) {
952 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
955 /* Non-uniform formats. */
957 switch(desc
->nr_channels
) {
959 if (desc
->channel
[0].size
== 5 &&
960 desc
->channel
[1].size
== 6 &&
961 desc
->channel
[2].size
== 5) {
967 if (desc
->channel
[0].size
== 5 &&
968 desc
->channel
[1].size
== 5 &&
969 desc
->channel
[2].size
== 5 &&
970 desc
->channel
[3].size
== 1) {
971 result
= FMT_1_5_5_5
;
974 if (desc
->channel
[0].size
== 10 &&
975 desc
->channel
[1].size
== 10 &&
976 desc
->channel
[2].size
== 10 &&
977 desc
->channel
[3].size
== 2) {
978 result
= FMT_2_10_10_10
;
986 /* Find the first non-VOID channel. */
987 for (i
= 0; i
< 4; i
++) {
988 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
996 /* uniform formats */
997 switch (desc
->channel
[i
].type
) {
998 case UTIL_FORMAT_TYPE_UNSIGNED
:
999 case UTIL_FORMAT_TYPE_SIGNED
:
1000 if (!desc
->channel
[i
].normalized
&&
1001 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
1005 switch (desc
->channel
[i
].size
) {
1007 switch (desc
->nr_channels
) {
1012 result
= FMT_4_4_4_4
;
1017 switch (desc
->nr_channels
) {
1025 result
= FMT_8_8_8_8
;
1030 switch (desc
->nr_channels
) {
1038 result
= FMT_16_16_16_16
;
1043 switch (desc
->nr_channels
) {
1051 result
= FMT_32_32_32_32
;
1057 case UTIL_FORMAT_TYPE_FLOAT
:
1058 switch (desc
->channel
[i
].size
) {
1060 switch (desc
->nr_channels
) {
1062 result
= FMT_16_FLOAT
;
1065 result
= FMT_16_16_FLOAT
;
1068 result
= FMT_16_16_16_16_FLOAT
;
1073 switch (desc
->nr_channels
) {
1075 result
= FMT_32_FLOAT
;
1078 result
= FMT_32_32_FLOAT
;
1081 result
= FMT_32_32_32_32_FLOAT
;
1092 *yuv_format_p
= yuv_format
;
1095 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */