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r600g: properly check whether texture is busy in get_transfer
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <errno.h>
28 #include "pipe/p_screen.h"
29 #include "util/u_format.h"
30 #include "util/u_format_s3tc.h"
31 #include "util/u_math.h"
32 #include "util/u_inlines.h"
33 #include "util/u_memory.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
37 #include "r600d.h"
38 #include "r600_formats.h"
39
40 /* Copy from a full GPU texture to a transfer's staging one. */
41 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
42 {
43 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
44 struct pipe_resource *texture = transfer->resource;
45
46 ctx->resource_copy_region(ctx, rtransfer->staging_texture,
47 0, 0, 0, 0, texture, transfer->level,
48 &transfer->box);
49 }
50
51
52 /* Copy from a transfer's staging texture to a full GPU one. */
53 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
54 {
55 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
56 struct pipe_resource *texture = transfer->resource;
57 struct pipe_box sbox;
58
59 sbox.x = sbox.y = sbox.z = 0;
60 sbox.width = transfer->box.width;
61 sbox.height = transfer->box.height;
62 /* XXX that might be wrong */
63 sbox.depth = 1;
64 ctx->resource_copy_region(ctx, texture, transfer->level,
65 transfer->box.x, transfer->box.y, transfer->box.z,
66 rtransfer->staging_texture,
67 0, &sbox);
68 }
69
70 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
71 unsigned level, unsigned layer)
72 {
73 unsigned offset = rtex->offset[level];
74
75 switch (rtex->resource.b.b.b.target) {
76 case PIPE_TEXTURE_3D:
77 case PIPE_TEXTURE_CUBE:
78 default:
79 return offset + layer * rtex->layer_size[level];
80 }
81 }
82
83 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
84 enum pipe_format format,
85 unsigned array_mode)
86 {
87 struct r600_screen* rscreen = (struct r600_screen *)screen;
88 unsigned pixsize = util_format_get_blocksize(format);
89 int p_align;
90
91 switch(array_mode) {
92 case V_038000_ARRAY_1D_TILED_THIN1:
93 p_align = MAX2(8,
94 ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
95 break;
96 case V_038000_ARRAY_2D_TILED_THIN1:
97 p_align = MAX2(rscreen->tiling_info.num_banks,
98 (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
99 rscreen->tiling_info.num_banks)) * 8;
100 break;
101 case V_038000_ARRAY_LINEAR_ALIGNED:
102 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
103 break;
104 case V_038000_ARRAY_LINEAR_GENERAL:
105 default:
106 p_align = rscreen->tiling_info.group_bytes / pixsize;
107 break;
108 }
109 return p_align;
110 }
111
112 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
113 unsigned array_mode)
114 {
115 struct r600_screen* rscreen = (struct r600_screen *)screen;
116 int h_align;
117
118 switch (array_mode) {
119 case V_038000_ARRAY_2D_TILED_THIN1:
120 h_align = rscreen->tiling_info.num_channels * 8;
121 break;
122 case V_038000_ARRAY_1D_TILED_THIN1:
123 case V_038000_ARRAY_LINEAR_ALIGNED:
124 h_align = 8;
125 break;
126 case V_038000_ARRAY_LINEAR_GENERAL:
127 default:
128 h_align = 1;
129 break;
130 }
131 return h_align;
132 }
133
134 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
135 enum pipe_format format,
136 unsigned array_mode)
137 {
138 struct r600_screen* rscreen = (struct r600_screen *)screen;
139 unsigned pixsize = util_format_get_blocksize(format);
140 int p_align = r600_get_block_alignment(screen, format, array_mode);
141 int h_align = r600_get_height_alignment(screen, array_mode);
142 int b_align;
143
144 switch (array_mode) {
145 case V_038000_ARRAY_2D_TILED_THIN1:
146 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
147 p_align * pixsize * h_align);
148 break;
149 case V_038000_ARRAY_1D_TILED_THIN1:
150 case V_038000_ARRAY_LINEAR_ALIGNED:
151 case V_038000_ARRAY_LINEAR_GENERAL:
152 default:
153 b_align = rscreen->tiling_info.group_bytes;
154 break;
155 }
156 return b_align;
157 }
158
159 static unsigned mip_minify(unsigned size, unsigned level)
160 {
161 unsigned val;
162 val = u_minify(size, level);
163 if (level > 0)
164 val = util_next_power_of_two(val);
165 return val;
166 }
167
168 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
169 struct r600_resource_texture *rtex,
170 unsigned level)
171 {
172 struct pipe_resource *ptex = &rtex->resource.b.b.b;
173 unsigned nblocksx, block_align, width;
174 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
175
176 if (rtex->pitch_override)
177 return rtex->pitch_override / blocksize;
178
179 width = mip_minify(ptex->width0, level);
180 nblocksx = util_format_get_nblocksx(rtex->real_format, width);
181
182 block_align = r600_get_block_alignment(screen, rtex->real_format,
183 rtex->array_mode[level]);
184 nblocksx = align(nblocksx, block_align);
185 return nblocksx;
186 }
187
188 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
189 struct r600_resource_texture *rtex,
190 unsigned level)
191 {
192 struct pipe_resource *ptex = &rtex->resource.b.b.b;
193 unsigned height, tile_height;
194
195 height = mip_minify(ptex->height0, level);
196 height = util_format_get_nblocksy(rtex->real_format, height);
197 tile_height = r600_get_height_alignment(screen,
198 rtex->array_mode[level]);
199
200 /* XXX Hack around an alignment issue. Less tests fail with this.
201 *
202 * The thing is depth-stencil buffers should be tiled, i.e.
203 * the alignment should be >=8. If I make them tiled, stencil starts
204 * working because it no longer overlaps with the depth buffer
205 * in memory, but texturing like drawpix-stencil breaks. */
206 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
207 tile_height = 8;
208
209 height = align(height, tile_height);
210 return height;
211 }
212
213 static void r600_texture_set_array_mode(struct pipe_screen *screen,
214 struct r600_resource_texture *rtex,
215 unsigned level, unsigned array_mode)
216 {
217 struct pipe_resource *ptex = &rtex->resource.b.b.b;
218
219 switch (array_mode) {
220 case V_0280A0_ARRAY_LINEAR_GENERAL:
221 case V_0280A0_ARRAY_LINEAR_ALIGNED:
222 case V_0280A0_ARRAY_1D_TILED_THIN1:
223 default:
224 rtex->array_mode[level] = array_mode;
225 break;
226 case V_0280A0_ARRAY_2D_TILED_THIN1:
227 {
228 unsigned w, h, tile_height, tile_width;
229
230 tile_height = r600_get_height_alignment(screen, array_mode);
231 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
232
233 w = mip_minify(ptex->width0, level);
234 h = mip_minify(ptex->height0, level);
235 if (w <= tile_width || h <= tile_height)
236 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
237 else
238 rtex->array_mode[level] = array_mode;
239 }
240 break;
241 }
242 }
243
244 static int r600_init_surface(struct radeon_surface *surface,
245 const struct pipe_resource *ptex,
246 unsigned array_mode)
247 {
248 surface->npix_x = ptex->width0;
249 surface->npix_y = ptex->height0;
250 surface->npix_z = ptex->depth0;
251 surface->blk_w = util_format_get_blockwidth(ptex->format);
252 surface->blk_h = util_format_get_blockheight(ptex->format);
253 surface->blk_d = 1;
254 surface->array_size = 1;
255 surface->last_level = ptex->last_level;
256 surface->bpe = util_format_get_blocksize(ptex->format);
257 /* align byte per element on dword */
258 if (surface->bpe == 3) {
259 surface->bpe = 4;
260 }
261 surface->nsamples = 1;
262 surface->flags = 0;
263 switch (array_mode) {
264 case V_038000_ARRAY_1D_TILED_THIN1:
265 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
266 break;
267 case V_038000_ARRAY_2D_TILED_THIN1:
268 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
269 break;
270 case V_038000_ARRAY_LINEAR_ALIGNED:
271 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
272 break;
273 case V_038000_ARRAY_LINEAR_GENERAL:
274 default:
275 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
276 break;
277 }
278 switch (ptex->target) {
279 case PIPE_TEXTURE_1D:
280 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
281 break;
282 case PIPE_TEXTURE_RECT:
283 case PIPE_TEXTURE_2D:
284 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
285 break;
286 case PIPE_TEXTURE_3D:
287 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
288 break;
289 case PIPE_TEXTURE_1D_ARRAY:
290 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
291 surface->array_size = ptex->array_size;
292 break;
293 case PIPE_TEXTURE_2D_ARRAY:
294 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
295 surface->array_size = ptex->array_size;
296 break;
297 case PIPE_TEXTURE_CUBE:
298 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
299 break;
300 case PIPE_BUFFER:
301 default:
302 return -EINVAL;
303 }
304 if (ptex->bind & PIPE_BIND_SCANOUT) {
305 surface->flags |= RADEON_SURF_SCANOUT;
306 }
307 if (util_format_is_depth_and_stencil(ptex->format)) {
308 surface->flags |= RADEON_SURF_ZBUFFER;
309 surface->flags |= RADEON_SURF_SBUFFER;
310 }
311
312 return 0;
313 }
314
315 static int r600_setup_surface(struct pipe_screen *screen,
316 struct r600_resource_texture *rtex,
317 unsigned array_mode,
318 unsigned pitch_in_bytes_override)
319 {
320 struct pipe_resource *ptex = &rtex->resource.b.b.b;
321 struct r600_screen *rscreen = (struct r600_screen*)screen;
322 unsigned i;
323 int r;
324
325 if (util_format_is_depth_or_stencil(rtex->real_format)) {
326 rtex->surface.flags |= RADEON_SURF_ZBUFFER;
327 rtex->surface.flags |= RADEON_SURF_SBUFFER;
328 }
329
330 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
331 if (r) {
332 return r;
333 }
334 rtex->size = rtex->surface.bo_size;
335 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
336 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
337 * for those
338 */
339 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
340 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
341 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
342 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
343 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
344 }
345 }
346 for (i = 0; i <= ptex->last_level; i++) {
347 rtex->offset[i] = rtex->surface.level[i].offset;
348 rtex->layer_size[i] = rtex->surface.level[i].slice_size;
349 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
350 switch (rtex->surface.level[i].mode) {
351 case RADEON_SURF_MODE_LINEAR_ALIGNED:
352 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
353 break;
354 case RADEON_SURF_MODE_1D:
355 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
356 break;
357 case RADEON_SURF_MODE_2D:
358 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
359 break;
360 default:
361 case RADEON_SURF_MODE_LINEAR:
362 rtex->array_mode[i] = 0;
363 break;
364 }
365 }
366 return 0;
367 }
368
369 static void r600_setup_miptree(struct pipe_screen *screen,
370 struct r600_resource_texture *rtex,
371 unsigned array_mode)
372 {
373 struct pipe_resource *ptex = &rtex->resource.b.b.b;
374 enum chip_class chipc = ((struct r600_screen*)screen)->chip_class;
375 unsigned size, layer_size, i, offset;
376 unsigned nblocksx, nblocksy;
377
378 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
379 unsigned blocksize = util_format_get_blocksize(rtex->real_format);
380 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
381
382 r600_texture_set_array_mode(screen, rtex, i, array_mode);
383
384 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
385 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
386
387 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL)
388 layer_size = align(nblocksx, 64) * nblocksy * blocksize;
389 else
390 layer_size = nblocksx * nblocksy * blocksize;
391
392 if (ptex->target == PIPE_TEXTURE_CUBE) {
393 if (chipc >= R700)
394 size = layer_size * 8;
395 else
396 size = layer_size * 6;
397 }
398 else if (ptex->target == PIPE_TEXTURE_3D)
399 size = layer_size * u_minify(ptex->depth0, i);
400 else
401 size = layer_size * ptex->array_size;
402
403 /* align base image and start of miptree */
404 if ((i == 0) || (i == 1))
405 offset = align(offset, base_align);
406 rtex->offset[i] = offset;
407 rtex->layer_size[i] = layer_size;
408 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
409 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
410
411 offset += size;
412 }
413 rtex->size = offset;
414 }
415
416 /* Figure out whether u_blitter will fallback to a transfer operation.
417 * If so, don't use a staging resource.
418 */
419 static boolean permit_hardware_blit(struct pipe_screen *screen,
420 const struct pipe_resource *res)
421 {
422 unsigned bind;
423
424 if (util_format_is_depth_or_stencil(res->format))
425 bind = PIPE_BIND_DEPTH_STENCIL;
426 else
427 bind = PIPE_BIND_RENDER_TARGET;
428
429 /* hackaround for S3TC */
430 if (util_format_is_compressed(res->format))
431 return TRUE;
432
433 if (!screen->is_format_supported(screen,
434 res->format,
435 res->target,
436 res->nr_samples,
437 bind))
438 return FALSE;
439
440 if (!screen->is_format_supported(screen,
441 res->format,
442 res->target,
443 res->nr_samples,
444 PIPE_BIND_SAMPLER_VIEW))
445 return FALSE;
446
447 switch (res->usage) {
448 case PIPE_USAGE_STREAM:
449 case PIPE_USAGE_STAGING:
450 return FALSE;
451
452 default:
453 return TRUE;
454 }
455 }
456
457 static boolean r600_texture_get_handle(struct pipe_screen* screen,
458 struct pipe_resource *ptex,
459 struct winsys_handle *whandle)
460 {
461 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
462 struct r600_resource *resource = &rtex->resource;
463 struct r600_screen *rscreen = (struct r600_screen*)screen;
464
465 return rscreen->ws->buffer_get_handle(resource->buf,
466 rtex->pitch_in_bytes[0], whandle);
467 }
468
469 static void r600_texture_destroy(struct pipe_screen *screen,
470 struct pipe_resource *ptex)
471 {
472 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
473 struct r600_resource *resource = &rtex->resource;
474
475 if (rtex->flushed_depth_texture)
476 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
477
478 if (rtex->stencil)
479 pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL);
480
481 pb_reference(&resource->buf, NULL);
482 FREE(rtex);
483 }
484
485 static const struct u_resource_vtbl r600_texture_vtbl =
486 {
487 r600_texture_get_handle, /* get_handle */
488 r600_texture_destroy, /* resource_destroy */
489 r600_texture_get_transfer, /* get_transfer */
490 r600_texture_transfer_destroy, /* transfer_destroy */
491 r600_texture_transfer_map, /* transfer_map */
492 u_default_transfer_flush_region,/* transfer_flush_region */
493 r600_texture_transfer_unmap, /* transfer_unmap */
494 u_default_transfer_inline_write /* transfer_inline_write */
495 };
496
497 DEBUG_GET_ONCE_BOOL_OPTION(use_surface, "R600_SURF", TRUE);
498
499 static struct r600_resource_texture *
500 r600_texture_create_object(struct pipe_screen *screen,
501 const struct pipe_resource *base,
502 unsigned array_mode,
503 unsigned pitch_in_bytes_override,
504 unsigned max_buffer_size,
505 struct pb_buffer *buf,
506 boolean alloc_bo,
507 struct radeon_surface *surface)
508 {
509 struct r600_resource_texture *rtex;
510 struct r600_resource *resource;
511 struct r600_screen *rscreen = (struct r600_screen*)screen;
512 int r;
513
514 /* FIXME ugly temporary hack to allow to switch btw current code
515 * and common surface allocator code
516 */
517 if (debug_get_option_use_surface()) {
518 rscreen->use_surface = 1;
519 }
520
521 rtex = CALLOC_STRUCT(r600_resource_texture);
522 if (rtex == NULL)
523 return NULL;
524
525 resource = &rtex->resource;
526 resource->b.b.b = *base;
527 resource->b.b.vtbl = &r600_texture_vtbl;
528 pipe_reference_init(&resource->b.b.b.reference, 1);
529 resource->b.b.b.screen = screen;
530 rtex->pitch_override = pitch_in_bytes_override;
531 rtex->real_format = base->format;
532
533 /* We must split depth and stencil into two separate buffers on Evergreen. */
534 if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) &&
535 ((struct r600_screen*)screen)->chip_class >= EVERGREEN &&
536 util_format_is_depth_and_stencil(base->format) &&
537 !rscreen->use_surface) {
538 struct pipe_resource stencil;
539 unsigned stencil_pitch_override = 0;
540
541 switch (base->format) {
542 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
543 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
544 break;
545 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
546 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
547 break;
548 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
549 rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
550 break;
551 default:
552 assert(0);
553 FREE(rtex);
554 return NULL;
555 }
556
557 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
558 if (pitch_in_bytes_override) {
559 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT ||
560 base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
561 stencil_pitch_override = pitch_in_bytes_override / 4;
562 }
563
564 /* Allocate the stencil buffer. */
565 stencil = *base;
566 stencil.format = PIPE_FORMAT_S8_UINT;
567 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
568 stencil_pitch_override,
569 max_buffer_size, NULL, FALSE, surface);
570 if (!rtex->stencil) {
571 FREE(rtex);
572 return NULL;
573 }
574 /* Proceed in creating the depth buffer. */
575 }
576
577 /* only mark depth textures the HW can hit as depth textures */
578 if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
579 rtex->is_depth = true;
580
581 r600_setup_miptree(screen, rtex, array_mode);
582 if (rscreen->use_surface) {
583 rtex->surface = *surface;
584 r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
585 if (r) {
586 FREE(rtex);
587 return NULL;
588 }
589 }
590
591 /* If we initialized separate stencil for Evergreen. place it after depth. */
592 if (rtex->stencil) {
593 unsigned stencil_align, stencil_offset;
594
595 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
596 stencil_offset = align(rtex->size, stencil_align);
597
598 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++)
599 rtex->stencil->offset[i] += stencil_offset;
600
601 rtex->size = stencil_offset + rtex->stencil->size;
602 }
603
604 /* Now create the backing buffer. */
605 if (!buf && alloc_bo) {
606 struct pipe_resource *ptex = &rtex->resource.b.b.b;
607 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
608
609 if (rscreen->use_surface) {
610 base_align = rtex->surface.bo_alignment;
611 } else if (util_format_is_depth_or_stencil(rtex->real_format)) {
612 /* ugly work around depth buffer need stencil room at end of bo */
613 rtex->size += ptex->width0 * ptex->height0;
614 }
615 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
616 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
617 FREE(rtex);
618 return NULL;
619 }
620 } else if (buf) {
621 resource->buf = buf;
622 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
623 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
624 }
625
626 if (rtex->stencil) {
627 pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf);
628 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf;
629 rtex->stencil->resource.domains = rtex->resource.domains;
630 }
631 return rtex;
632 }
633
634 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
635 const struct pipe_resource *templ)
636 {
637 struct r600_screen *rscreen = (struct r600_screen*)screen;
638 struct radeon_surface surface;
639 unsigned array_mode = 0;
640 int r;
641
642 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
643 !(templ->bind & PIPE_BIND_SCANOUT)) {
644 if (rscreen->use_surface) {
645 if (permit_hardware_blit(screen, templ)) {
646 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
647 }
648 } else if (util_format_is_compressed(templ->format)) {
649 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
650 }
651 }
652
653 r = r600_init_surface(&surface, templ, array_mode);
654 if (r) {
655 return NULL;
656 }
657 r = rscreen->ws->surface_best(rscreen->ws, &surface);
658 if (r) {
659 return NULL;
660 }
661 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
662 0, 0, NULL, TRUE, &surface);
663 }
664
665 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
666 struct pipe_resource *texture,
667 const struct pipe_surface *surf_tmpl)
668 {
669 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
670 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
671 unsigned level = surf_tmpl->u.tex.level;
672
673 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
674 if (surface == NULL)
675 return NULL;
676 /* XXX no offset */
677 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
678 pipe_reference_init(&surface->base.reference, 1);
679 pipe_resource_reference(&surface->base.texture, texture);
680 surface->base.context = pipe;
681 surface->base.format = surf_tmpl->format;
682 surface->base.width = mip_minify(texture->width0, level);
683 surface->base.height = mip_minify(texture->height0, level);
684 surface->base.usage = surf_tmpl->usage;
685 surface->base.texture = texture;
686 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
687 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
688 surface->base.u.tex.level = level;
689
690 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
691 rtex, level);
692 return &surface->base;
693 }
694
695 static void r600_surface_destroy(struct pipe_context *pipe,
696 struct pipe_surface *surface)
697 {
698 pipe_resource_reference(&surface->texture, NULL);
699 FREE(surface);
700 }
701
702 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
703 const struct pipe_resource *templ,
704 struct winsys_handle *whandle)
705 {
706 struct r600_screen *rscreen = (struct r600_screen*)screen;
707 struct pb_buffer *buf = NULL;
708 unsigned stride = 0;
709 unsigned array_mode = 0;
710 enum radeon_bo_layout micro, macro;
711 struct radeon_surface surface;
712 int r;
713
714 /* Support only 2D textures without mipmaps */
715 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
716 templ->depth0 != 1 || templ->last_level != 0)
717 return NULL;
718
719 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
720 if (!buf)
721 return NULL;
722
723 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
724 &surface.bankw, &surface.bankh,
725 &surface.tile_split,
726 &surface.stencil_tile_split,
727 &surface.mtilea);
728
729 if (macro == RADEON_LAYOUT_TILED)
730 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
731 else if (micro == RADEON_LAYOUT_TILED)
732 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
733 else
734 array_mode = 0;
735
736 r = r600_init_surface(&surface, templ, array_mode);
737 if (r) {
738 return NULL;
739 }
740 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
741 stride, 0, buf, FALSE, &surface);
742 }
743
744 int r600_texture_depth_flush(struct pipe_context *ctx,
745 struct pipe_resource *texture, boolean just_create)
746 {
747 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
748 struct pipe_resource resource;
749
750 if (rtex->flushed_depth_texture)
751 goto out;
752
753 resource.target = texture->target;
754 resource.format = texture->format;
755 resource.width0 = texture->width0;
756 resource.height0 = texture->height0;
757 resource.depth0 = texture->depth0;
758 resource.array_size = texture->array_size;
759 resource.last_level = texture->last_level;
760 resource.nr_samples = texture->nr_samples;
761 resource.usage = PIPE_USAGE_DYNAMIC;
762 resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL;
763 resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags;
764
765 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
766 if (rtex->flushed_depth_texture == NULL) {
767 R600_ERR("failed to create temporary texture to hold untiled copy\n");
768 return -ENOMEM;
769 }
770
771 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
772 out:
773 if (just_create)
774 return 0;
775
776 /* XXX: only do this if the depth texture has actually changed:
777 */
778 r600_blit_uncompress_depth(ctx, rtex);
779 return 0;
780 }
781
782 /* Needs adjustment for pixelformat:
783 */
784 static INLINE unsigned u_box_volume( const struct pipe_box *box )
785 {
786 return box->width * box->depth * box->height;
787 };
788
789 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
790 struct pipe_resource *texture,
791 unsigned level,
792 unsigned usage,
793 const struct pipe_box *box)
794 {
795 struct r600_context *rctx = (struct r600_context*)ctx;
796 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
797 struct pipe_resource resource;
798 struct r600_transfer *trans;
799 int r;
800 boolean use_staging_texture = FALSE;
801
802 if (usage & PIPE_TRANSFER_MAP_PERMANENTLY) {
803 return NULL;
804 }
805
806 /* We cannot map a tiled texture directly because the data is
807 * in a different order, therefore we do detiling using a blit.
808 *
809 * Also, use a temporary in GTT memory for read transfers, as
810 * the CPU is much happier reading out of cached system memory
811 * than uncached VRAM.
812 */
813 if (R600_TEX_IS_TILED(rtex, level))
814 use_staging_texture = TRUE;
815
816 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
817 use_staging_texture = TRUE;
818
819 /* Use a staging texture for uploads if the underlying BO is busy. */
820 if (!(usage & PIPE_TRANSFER_READ) &&
821 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf) ||
822 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE)))
823 use_staging_texture = TRUE;
824
825 if (!permit_hardware_blit(ctx->screen, texture) ||
826 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
827 use_staging_texture = FALSE;
828
829 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
830 return NULL;
831
832 trans = CALLOC_STRUCT(r600_transfer);
833 if (trans == NULL)
834 return NULL;
835 pipe_resource_reference(&trans->transfer.resource, texture);
836 trans->transfer.level = level;
837 trans->transfer.usage = usage;
838 trans->transfer.box = *box;
839 if (rtex->is_depth) {
840 /* XXX: only readback the rectangle which is being mapped?
841 */
842 /* XXX: when discard is true, no need to read back from depth texture
843 */
844 r = r600_texture_depth_flush(ctx, texture, FALSE);
845 if (r < 0) {
846 R600_ERR("failed to create temporary texture to hold untiled copy\n");
847 pipe_resource_reference(&trans->transfer.resource, NULL);
848 FREE(trans);
849 return NULL;
850 }
851 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
852 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
853 return &trans->transfer;
854 } else if (use_staging_texture) {
855 resource.target = PIPE_TEXTURE_2D;
856 resource.format = texture->format;
857 resource.width0 = box->width;
858 resource.height0 = box->height;
859 resource.depth0 = 1;
860 resource.array_size = 1;
861 resource.last_level = 0;
862 resource.nr_samples = 0;
863 resource.usage = PIPE_USAGE_STAGING;
864 resource.bind = 0;
865 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
866 /* For texture reading, the temporary (detiled) texture is used as
867 * a render target when blitting from a tiled texture. */
868 if (usage & PIPE_TRANSFER_READ) {
869 resource.bind |= PIPE_BIND_RENDER_TARGET;
870 }
871 /* For texture writing, the temporary texture is used as a sampler
872 * when blitting into a tiled texture. */
873 if (usage & PIPE_TRANSFER_WRITE) {
874 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
875 }
876 /* Create the temporary texture. */
877 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
878 if (trans->staging_texture == NULL) {
879 R600_ERR("failed to create temporary texture to hold untiled copy\n");
880 pipe_resource_reference(&trans->transfer.resource, NULL);
881 FREE(trans);
882 return NULL;
883 }
884
885 trans->transfer.stride =
886 ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
887 if (usage & PIPE_TRANSFER_READ) {
888 r600_copy_to_staging_texture(ctx, trans);
889 /* Always referenced in the blit. */
890 r600_flush(ctx, NULL, 0);
891 }
892 return &trans->transfer;
893 }
894 trans->transfer.stride = rtex->pitch_in_bytes[level];
895 trans->transfer.layer_stride = rtex->layer_size[level];
896 trans->offset = r600_texture_get_offset(rtex, level, box->z);
897 return &trans->transfer;
898 }
899
900 void r600_texture_transfer_destroy(struct pipe_context *ctx,
901 struct pipe_transfer *transfer)
902 {
903 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
904 struct pipe_resource *texture = transfer->resource;
905 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
906
907 if (rtransfer->staging_texture) {
908 if (transfer->usage & PIPE_TRANSFER_WRITE) {
909 r600_copy_from_staging_texture(ctx, rtransfer);
910 }
911 pipe_resource_reference(&rtransfer->staging_texture, NULL);
912 }
913
914 if (rtex->is_depth && !rtex->is_flushing_texture) {
915 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
916 r600_blit_push_depth(ctx, rtex);
917 }
918
919 pipe_resource_reference(&transfer->resource, NULL);
920 FREE(transfer);
921 }
922
923 void* r600_texture_transfer_map(struct pipe_context *ctx,
924 struct pipe_transfer* transfer)
925 {
926 struct r600_context *rctx = (struct r600_context *)ctx;
927 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
928 struct pb_buffer *buf;
929 enum pipe_format format = transfer->resource->format;
930 unsigned offset = 0;
931 char *map;
932
933 if (rtransfer->staging_texture) {
934 buf = ((struct r600_resource *)rtransfer->staging_texture)->buf;
935 } else {
936 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
937
938 if (rtex->flushed_depth_texture)
939 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf;
940 else
941 buf = ((struct r600_resource *)transfer->resource)->buf;
942
943 offset = rtransfer->offset +
944 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
945 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
946 }
947
948 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
949 return NULL;
950 }
951
952 return map + offset;
953 }
954
955 void r600_texture_transfer_unmap(struct pipe_context *ctx,
956 struct pipe_transfer* transfer)
957 {
958 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
959 struct r600_context *rctx = (struct r600_context*)ctx;
960 struct pb_buffer *buf;
961
962 if (rtransfer->staging_texture) {
963 buf = ((struct r600_resource *)rtransfer->staging_texture)->buf;
964 } else {
965 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
966
967 if (rtex->flushed_depth_texture) {
968 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf;
969 } else {
970 buf = ((struct r600_resource *)transfer->resource)->buf;
971 }
972 }
973 rctx->ws->buffer_unmap(buf);
974 }
975
976 void r600_init_surface_functions(struct r600_context *r600)
977 {
978 r600->context.create_surface = r600_create_surface;
979 r600->context.surface_destroy = r600_surface_destroy;
980 }
981
982 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
983 const unsigned char *swizzle_view)
984 {
985 unsigned i;
986 unsigned char swizzle[4];
987 unsigned result = 0;
988 const uint32_t swizzle_shift[4] = {
989 16, 19, 22, 25,
990 };
991 const uint32_t swizzle_bit[4] = {
992 0, 1, 2, 3,
993 };
994
995 if (swizzle_view) {
996 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
997 } else {
998 memcpy(swizzle, swizzle_format, 4);
999 }
1000
1001 /* Get swizzle. */
1002 for (i = 0; i < 4; i++) {
1003 switch (swizzle[i]) {
1004 case UTIL_FORMAT_SWIZZLE_Y:
1005 result |= swizzle_bit[1] << swizzle_shift[i];
1006 break;
1007 case UTIL_FORMAT_SWIZZLE_Z:
1008 result |= swizzle_bit[2] << swizzle_shift[i];
1009 break;
1010 case UTIL_FORMAT_SWIZZLE_W:
1011 result |= swizzle_bit[3] << swizzle_shift[i];
1012 break;
1013 case UTIL_FORMAT_SWIZZLE_0:
1014 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1015 break;
1016 case UTIL_FORMAT_SWIZZLE_1:
1017 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1018 break;
1019 default: /* UTIL_FORMAT_SWIZZLE_X */
1020 result |= swizzle_bit[0] << swizzle_shift[i];
1021 }
1022 }
1023 return result;
1024 }
1025
1026 /* texture format translate */
1027 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1028 enum pipe_format format,
1029 const unsigned char *swizzle_view,
1030 uint32_t *word4_p, uint32_t *yuv_format_p)
1031 {
1032 uint32_t result = 0, word4 = 0, yuv_format = 0;
1033 const struct util_format_description *desc;
1034 boolean uniform = TRUE;
1035 static int r600_enable_s3tc = -1;
1036 bool is_srgb_valid = FALSE;
1037
1038 int i;
1039 const uint32_t sign_bit[4] = {
1040 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1041 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1042 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1043 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1044 };
1045 desc = util_format_description(format);
1046
1047 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
1048
1049 /* Colorspace (return non-RGB formats directly). */
1050 switch (desc->colorspace) {
1051 /* Depth stencil formats */
1052 case UTIL_FORMAT_COLORSPACE_ZS:
1053 switch (format) {
1054 case PIPE_FORMAT_Z16_UNORM:
1055 result = FMT_16;
1056 goto out_word4;
1057 case PIPE_FORMAT_X24S8_UINT:
1058 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1059 case PIPE_FORMAT_Z24X8_UNORM:
1060 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1061 result = FMT_8_24;
1062 goto out_word4;
1063 case PIPE_FORMAT_S8X24_UINT:
1064 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1065 case PIPE_FORMAT_X8Z24_UNORM:
1066 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1067 result = FMT_24_8;
1068 goto out_word4;
1069 case PIPE_FORMAT_S8_UINT:
1070 result = FMT_8;
1071 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1072 goto out_word4;
1073 case PIPE_FORMAT_Z32_FLOAT:
1074 result = FMT_32_FLOAT;
1075 goto out_word4;
1076 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1077 result = FMT_X24_8_32_FLOAT;
1078 goto out_word4;
1079 default:
1080 goto out_unknown;
1081 }
1082
1083 case UTIL_FORMAT_COLORSPACE_YUV:
1084 yuv_format |= (1 << 30);
1085 switch (format) {
1086 case PIPE_FORMAT_UYVY:
1087 case PIPE_FORMAT_YUYV:
1088 default:
1089 break;
1090 }
1091 goto out_unknown; /* TODO */
1092
1093 case UTIL_FORMAT_COLORSPACE_SRGB:
1094 word4 |= S_038010_FORCE_DEGAMMA(1);
1095 break;
1096
1097 default:
1098 break;
1099 }
1100
1101 if (r600_enable_s3tc == -1) {
1102 struct r600_screen *rscreen = (struct r600_screen *)screen;
1103 if (rscreen->info.drm_minor >= 9)
1104 r600_enable_s3tc = 1;
1105 else
1106 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
1107 }
1108
1109 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1110 if (!r600_enable_s3tc)
1111 goto out_unknown;
1112
1113 switch (format) {
1114 case PIPE_FORMAT_RGTC1_SNORM:
1115 case PIPE_FORMAT_LATC1_SNORM:
1116 word4 |= sign_bit[0];
1117 case PIPE_FORMAT_RGTC1_UNORM:
1118 case PIPE_FORMAT_LATC1_UNORM:
1119 result = FMT_BC4;
1120 goto out_word4;
1121 case PIPE_FORMAT_RGTC2_SNORM:
1122 case PIPE_FORMAT_LATC2_SNORM:
1123 word4 |= sign_bit[0] | sign_bit[1];
1124 case PIPE_FORMAT_RGTC2_UNORM:
1125 case PIPE_FORMAT_LATC2_UNORM:
1126 result = FMT_BC5;
1127 goto out_word4;
1128 default:
1129 goto out_unknown;
1130 }
1131 }
1132
1133 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1134
1135 if (!r600_enable_s3tc)
1136 goto out_unknown;
1137
1138 if (!util_format_s3tc_enabled) {
1139 goto out_unknown;
1140 }
1141
1142 switch (format) {
1143 case PIPE_FORMAT_DXT1_RGB:
1144 case PIPE_FORMAT_DXT1_RGBA:
1145 case PIPE_FORMAT_DXT1_SRGB:
1146 case PIPE_FORMAT_DXT1_SRGBA:
1147 result = FMT_BC1;
1148 is_srgb_valid = TRUE;
1149 goto out_word4;
1150 case PIPE_FORMAT_DXT3_RGBA:
1151 case PIPE_FORMAT_DXT3_SRGBA:
1152 result = FMT_BC2;
1153 is_srgb_valid = TRUE;
1154 goto out_word4;
1155 case PIPE_FORMAT_DXT5_RGBA:
1156 case PIPE_FORMAT_DXT5_SRGBA:
1157 result = FMT_BC3;
1158 is_srgb_valid = TRUE;
1159 goto out_word4;
1160 default:
1161 goto out_unknown;
1162 }
1163 }
1164
1165 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1166 result = FMT_5_9_9_9_SHAREDEXP;
1167 goto out_word4;
1168 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1169 result = FMT_10_11_11_FLOAT;
1170 goto out_word4;
1171 }
1172
1173
1174 for (i = 0; i < desc->nr_channels; i++) {
1175 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1176 word4 |= sign_bit[i];
1177 }
1178 }
1179
1180 /* R8G8Bx_SNORM - TODO CxV8U8 */
1181
1182 /* See whether the components are of the same size. */
1183 for (i = 1; i < desc->nr_channels; i++) {
1184 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1185 }
1186
1187 /* Non-uniform formats. */
1188 if (!uniform) {
1189 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1190 desc->channel[0].pure_integer)
1191 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1192 switch(desc->nr_channels) {
1193 case 3:
1194 if (desc->channel[0].size == 5 &&
1195 desc->channel[1].size == 6 &&
1196 desc->channel[2].size == 5) {
1197 result = FMT_5_6_5;
1198 goto out_word4;
1199 }
1200 goto out_unknown;
1201 case 4:
1202 if (desc->channel[0].size == 5 &&
1203 desc->channel[1].size == 5 &&
1204 desc->channel[2].size == 5 &&
1205 desc->channel[3].size == 1) {
1206 result = FMT_1_5_5_5;
1207 goto out_word4;
1208 }
1209 if (desc->channel[0].size == 10 &&
1210 desc->channel[1].size == 10 &&
1211 desc->channel[2].size == 10 &&
1212 desc->channel[3].size == 2) {
1213 result = FMT_2_10_10_10;
1214 goto out_word4;
1215 }
1216 goto out_unknown;
1217 }
1218 goto out_unknown;
1219 }
1220
1221 /* Find the first non-VOID channel. */
1222 for (i = 0; i < 4; i++) {
1223 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1224 break;
1225 }
1226 }
1227
1228 if (i == 4)
1229 goto out_unknown;
1230
1231 /* uniform formats */
1232 switch (desc->channel[i].type) {
1233 case UTIL_FORMAT_TYPE_UNSIGNED:
1234 case UTIL_FORMAT_TYPE_SIGNED:
1235 #if 0
1236 if (!desc->channel[i].normalized &&
1237 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1238 goto out_unknown;
1239 }
1240 #endif
1241 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1242 desc->channel[i].pure_integer)
1243 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1244
1245 switch (desc->channel[i].size) {
1246 case 4:
1247 switch (desc->nr_channels) {
1248 case 2:
1249 result = FMT_4_4;
1250 goto out_word4;
1251 case 4:
1252 result = FMT_4_4_4_4;
1253 goto out_word4;
1254 }
1255 goto out_unknown;
1256 case 8:
1257 switch (desc->nr_channels) {
1258 case 1:
1259 result = FMT_8;
1260 goto out_word4;
1261 case 2:
1262 result = FMT_8_8;
1263 goto out_word4;
1264 case 4:
1265 result = FMT_8_8_8_8;
1266 is_srgb_valid = TRUE;
1267 goto out_word4;
1268 }
1269 goto out_unknown;
1270 case 16:
1271 switch (desc->nr_channels) {
1272 case 1:
1273 result = FMT_16;
1274 goto out_word4;
1275 case 2:
1276 result = FMT_16_16;
1277 goto out_word4;
1278 case 4:
1279 result = FMT_16_16_16_16;
1280 goto out_word4;
1281 }
1282 goto out_unknown;
1283 case 32:
1284 switch (desc->nr_channels) {
1285 case 1:
1286 result = FMT_32;
1287 goto out_word4;
1288 case 2:
1289 result = FMT_32_32;
1290 goto out_word4;
1291 case 4:
1292 result = FMT_32_32_32_32;
1293 goto out_word4;
1294 }
1295 }
1296 goto out_unknown;
1297
1298 case UTIL_FORMAT_TYPE_FLOAT:
1299 switch (desc->channel[i].size) {
1300 case 16:
1301 switch (desc->nr_channels) {
1302 case 1:
1303 result = FMT_16_FLOAT;
1304 goto out_word4;
1305 case 2:
1306 result = FMT_16_16_FLOAT;
1307 goto out_word4;
1308 case 4:
1309 result = FMT_16_16_16_16_FLOAT;
1310 goto out_word4;
1311 }
1312 goto out_unknown;
1313 case 32:
1314 switch (desc->nr_channels) {
1315 case 1:
1316 result = FMT_32_FLOAT;
1317 goto out_word4;
1318 case 2:
1319 result = FMT_32_32_FLOAT;
1320 goto out_word4;
1321 case 4:
1322 result = FMT_32_32_32_32_FLOAT;
1323 goto out_word4;
1324 }
1325 }
1326 goto out_unknown;
1327 }
1328
1329 out_word4:
1330
1331 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1332 return ~0;
1333 if (word4_p)
1334 *word4_p = word4;
1335 if (yuv_format_p)
1336 *yuv_format_p = yuv_format;
1337 return result;
1338 out_unknown:
1339 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1340 return ~0;
1341 }