src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_format_s3tc.h>
  31 #include <util/u_math.h>
  32 #include <util/u_inlines.h>
  33 #include <util/u_memory.h>
  34 #include "state_tracker/drm_driver.h"
  35 #include "pipebuffer/pb_buffer.h"
  36 #include "r600_pipe.h"
  37 #include "r600_resource.h"
  38 #include "r600_state_inlines.h"
  39 #include "r600d.h"
  40 #include "r600_formats.h"
  41
  42 /* Copy from a full GPU texture to a transfer's staging one. */
  43 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  44 {
  45         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  46         struct pipe_resource *texture = transfer->resource;
  47
  48         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  49                                 0, 0, 0, 0, texture, transfer->level,
  50                                 &transfer->box);
  51 }
  52
  53
  54 /* Copy from a transfer's staging texture to a full GPU one. */
  55 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  56 {
  57         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  58         struct pipe_resource *texture = transfer->resource;
  59         struct pipe_box sbox;
  60
  61         sbox.x = sbox.y = sbox.z = 0;
  62         sbox.width = transfer->box.width;
  63         sbox.height = transfer->box.height;
  64         /* XXX that might be wrong */
  65         sbox.depth = 1;
  66         ctx->resource_copy_region(ctx, texture, transfer->level,
  67                                   transfer->box.x, transfer->box.y, transfer->box.z,
  68                                   rtransfer->staging_texture,
  69                                   0, &sbox);
  70
  71         ctx->flush(ctx, 0, NULL);
  72 }
  73
  74 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  75                                         unsigned level, unsigned layer)
  76 {
  77         unsigned offset = rtex->offset[level];
  78
  79         switch (rtex->resource.b.b.b.target) {
  80         case PIPE_TEXTURE_3D:
  81         case PIPE_TEXTURE_CUBE:
  82                 return offset + layer * rtex->layer_size[level];
  83         default:
  84                 assert(layer == 0);
  85                 return offset;
  86         }
  87 }
  88
  89 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
  90                                          enum pipe_format format,
  91                                          unsigned array_mode)
  92 {
  93         struct r600_screen* rscreen = (struct r600_screen *)screen;
  94         unsigned pixsize = util_format_get_blocksize(format);
  95         int p_align;
  96
  97         switch(array_mode) {
  98         case V_038000_ARRAY_1D_TILED_THIN1:
  99                 p_align = MAX2(8,
 100                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
 101                 break;
 102         case V_038000_ARRAY_2D_TILED_THIN1:
 103                 p_align = MAX2(rscreen->tiling_info->num_banks,
 104                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 105                                 rscreen->tiling_info->num_banks)) * 8;
 106                 break;
 107         case V_038000_ARRAY_LINEAR_ALIGNED:
 108                 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
 109                 break;
 110         case V_038000_ARRAY_LINEAR_GENERAL:
 111         default:
 112                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 113                 break;
 114         }
 115         return p_align;
 116 }
 117
 118 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 119                                           unsigned array_mode)
 120 {
 121         struct r600_screen* rscreen = (struct r600_screen *)screen;
 122         int h_align;
 123
 124         switch (array_mode) {
 125         case V_038000_ARRAY_2D_TILED_THIN1:
 126                 h_align = rscreen->tiling_info->num_channels * 8;
 127                 break;
 128         case V_038000_ARRAY_1D_TILED_THIN1:
 129         case V_038000_ARRAY_LINEAR_ALIGNED:
 130                 h_align = 8;
 131                 break;
 132         case V_038000_ARRAY_LINEAR_GENERAL:
 133         default:
 134                 h_align = 1;
 135                 break;
 136         }
 137         return h_align;
 138 }
 139
 140 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 141                                         enum pipe_format format,
 142                                         unsigned array_mode)
 143 {
 144         struct r600_screen* rscreen = (struct r600_screen *)screen;
 145         unsigned pixsize = util_format_get_blocksize(format);
 146         int p_align = r600_get_block_alignment(screen, format, array_mode);
 147         int h_align = r600_get_height_alignment(screen, array_mode);
 148         int b_align;
 149
 150         switch (array_mode) {
 151         case V_038000_ARRAY_2D_TILED_THIN1:
 152                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 153                                p_align * pixsize * h_align);
 154                 break;
 155         case V_038000_ARRAY_1D_TILED_THIN1:
 156         case V_038000_ARRAY_LINEAR_ALIGNED:
 157         case V_038000_ARRAY_LINEAR_GENERAL:
 158         default:
 159                 b_align = rscreen->tiling_info->group_bytes;
 160                 break;
 161         }
 162         return b_align;
 163 }
 164
 165 static unsigned mip_minify(unsigned size, unsigned level)
 166 {
 167         unsigned val;
 168         val = u_minify(size, level);
 169         if (level > 0)
 170                 val = util_next_power_of_two(val);
 171         return val;
 172 }
 173
 174 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
 175                                           struct r600_resource_texture *rtex,
 176                                           unsigned level)
 177 {
 178         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 179         unsigned nblocksx, block_align, width;
 180         unsigned blocksize = util_format_get_blocksize(ptex->format);
 181
 182         if (rtex->pitch_override)
 183                 return rtex->pitch_override / blocksize;
 184
 185         width = mip_minify(ptex->width0, level);
 186         nblocksx = util_format_get_nblocksx(ptex->format, width);
 187
 188         block_align = r600_get_block_alignment(screen, ptex->format,
 189                                               rtex->array_mode[level]);
 190         nblocksx = align(nblocksx, block_align);
 191         return nblocksx;
 192 }
 193
 194 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 195                                           struct r600_resource_texture *rtex,
 196                                           unsigned level)
 197 {
 198         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 199         unsigned height, tile_height;
 200
 201         height = mip_minify(ptex->height0, level);
 202         height = util_format_get_nblocksy(ptex->format, height);
 203         tile_height = r600_get_height_alignment(screen,
 204                                                 rtex->array_mode[level]);
 205         height = align(height, tile_height);
 206         return height;
 207 }
 208
 209 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 210                                         struct r600_resource_texture *rtex,
 211                                         unsigned level, unsigned array_mode)
 212 {
 213         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 214
 215         switch (array_mode) {
 216         case V_0280A0_ARRAY_LINEAR_GENERAL:
 217         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 218         case V_0280A0_ARRAY_1D_TILED_THIN1:
 219         default:
 220                 rtex->array_mode[level] = array_mode;
 221                 break;
 222         case V_0280A0_ARRAY_2D_TILED_THIN1:
 223         {
 224                 unsigned w, h, tile_height, tile_width;
 225
 226                 tile_height = r600_get_height_alignment(screen, array_mode);
 227                 tile_width = r600_get_block_alignment(screen, ptex->format, array_mode);
 228
 229                 w = mip_minify(ptex->width0, level);
 230                 h = mip_minify(ptex->height0, level);
 231                 if (w < tile_width || h < tile_height)
 232                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 233                 else
 234                         rtex->array_mode[level] = array_mode;
 235         }
 236         break;
 237         }
 238 }
 239
 240 static void r600_setup_miptree(struct pipe_screen *screen,
 241                                struct r600_resource_texture *rtex,
 242                                unsigned array_mode)
 243 {
 244         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 245         struct radeon *radeon = (struct radeon *)screen->winsys;
 246         enum chip_class chipc = r600_get_family_class(radeon);
 247         unsigned size, layer_size, i, offset;
 248         unsigned nblocksx, nblocksy;
 249
 250         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 251                 unsigned blocksize = util_format_get_blocksize(ptex->format);
 252
 253                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 254
 255                 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
 256                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 257
 258                 layer_size = nblocksx * nblocksy * blocksize;
 259                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 260                         if (chipc >= R700)
 261                                 size = layer_size * 8;
 262                         else
 263                                 size = layer_size * 6;
 264                 }
 265                 else
 266                         size = layer_size * u_minify(ptex->depth0, i);
 267                 /* align base image and start of miptree */
 268                 if ((i == 0) || (i == 1))
 269                         offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
 270                 rtex->offset[i] = offset;
 271                 rtex->layer_size[i] = layer_size;
 272                 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
 273                 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
 274
 275                 offset += size;
 276         }
 277         rtex->size = offset;
 278 }
 279
 280 /* Figure out whether u_blitter will fallback to a transfer operation.
 281  * If so, don't use a staging resource.
 282  */
 283 static boolean permit_hardware_blit(struct pipe_screen *screen,
 284                                         const struct pipe_resource *res)
 285 {
 286         unsigned bind;
 287
 288         if (util_format_is_depth_or_stencil(res->format))
 289                 bind = PIPE_BIND_DEPTH_STENCIL;
 290         else
 291                 bind = PIPE_BIND_RENDER_TARGET;
 292
 293         /* hackaround for S3TC */
 294         if (util_format_is_s3tc(res->format))
 295                 return TRUE;
 296
 297         if (!screen->is_format_supported(screen,
 298                                 res->format,
 299                                 res->target,
 300                                 res->nr_samples,
 301                                 bind, 0))
 302                 return FALSE;
 303
 304         if (!screen->is_format_supported(screen,
 305                                 res->format,
 306                                 res->target,
 307                                 res->nr_samples,
 308                                 PIPE_BIND_SAMPLER_VIEW, 0))
 309                 return FALSE;
 310
 311         return TRUE;
 312 }
 313
 314 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 315                                         struct pipe_resource *ptex,
 316                                         struct winsys_handle *whandle)
 317 {
 318         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 319         struct r600_resource *resource = &rtex->resource;
 320         struct radeon *radeon = (struct radeon *)screen->winsys;
 321
 322         return r600_bo_get_winsys_handle(radeon, resource->bo,
 323                         rtex->pitch_in_bytes[0], whandle);
 324 }
 325
 326 static void r600_texture_destroy(struct pipe_screen *screen,
 327                                  struct pipe_resource *ptex)
 328 {
 329         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 330         struct r600_resource *resource = &rtex->resource;
 331         struct radeon *radeon = (struct radeon *)screen->winsys;
 332
 333         if (rtex->flushed_depth_texture)
 334                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 335
 336         if (resource->bo) {
 337                 r600_bo_reference(radeon, &resource->bo, NULL);
 338         }
 339         FREE(rtex);
 340 }
 341
 342 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 343                                                 struct pipe_resource *texture,
 344                                                 unsigned level, int layer)
 345 {
 346         /* FIXME */
 347         return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 348 }
 349
 350 static const struct u_resource_vtbl r600_texture_vtbl =
 351 {
 352         r600_texture_get_handle,        /* get_handle */
 353         r600_texture_destroy,           /* resource_destroy */
 354         r600_texture_is_referenced,     /* is_resource_referenced */
 355         r600_texture_get_transfer,      /* get_transfer */
 356         r600_texture_transfer_destroy,  /* transfer_destroy */
 357         r600_texture_transfer_map,      /* transfer_map */
 358         u_default_transfer_flush_region,/* transfer_flush_region */
 359         r600_texture_transfer_unmap,    /* transfer_unmap */
 360         u_default_transfer_inline_write /* transfer_inline_write */
 361 };
 362
 363 static struct r600_resource_texture *
 364 r600_texture_create_object(struct pipe_screen *screen,
 365                            const struct pipe_resource *base,
 366                            unsigned array_mode,
 367                            unsigned pitch_in_bytes_override,
 368                            unsigned max_buffer_size,
 369                            struct r600_bo *bo)
 370 {
 371         struct r600_resource_texture *rtex;
 372         struct r600_resource *resource;
 373         struct radeon *radeon = (struct radeon *)screen->winsys;
 374
 375         rtex = CALLOC_STRUCT(r600_resource_texture);
 376         if (rtex == NULL)
 377                 return NULL;
 378
 379         resource = &rtex->resource;
 380         resource->b.b.b = *base;
 381         resource->b.b.vtbl = &r600_texture_vtbl;
 382         pipe_reference_init(&resource->b.b.b.reference, 1);
 383         resource->b.b.b.screen = screen;
 384         resource->bo = bo;
 385         rtex->pitch_override = pitch_in_bytes_override;
 386         /* only mark depth textures the HW can hit as depth textures */
 387         if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
 388                 rtex->depth = 1;
 389
 390         r600_setup_miptree(screen, rtex, array_mode);
 391
 392         resource->size = rtex->size;
 393
 394         if (!resource->bo) {
 395                 struct pipe_resource *ptex = &rtex->resource.b.b.b;
 396                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 397
 398                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 399                 if (!resource->bo) {
 400                         FREE(rtex);
 401                         return NULL;
 402                 }
 403         }
 404         return rtex;
 405 }
 406
 407 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 408                                                 const struct pipe_resource *templ)
 409 {
 410         unsigned array_mode = 0;
 411         static int force_tiling = -1;
 412
 413         /* Would like some magic "get_bool_option_once" routine.
 414          */
 415         if (force_tiling == -1)
 416                 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
 417
 418         if (force_tiling && permit_hardware_blit(screen, templ)) {
 419                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 420                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 421                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 422                 }
 423         }
 424
 425         if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 426             util_format_is_s3tc(templ->format))
 427                 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
 428
 429         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 430                                                                   0, 0, NULL);
 431
 432 }
 433
 434 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 435                                                 struct pipe_resource *texture,
 436                                                 const struct pipe_surface *surf_tmpl)
 437 {
 438         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 439         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 440         unsigned level = surf_tmpl->u.tex.level;
 441
 442         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 443         if (surface == NULL)
 444                 return NULL;
 445         /* XXX no offset */
 446 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 447         pipe_reference_init(&surface->base.reference, 1);
 448         pipe_resource_reference(&surface->base.texture, texture);
 449         surface->base.context = pipe;
 450         surface->base.format = surf_tmpl->format;
 451         surface->base.width = mip_minify(texture->width0, level);
 452         surface->base.height = mip_minify(texture->height0, level);
 453         surface->base.usage = surf_tmpl->usage;
 454         surface->base.texture = texture;
 455         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 456         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 457         surface->base.u.tex.level = level;
 458
 459         surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
 460                                                             rtex, level);
 461         return &surface->base;
 462 }
 463
 464 static void r600_surface_destroy(struct pipe_context *pipe,
 465                                  struct pipe_surface *surface)
 466 {
 467         pipe_resource_reference(&surface->texture, NULL);
 468         FREE(surface);
 469 }
 470
 471
 472 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 473                                                const struct pipe_resource *templ,
 474                                                struct winsys_handle *whandle)
 475 {
 476         struct radeon *rw = (struct radeon*)screen->winsys;
 477         struct r600_bo *bo = NULL;
 478         unsigned array_mode = 0;
 479
 480         /* Support only 2D textures without mipmaps */
 481         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 482               templ->depth0 != 1 || templ->last_level != 0)
 483                 return NULL;
 484
 485         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 486         if (bo == NULL) {
 487                 return NULL;
 488         }
 489
 490         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 491                                                                   whandle->stride,
 492                                                                   0,
 493                                                                   bo);
 494 }
 495
 496 int r600_texture_depth_flush(struct pipe_context *ctx,
 497                              struct pipe_resource *texture, boolean just_create)
 498 {
 499         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 500         struct pipe_resource resource;
 501
 502         if (rtex->flushed_depth_texture)
 503                 goto out;
 504
 505         resource.target = PIPE_TEXTURE_2D;
 506         resource.format = texture->format;
 507         resource.width0 = texture->width0;
 508         resource.height0 = texture->height0;
 509         resource.depth0 = 1;
 510         resource.last_level = texture->last_level;
 511         resource.nr_samples = 0;
 512         resource.usage = PIPE_USAGE_DYNAMIC;
 513         resource.bind = 0;
 514         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 515
 516         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 517
 518         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 519         if (rtex->flushed_depth_texture == NULL) {
 520                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 521                 return -ENOMEM;
 522         }
 523
 524         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 525 out:
 526         if (just_create)
 527                 return 0;
 528
 529         /* XXX: only do this if the depth texture has actually changed:
 530          */
 531         r600_blit_uncompress_depth(ctx, rtex);
 532         return 0;
 533 }
 534
 535 /* Needs adjustment for pixelformat:
 536  */
 537 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 538 {
 539         return box->width * box->depth * box->height;
 540 };
 541
 542 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 543                                                 struct pipe_resource *texture,
 544                                                 unsigned level,
 545                                                 unsigned usage,
 546                                                 const struct pipe_box *box)
 547 {
 548         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 549         struct pipe_resource resource;
 550         struct r600_transfer *trans;
 551         int r;
 552         boolean use_staging_texture = FALSE;
 553
 554         /* We cannot map a tiled texture directly because the data is
 555          * in a different order, therefore we do detiling using a blit.
 556          *
 557          * Also, use a temporary in GTT memory for read transfers, as
 558          * the CPU is much happier reading out of cached system memory
 559          * than uncached VRAM.
 560          */
 561         if (R600_TEX_IS_TILED(rtex, level))
 562                 use_staging_texture = TRUE;
 563
 564         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 565                 use_staging_texture = TRUE;
 566
 567         /* XXX: Use a staging texture for uploads if the underlying BO
 568          * is busy.  No interface for checking that currently? so do
 569          * it eagerly whenever the transfer doesn't require a readback
 570          * and might block.
 571          */
 572         if ((usage & PIPE_TRANSFER_WRITE) &&
 573                         !(usage & (PIPE_TRANSFER_READ |
 574                                         PIPE_TRANSFER_DONTBLOCK |
 575                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 576                 use_staging_texture = TRUE;
 577
 578         if (!permit_hardware_blit(ctx->screen, texture) ||
 579                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 580                 use_staging_texture = FALSE;
 581
 582         trans = CALLOC_STRUCT(r600_transfer);
 583         if (trans == NULL)
 584                 return NULL;
 585         pipe_resource_reference(&trans->transfer.resource, texture);
 586         trans->transfer.level = level;
 587         trans->transfer.usage = usage;
 588         trans->transfer.box = *box;
 589         if (rtex->depth) {
 590                 /* XXX: only readback the rectangle which is being mapped?
 591                 */
 592                 /* XXX: when discard is true, no need to read back from depth texture
 593                 */
 594                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 595                 if (r < 0) {
 596                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 597                         pipe_resource_reference(&trans->transfer.resource, NULL);
 598                         FREE(trans);
 599                         return NULL;
 600                 }
 601                 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
 602                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 603                 return &trans->transfer;
 604         } else if (use_staging_texture) {
 605                 resource.target = PIPE_TEXTURE_2D;
 606                 resource.format = texture->format;
 607                 resource.width0 = box->width;
 608                 resource.height0 = box->height;
 609                 resource.depth0 = 1;
 610                 resource.array_size = 1;
 611                 resource.last_level = 0;
 612                 resource.nr_samples = 0;
 613                 resource.usage = PIPE_USAGE_STAGING;
 614                 resource.bind = 0;
 615                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 616                 /* For texture reading, the temporary (detiled) texture is used as
 617                  * a render target when blitting from a tiled texture. */
 618                 if (usage & PIPE_TRANSFER_READ) {
 619                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 620                 }
 621                 /* For texture writing, the temporary texture is used as a sampler
 622                  * when blitting into a tiled texture. */
 623                 if (usage & PIPE_TRANSFER_WRITE) {
 624                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 625                 }
 626                 /* Create the temporary texture. */
 627                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 628                 if (trans->staging_texture == NULL) {
 629                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 630                         pipe_resource_reference(&trans->transfer.resource, NULL);
 631                         FREE(trans);
 632                         return NULL;
 633                 }
 634
 635                 trans->transfer.stride =
 636                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 637                 if (usage & PIPE_TRANSFER_READ) {
 638                         r600_copy_to_staging_texture(ctx, trans);
 639                         /* Always referenced in the blit. */
 640                         ctx->flush(ctx, 0, NULL);
 641                 }
 642                 return &trans->transfer;
 643         }
 644         trans->transfer.stride = rtex->pitch_in_bytes[level];
 645         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 646         return &trans->transfer;
 647 }
 648
 649 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 650                                    struct pipe_transfer *transfer)
 651 {
 652         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 653         struct pipe_resource *texture = transfer->resource;
 654         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 655
 656         if (rtransfer->staging_texture) {
 657                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 658                         r600_copy_from_staging_texture(ctx, rtransfer);
 659                 }
 660                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 661         }
 662
 663         if (rtex->depth && !rtex->is_flushing_texture) {
 664                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 665                         r600_blit_push_depth(ctx, rtex);
 666         }
 667
 668         pipe_resource_reference(&transfer->resource, NULL);
 669         FREE(transfer);
 670 }
 671
 672 void* r600_texture_transfer_map(struct pipe_context *ctx,
 673                                 struct pipe_transfer* transfer)
 674 {
 675         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 676         struct r600_bo *bo;
 677         enum pipe_format format = transfer->resource->format;
 678         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 679         unsigned offset = 0;
 680         unsigned usage = 0;
 681         char *map;
 682
 683         if (rtransfer->staging_texture) {
 684                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 685         } else {
 686                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 687
 688                 if (rtex->flushed_depth_texture)
 689                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 690                 else
 691                         bo = ((struct r600_resource *)transfer->resource)->bo;
 692
 693                 offset = rtransfer->offset +
 694                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 695                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 696         }
 697
 698         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 699                 usage |= PB_USAGE_CPU_WRITE;
 700
 701                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 702                 }
 703
 704                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 705                 }
 706         }
 707
 708         if (transfer->usage & PIPE_TRANSFER_READ) {
 709                 usage |= PB_USAGE_CPU_READ;
 710         }
 711
 712         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 713                 usage |= PB_USAGE_DONTBLOCK;
 714         }
 715
 716         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 717                 usage |= PB_USAGE_UNSYNCHRONIZED;
 718         }
 719
 720         map = r600_bo_map(radeon, bo, usage, ctx);
 721         if (!map) {
 722                 return NULL;
 723         }
 724
 725         return map + offset;
 726 }
 727
 728 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 729                                  struct pipe_transfer* transfer)
 730 {
 731         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 732         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 733         struct r600_bo *bo;
 734
 735         if (rtransfer->staging_texture) {
 736                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 737         } else {
 738                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 739
 740                 if (rtex->flushed_depth_texture) {
 741                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 742                 } else {
 743                         bo = ((struct r600_resource *)transfer->resource)->bo;
 744                 }
 745         }
 746         r600_bo_unmap(radeon, bo);
 747 }
 748
 749 void r600_init_surface_functions(struct r600_pipe_context *r600)
 750 {
 751         r600->context.create_surface = r600_create_surface;
 752         r600->context.surface_destroy = r600_surface_destroy;
 753 }
 754
 755 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 756                 const unsigned char *swizzle_view)
 757 {
 758         unsigned i;
 759         unsigned char swizzle[4];
 760         unsigned result = 0;
 761         const uint32_t swizzle_shift[4] = {
 762                 16, 19, 22, 25,
 763         };
 764         const uint32_t swizzle_bit[4] = {
 765                 0, 1, 2, 3,
 766         };
 767
 768         if (swizzle_view) {
 769                 /* Combine two sets of swizzles. */
 770                 for (i = 0; i < 4; i++) {
 771                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 772                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 773                 }
 774         } else {
 775                 memcpy(swizzle, swizzle_format, 4);
 776         }
 777
 778         /* Get swizzle. */
 779         for (i = 0; i < 4; i++) {
 780                 switch (swizzle[i]) {
 781                 case UTIL_FORMAT_SWIZZLE_Y:
 782                         result |= swizzle_bit[1] << swizzle_shift[i];
 783                         break;
 784                 case UTIL_FORMAT_SWIZZLE_Z:
 785                         result |= swizzle_bit[2] << swizzle_shift[i];
 786                         break;
 787                 case UTIL_FORMAT_SWIZZLE_W:
 788                         result |= swizzle_bit[3] << swizzle_shift[i];
 789                         break;
 790                 case UTIL_FORMAT_SWIZZLE_0:
 791                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 792                         break;
 793                 case UTIL_FORMAT_SWIZZLE_1:
 794                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 795                         break;
 796                 default: /* UTIL_FORMAT_SWIZZLE_X */
 797                         result |= swizzle_bit[0] << swizzle_shift[i];
 798                 }
 799         }
 800         return result;
 801 }
 802
 803 /* texture format translate */
 804 uint32_t r600_translate_texformat(enum pipe_format format,
 805                                   const unsigned char *swizzle_view,
 806                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 807 {
 808         uint32_t result = 0, word4 = 0, yuv_format = 0;
 809         const struct util_format_description *desc;
 810         boolean uniform = TRUE;
 811         int i;
 812         const uint32_t sign_bit[4] = {
 813                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 814                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 815                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 816                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 817         };
 818         desc = util_format_description(format);
 819
 820         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 821
 822         /* Colorspace (return non-RGB formats directly). */
 823         switch (desc->colorspace) {
 824                 /* Depth stencil formats */
 825         case UTIL_FORMAT_COLORSPACE_ZS:
 826                 switch (format) {
 827                 case PIPE_FORMAT_Z16_UNORM:
 828                         result = FMT_16;
 829                         goto out_word4;
 830                 case PIPE_FORMAT_X24S8_USCALED:
 831                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 832                 case PIPE_FORMAT_Z24X8_UNORM:
 833                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 834                         result = FMT_8_24;
 835                         goto out_word4;
 836                 case PIPE_FORMAT_S8X24_USCALED:
 837                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 838                 case PIPE_FORMAT_X8Z24_UNORM:
 839                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 840                         result = FMT_24_8;
 841                         goto out_word4;
 842                 case PIPE_FORMAT_S8_USCALED:
 843                         result = FMT_8;
 844                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 845                         goto out_word4;
 846                 default:
 847                         goto out_unknown;
 848                 }
 849
 850         case UTIL_FORMAT_COLORSPACE_YUV:
 851                 yuv_format |= (1 << 30);
 852                 switch (format) {
 853                 case PIPE_FORMAT_UYVY:
 854                 case PIPE_FORMAT_YUYV:
 855                 default:
 856                         break;
 857                 }
 858                 goto out_unknown; /* TODO */
 859
 860         case UTIL_FORMAT_COLORSPACE_SRGB:
 861                 word4 |= S_038010_FORCE_DEGAMMA(1);
 862                 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
 863                         goto out_unknown; /* fails for some reason - TODO */
 864                 break;
 865
 866         default:
 867                 break;
 868         }
 869
 870         /* S3TC formats. TODO */
 871         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 872                 static int r600_enable_s3tc = -1;
 873
 874                 if (r600_enable_s3tc == -1)
 875                         r600_enable_s3tc =
 876                                 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 877
 878                 if (!r600_enable_s3tc)
 879                         goto out_unknown;
 880
 881                 if (!util_format_s3tc_enabled) {
 882                         goto out_unknown;
 883                 }
 884
 885                 switch (format) {
 886                 case PIPE_FORMAT_DXT1_RGB:
 887                 case PIPE_FORMAT_DXT1_RGBA:
 888                         result = FMT_BC1;
 889                         goto out_word4;
 890                 case PIPE_FORMAT_DXT3_RGBA:
 891                         result = FMT_BC2;
 892                         goto out_word4;
 893                 case PIPE_FORMAT_DXT5_RGBA:
 894                         result = FMT_BC3;
 895                         goto out_word4;
 896                 default:
 897                         goto out_unknown;
 898                 }
 899         }
 900
 901
 902         for (i = 0; i < desc->nr_channels; i++) {
 903                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 904                         word4 |= sign_bit[i];
 905                 }
 906         }
 907
 908         /* R8G8Bx_SNORM - TODO CxV8U8 */
 909
 910         /* RGTC - TODO */
 911
 912         /* See whether the components are of the same size. */
 913         for (i = 1; i < desc->nr_channels; i++) {
 914                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 915         }
 916
 917         /* Non-uniform formats. */
 918         if (!uniform) {
 919                 switch(desc->nr_channels) {
 920                 case 3:
 921                         if (desc->channel[0].size == 5 &&
 922                             desc->channel[1].size == 6 &&
 923                             desc->channel[2].size == 5) {
 924                                 result = FMT_5_6_5;
 925                                 goto out_word4;
 926                         }
 927                         goto out_unknown;
 928                 case 4:
 929                         if (desc->channel[0].size == 5 &&
 930                             desc->channel[1].size == 5 &&
 931                             desc->channel[2].size == 5 &&
 932                             desc->channel[3].size == 1) {
 933                                 result = FMT_1_5_5_5;
 934                                 goto out_word4;
 935                         }
 936                         if (desc->channel[0].size == 10 &&
 937                             desc->channel[1].size == 10 &&
 938                             desc->channel[2].size == 10 &&
 939                             desc->channel[3].size == 2) {
 940                                 result = FMT_2_10_10_10;
 941                                 goto out_word4;
 942                         }
 943                         goto out_unknown;
 944                 }
 945                 goto out_unknown;
 946         }
 947
 948         /* Find the first non-VOID channel. */
 949         for (i = 0; i < 4; i++) {
 950                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 951                         break;
 952                 }
 953         }
 954
 955         if (i == 4)
 956                 goto out_unknown;
 957
 958         /* uniform formats */
 959         switch (desc->channel[i].type) {
 960         case UTIL_FORMAT_TYPE_UNSIGNED:
 961         case UTIL_FORMAT_TYPE_SIGNED:
 962                 if (!desc->channel[i].normalized &&
 963                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 964                         goto out_unknown;
 965                 }
 966
 967                 switch (desc->channel[i].size) {
 968                 case 4:
 969                         switch (desc->nr_channels) {
 970                         case 2:
 971                                 result = FMT_4_4;
 972                                 goto out_word4;
 973                         case 4:
 974                                 result = FMT_4_4_4_4;
 975                                 goto out_word4;
 976                         }
 977                         goto out_unknown;
 978                 case 8:
 979                         switch (desc->nr_channels) {
 980                         case 1:
 981                                 result = FMT_8;
 982                                 goto out_word4;
 983                         case 2:
 984                                 result = FMT_8_8;
 985                                 goto out_word4;
 986                         case 4:
 987                                 result = FMT_8_8_8_8;
 988                                 goto out_word4;
 989                         }
 990                         goto out_unknown;
 991                 case 16:
 992                         switch (desc->nr_channels) {
 993                         case 1:
 994                                 result = FMT_16;
 995                                 goto out_word4;
 996                         case 2:
 997                                 result = FMT_16_16;
 998                                 goto out_word4;
 999                         case 4:
1000                                 result = FMT_16_16_16_16;
1001                                 goto out_word4;
1002                         }
1003                         goto out_unknown;
1004                 case 32:
1005                         switch (desc->nr_channels) {
1006                         case 1:
1007                                 result = FMT_32;
1008                                 goto out_word4;
1009                         case 2:
1010                                 result = FMT_32_32;
1011                                 goto out_word4;
1012                         case 4:
1013                                 result = FMT_32_32_32_32;
1014                                 goto out_word4;
1015                         }
1016                 }
1017                 goto out_unknown;
1018
1019         case UTIL_FORMAT_TYPE_FLOAT:
1020                 switch (desc->channel[i].size) {
1021                 case 16:
1022                         switch (desc->nr_channels) {
1023                         case 1:
1024                                 result = FMT_16_FLOAT;
1025                                 goto out_word4;
1026                         case 2:
1027                                 result = FMT_16_16_FLOAT;
1028                                 goto out_word4;
1029                         case 4:
1030                                 result = FMT_16_16_16_16_FLOAT;
1031                                 goto out_word4;
1032                         }
1033                         goto out_unknown;
1034                 case 32:
1035                         switch (desc->nr_channels) {
1036                         case 1:
1037                                 result = FMT_32_FLOAT;
1038                                 goto out_word4;
1039                         case 2:
1040                                 result = FMT_32_32_FLOAT;
1041                                 goto out_word4;
1042                         case 4:
1043                                 result = FMT_32_32_32_32_FLOAT;
1044                                 goto out_word4;
1045                         }
1046                 }
1047
1048         }
1049 out_word4:
1050         if (word4_p)
1051                 *word4_p = word4;
1052         if (yuv_format_p)
1053                 *yuv_format_p = yuv_format;
1054         return result;
1055 out_unknown:
1056 //      R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1057         return ~0;
1058 }