2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_math.h>
31 #include <util/u_inlines.h>
32 #include <util/u_memory.h>
33 #include "state_tracker/drm_driver.h"
34 #include "r600_pipe.h"
35 #include "r600_resource.h"
36 #include "r600_state_inlines.h"
38 #include "r600_formats.h"
40 extern struct u_resource_vtbl r600_texture_vtbl
;
42 /* Copy from a tiled texture to a detiled one. */
43 static void r600_copy_from_tiled_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
45 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
46 struct pipe_resource
*texture
= transfer
->resource
;
47 struct pipe_subresource subdst
;
51 ctx
->resource_copy_region(ctx
, rtransfer
->linear_texture
,
52 subdst
, 0, 0, 0, texture
, transfer
->sr
,
53 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
54 transfer
->box
.width
, transfer
->box
.height
);
58 /* Copy from a detiled texture to a tiled one. */
59 static void r600_copy_into_tiled_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
61 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
62 struct pipe_resource
*texture
= transfer
->resource
;
63 struct pipe_subresource subsrc
;
67 ctx
->resource_copy_region(ctx
, texture
, transfer
->sr
,
68 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
69 rtransfer
->linear_texture
, subsrc
,
71 transfer
->box
.width
, transfer
->box
.height
);
73 ctx
->flush(ctx
, 0, NULL
);
76 static unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
77 unsigned level
, unsigned zslice
,
80 unsigned offset
= rtex
->offset
[level
];
82 switch (rtex
->resource
.base
.b
.target
) {
85 return offset
+ zslice
* rtex
->layer_size
[level
];
86 case PIPE_TEXTURE_CUBE
:
88 return offset
+ face
* rtex
->layer_size
[level
];
90 assert(zslice
== 0 && face
== 0);
95 static unsigned r600_get_pixel_alignment(struct pipe_screen
*screen
,
96 enum pipe_format format
,
102 static unsigned r600_get_height_alignment(struct pipe_screen
*screen
,
108 static unsigned mip_minify(unsigned size
, unsigned level
)
111 val
= u_minify(size
, level
);
113 val
= util_next_power_of_two(val
);
117 static unsigned r600_texture_get_stride(struct pipe_screen
*screen
,
118 struct r600_resource_texture
*rtex
,
121 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
122 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
123 enum chip_class chipc
= r600_get_family_class(radeon
);
124 unsigned width
, stride
, tile_width
;
126 if (rtex
->pitch_override
)
127 return rtex
->pitch_override
;
129 width
= mip_minify(ptex
->width0
, level
);
130 if (util_format_is_plain(ptex
->format
)) {
131 tile_width
= r600_get_pixel_alignment(screen
, ptex
->format
,
132 rtex
->array_mode
[level
]);
133 width
= align(width
, tile_width
);
135 stride
= util_format_get_stride(ptex
->format
, width
);
136 if (chipc
== EVERGREEN
)
137 stride
= align(stride
, 512);
139 stride
= align(stride
, 256);
143 static unsigned r600_texture_get_nblocksy(struct pipe_screen
*screen
,
144 struct r600_resource_texture
*rtex
,
147 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
148 unsigned height
, tile_height
;
150 height
= mip_minify(ptex
->height0
, level
);
151 if (util_format_is_plain(ptex
->format
)) {
152 tile_height
= r600_get_height_alignment(screen
,
153 rtex
->array_mode
[level
]);
154 height
= align(height
, tile_height
);
156 return util_format_get_nblocksy(ptex
->format
, height
);
159 /* Get a width in pixels from a stride in bytes. */
160 static unsigned pitch_to_width(enum pipe_format format
,
161 unsigned pitch_in_bytes
)
163 return (pitch_in_bytes
/ util_format_get_blocksize(format
)) *
164 util_format_get_blockwidth(format
);
167 static void r600_texture_set_array_mode(struct pipe_screen
*screen
,
168 struct r600_resource_texture
*rtex
,
169 unsigned level
, unsigned array_mode
)
171 rtex
->array_mode
[level
] = array_mode
;
174 static void r600_setup_miptree(struct pipe_screen
*screen
,
175 struct r600_resource_texture
*rtex
,
178 struct pipe_resource
*ptex
= &rtex
->resource
.base
.b
;
179 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
180 enum chip_class chipc
= r600_get_family_class(radeon
);
181 unsigned pitch
, size
, layer_size
, i
, offset
;
184 for (i
= 0, offset
= 0; i
<= ptex
->last_level
; i
++) {
185 r600_texture_set_array_mode(screen
, rtex
, i
, array_mode
);
187 pitch
= r600_texture_get_stride(screen
, rtex
, i
);
188 nblocksy
= r600_texture_get_nblocksy(screen
, rtex
, i
);
190 layer_size
= pitch
* nblocksy
;
192 if (ptex
->target
== PIPE_TEXTURE_CUBE
) {
194 size
= layer_size
* 8;
196 size
= layer_size
* 6;
199 size
= layer_size
* u_minify(ptex
->depth0
, i
);
200 rtex
->offset
[i
] = offset
;
201 rtex
->layer_size
[i
] = layer_size
;
202 rtex
->pitch_in_bytes
[i
] = pitch
;
203 rtex
->pitch_in_pixels
[i
] = pitch_to_width(ptex
->format
, pitch
);
209 static struct r600_resource_texture
*
210 r600_texture_create_object(struct pipe_screen
*screen
,
211 const struct pipe_resource
*base
,
213 unsigned pitch_in_bytes_override
,
214 unsigned max_buffer_size
,
217 struct r600_resource_texture
*rtex
;
218 struct r600_resource
*resource
;
219 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
221 rtex
= CALLOC_STRUCT(r600_resource_texture
);
225 resource
= &rtex
->resource
;
226 resource
->base
.b
= *base
;
227 resource
->base
.vtbl
= &r600_texture_vtbl
;
228 pipe_reference_init(&resource
->base
.b
.reference
, 1);
229 resource
->base
.b
.screen
= screen
;
231 resource
->domain
= r600_domain_from_usage(resource
->base
.b
.bind
);
232 rtex
->pitch_override
= pitch_in_bytes_override
;
236 r600_setup_miptree(screen
, rtex
, array_mode
);
238 resource
->size
= rtex
->size
;
241 resource
->bo
= r600_bo(radeon
, rtex
->size
, 4096, 0);
250 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
251 const struct pipe_resource
*templ
)
253 unsigned array_mode
= 0;
255 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
260 static void r600_texture_destroy(struct pipe_screen
*screen
,
261 struct pipe_resource
*ptex
)
263 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
264 struct r600_resource
*resource
= &rtex
->resource
;
265 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
267 if (rtex
->flushed_depth_texture
)
268 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
271 r600_bo_reference(radeon
, &resource
->bo
, NULL
);
276 static struct pipe_surface
*r600_get_tex_surface(struct pipe_screen
*screen
,
277 struct pipe_resource
*texture
,
278 unsigned face
, unsigned level
,
279 unsigned zslice
, unsigned flags
)
281 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
282 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
283 unsigned offset
, tile_height
;
287 offset
= r600_texture_get_offset(rtex
, level
, zslice
, face
);
288 pipe_reference_init(&surface
->base
.reference
, 1);
289 pipe_resource_reference(&surface
->base
.texture
, texture
);
290 surface
->base
.format
= texture
->format
;
291 surface
->base
.width
= mip_minify(texture
->width0
, level
);
292 surface
->base
.height
= mip_minify(texture
->height0
, level
);
293 surface
->base
.offset
= offset
;
294 surface
->base
.usage
= flags
;
295 surface
->base
.zslice
= zslice
;
296 surface
->base
.texture
= texture
;
297 surface
->base
.face
= face
;
298 surface
->base
.level
= level
;
300 tile_height
= r600_get_height_alignment(screen
, rtex
->array_mode
[level
]);
301 surface
->aligned_height
= align(surface
->base
.height
, tile_height
);
302 return &surface
->base
;
305 static void r600_tex_surface_destroy(struct pipe_surface
*surface
)
307 pipe_resource_reference(&surface
->texture
, NULL
);
312 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
313 const struct pipe_resource
*templ
,
314 struct winsys_handle
*whandle
)
316 struct radeon
*rw
= (struct radeon
*)screen
->winsys
;
317 struct r600_bo
*bo
= NULL
;
318 unsigned array_mode
= 0;
320 /* Support only 2D textures without mipmaps */
321 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
322 templ
->depth0
!= 1 || templ
->last_level
!= 0)
325 bo
= r600_bo_handle(rw
, whandle
->handle
, &array_mode
);
330 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
336 static unsigned int r600_texture_is_referenced(struct pipe_context
*context
,
337 struct pipe_resource
*texture
,
338 unsigned face
, unsigned level
)
341 return PIPE_REFERENCED_FOR_READ
| PIPE_REFERENCED_FOR_WRITE
;
344 int (*r600_blit_uncompress_depth_ptr
)(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
346 int r600_texture_depth_flush(struct pipe_context
*ctx
,
347 struct pipe_resource
*texture
)
349 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
350 struct pipe_resource resource
;
352 if (rtex
->flushed_depth_texture
)
355 resource
.target
= PIPE_TEXTURE_2D
;
356 resource
.format
= texture
->format
;
357 resource
.width0
= texture
->width0
;
358 resource
.height0
= texture
->height0
;
360 resource
.last_level
= 0;
361 resource
.nr_samples
= 0;
362 resource
.usage
= PIPE_USAGE_DYNAMIC
;
364 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
366 resource
.bind
|= PIPE_BIND_DEPTH_STENCIL
;
368 rtex
->flushed_depth_texture
= (struct r600_resource_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
369 if (rtex
->flushed_depth_texture
== NULL
) {
370 R600_ERR("failed to create temporary texture to hold untiled copy\n");
375 r600_blit_uncompress_depth_ptr(ctx
, rtex
);
379 struct pipe_transfer
* r600_texture_get_transfer(struct pipe_context
*ctx
,
380 struct pipe_resource
*texture
,
381 struct pipe_subresource sr
,
383 const struct pipe_box
*box
)
385 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
386 struct pipe_resource resource
;
387 struct r600_transfer
*trans
;
390 trans
= CALLOC_STRUCT(r600_transfer
);
393 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
394 trans
->transfer
.sr
= sr
;
395 trans
->transfer
.usage
= usage
;
396 trans
->transfer
.box
= *box
;
398 r
= r600_texture_depth_flush(ctx
, texture
);
400 R600_ERR("failed to create temporary texture to hold untiled copy\n");
401 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
405 } else if (rtex
->tiled
) {
406 resource
.target
= PIPE_TEXTURE_2D
;
407 resource
.format
= texture
->format
;
408 resource
.width0
= box
->width
;
409 resource
.height0
= box
->height
;
411 resource
.last_level
= 0;
412 resource
.nr_samples
= 0;
413 resource
.usage
= PIPE_USAGE_DYNAMIC
;
415 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
416 /* For texture reading, the temporary (detiled) texture is used as
417 * a render target when blitting from a tiled texture. */
418 if (usage
& PIPE_TRANSFER_READ
) {
419 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
421 /* For texture writing, the temporary texture is used as a sampler
422 * when blitting into a tiled texture. */
423 if (usage
& PIPE_TRANSFER_WRITE
) {
424 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
426 /* Create the temporary texture. */
427 trans
->linear_texture
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
428 if (trans
->linear_texture
== NULL
) {
429 R600_ERR("failed to create temporary texture to hold untiled copy\n");
430 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
435 trans
->transfer
.stride
=
436 ((struct r600_resource_texture
*)trans
->linear_texture
)->pitch_in_bytes
[0];
437 if (usage
& PIPE_TRANSFER_READ
) {
438 /* We cannot map a tiled texture directly because the data is
439 * in a different order, therefore we do detiling using a blit. */
440 r600_copy_from_tiled_texture(ctx
, trans
);
441 /* Always referenced in the blit. */
442 ctx
->flush(ctx
, 0, NULL
);
444 return &trans
->transfer
;
446 trans
->transfer
.stride
= rtex
->pitch_in_bytes
[sr
.level
];
447 trans
->offset
= r600_texture_get_offset(rtex
, sr
.level
, box
->z
, sr
.face
);
448 return &trans
->transfer
;
451 void r600_texture_transfer_destroy(struct pipe_context
*ctx
,
452 struct pipe_transfer
*transfer
)
454 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
455 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
457 if (rtransfer
->linear_texture
) {
458 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
459 r600_copy_into_tiled_texture(ctx
, rtransfer
);
461 pipe_resource_reference(&rtransfer
->linear_texture
, NULL
);
463 if (rtex
->flushed_depth_texture
) {
464 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
466 pipe_resource_reference(&transfer
->resource
, NULL
);
470 void* r600_texture_transfer_map(struct pipe_context
*ctx
,
471 struct pipe_transfer
* transfer
)
473 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
475 enum pipe_format format
= transfer
->resource
->format
;
476 struct radeon
*radeon
= (struct radeon
*)ctx
->screen
->winsys
;
480 if (rtransfer
->linear_texture
) {
481 bo
= ((struct r600_resource
*)rtransfer
->linear_texture
)->bo
;
483 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
485 if (rtex
->flushed_depth_texture
)
486 bo
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->bo
;
488 bo
= ((struct r600_resource
*)transfer
->resource
)->bo
;
490 offset
= rtransfer
->offset
+
491 transfer
->box
.y
/ util_format_get_blockheight(format
) * transfer
->stride
+
492 transfer
->box
.x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
494 map
= r600_bo_map(radeon
, bo
, 0, ctx
);
502 void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
503 struct pipe_transfer
* transfer
)
505 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
506 struct radeon
*radeon
= (struct radeon
*)ctx
->screen
->winsys
;
509 if (rtransfer
->linear_texture
) {
510 bo
= ((struct r600_resource
*)rtransfer
->linear_texture
)->bo
;
512 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)transfer
->resource
;
514 if (rtex
->flushed_depth_texture
) {
515 bo
= ((struct r600_resource
*)rtex
->flushed_depth_texture
)->bo
;
517 bo
= ((struct r600_resource
*)transfer
->resource
)->bo
;
520 r600_bo_unmap(radeon
, bo
);
523 struct u_resource_vtbl r600_texture_vtbl
=
525 u_default_resource_get_handle
, /* get_handle */
526 r600_texture_destroy
, /* resource_destroy */
527 r600_texture_is_referenced
, /* is_resource_referenced */
528 r600_texture_get_transfer
, /* get_transfer */
529 r600_texture_transfer_destroy
, /* transfer_destroy */
530 r600_texture_transfer_map
, /* transfer_map */
531 u_default_transfer_flush_region
,/* transfer_flush_region */
532 r600_texture_transfer_unmap
, /* transfer_unmap */
533 u_default_transfer_inline_write
/* transfer_inline_write */
536 void r600_init_screen_texture_functions(struct pipe_screen
*screen
)
538 screen
->get_tex_surface
= r600_get_tex_surface
;
539 screen
->tex_surface_destroy
= r600_tex_surface_destroy
;
542 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
543 const unsigned char *swizzle_view
)
546 unsigned char swizzle
[4];
548 const uint32_t swizzle_shift
[4] = {
551 const uint32_t swizzle_bit
[4] = {
556 /* Combine two sets of swizzles. */
557 for (i
= 0; i
< 4; i
++) {
558 swizzle
[i
] = swizzle_view
[i
] <= UTIL_FORMAT_SWIZZLE_W
?
559 swizzle_format
[swizzle_view
[i
]] : swizzle_view
[i
];
562 memcpy(swizzle
, swizzle_format
, 4);
566 for (i
= 0; i
< 4; i
++) {
567 switch (swizzle
[i
]) {
568 case UTIL_FORMAT_SWIZZLE_Y
:
569 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
571 case UTIL_FORMAT_SWIZZLE_Z
:
572 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
574 case UTIL_FORMAT_SWIZZLE_W
:
575 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
577 case UTIL_FORMAT_SWIZZLE_0
:
578 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
580 case UTIL_FORMAT_SWIZZLE_1
:
581 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
583 default: /* UTIL_FORMAT_SWIZZLE_X */
584 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
590 /* texture format translate */
591 uint32_t r600_translate_texformat(enum pipe_format format
,
592 const unsigned char *swizzle_view
,
593 uint32_t *word4_p
, uint32_t *yuv_format_p
)
595 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
596 const struct util_format_description
*desc
;
597 boolean uniform
= TRUE
;
599 const uint32_t sign_bit
[4] = {
600 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
601 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
602 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
603 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
605 desc
= util_format_description(format
);
607 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
609 /* Colorspace (return non-RGB formats directly). */
610 switch (desc
->colorspace
) {
611 /* Depth stencil formats */
612 case UTIL_FORMAT_COLORSPACE_ZS
:
614 case PIPE_FORMAT_Z16_UNORM
:
617 case PIPE_FORMAT_X24S8_USCALED
:
618 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
619 case PIPE_FORMAT_Z24X8_UNORM
:
620 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
623 case PIPE_FORMAT_S8X24_USCALED
:
624 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
625 case PIPE_FORMAT_X8Z24_UNORM
:
626 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
629 case PIPE_FORMAT_S8_USCALED
:
630 result
= V_0280A0_COLOR_8
;
631 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
637 case UTIL_FORMAT_COLORSPACE_YUV
:
638 yuv_format
|= (1 << 30);
640 case PIPE_FORMAT_UYVY
:
641 case PIPE_FORMAT_YUYV
:
645 goto out_unknown
; /* TODO */
647 case UTIL_FORMAT_COLORSPACE_SRGB
:
648 word4
|= S_038010_FORCE_DEGAMMA(1);
649 if (format
== PIPE_FORMAT_L8A8_SRGB
|| format
== PIPE_FORMAT_L8_SRGB
)
650 goto out_unknown
; /* fails for some reason - TODO */
657 /* S3TC formats. TODO */
658 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
663 for (i
= 0; i
< desc
->nr_channels
; i
++) {
664 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
665 word4
|= sign_bit
[i
];
669 /* R8G8Bx_SNORM - TODO CxV8U8 */
673 /* See whether the components are of the same size. */
674 for (i
= 1; i
< desc
->nr_channels
; i
++) {
675 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
678 /* Non-uniform formats. */
680 switch(desc
->nr_channels
) {
682 if (desc
->channel
[0].size
== 5 &&
683 desc
->channel
[1].size
== 6 &&
684 desc
->channel
[2].size
== 5) {
690 if (desc
->channel
[0].size
== 5 &&
691 desc
->channel
[1].size
== 5 &&
692 desc
->channel
[2].size
== 5 &&
693 desc
->channel
[3].size
== 1) {
694 result
= FMT_1_5_5_5
;
697 if (desc
->channel
[0].size
== 10 &&
698 desc
->channel
[1].size
== 10 &&
699 desc
->channel
[2].size
== 10 &&
700 desc
->channel
[3].size
== 2) {
701 result
= FMT_10_10_10_2
;
709 /* Find the first non-VOID channel. */
710 for (i
= 0; i
< 4; i
++) {
711 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
719 /* uniform formats */
720 switch (desc
->channel
[i
].type
) {
721 case UTIL_FORMAT_TYPE_UNSIGNED
:
722 case UTIL_FORMAT_TYPE_SIGNED
:
723 if (!desc
->channel
[i
].normalized
&&
724 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
728 switch (desc
->channel
[i
].size
) {
730 switch (desc
->nr_channels
) {
735 result
= FMT_4_4_4_4
;
740 switch (desc
->nr_channels
) {
748 result
= FMT_8_8_8_8
;
753 switch (desc
->nr_channels
) {
761 result
= FMT_16_16_16_16
;
767 case UTIL_FORMAT_TYPE_FLOAT
:
768 switch (desc
->channel
[i
].size
) {
770 switch (desc
->nr_channels
) {
772 result
= FMT_16_FLOAT
;
775 result
= FMT_16_16_FLOAT
;
778 result
= FMT_16_16_16_16_FLOAT
;
783 switch (desc
->nr_channels
) {
785 result
= FMT_32_FLOAT
;
788 result
= FMT_32_32_FLOAT
;
791 result
= FMT_32_32_32_32_FLOAT
;
801 *yuv_format_p
= yuv_format
;
804 // R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));