src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_math.h>
  31 #include <util/u_inlines.h>
  32 #include <util/u_memory.h>
  33 #include "state_tracker/drm_driver.h"
  34 #include "pipebuffer/pb_buffer.h"
  35 #include "r600_pipe.h"
  36 #include "r600_resource.h"
  37 #include "r600_state_inlines.h"
  38 #include "r600d.h"
  39 #include "r600_formats.h"
  40
  41 /* Copy from a full GPU texture to a transfer's staging one. */
  42 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  43 {
  44         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  45         struct pipe_resource *texture = transfer->resource;
  46
  47         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  48                                 0, 0, 0, 0, texture, transfer->level,
  49                                 &transfer->box);
  50 }
  51
  52
  53 /* Copy from a transfer's staging texture to a full GPU one. */
  54 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  55 {
  56         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  57         struct pipe_resource *texture = transfer->resource;
  58         struct pipe_box sbox;
  59
  60         sbox.x = sbox.y = sbox.z = 0;
  61         sbox.width = transfer->box.width;
  62         sbox.height = transfer->box.height;
  63         /* XXX that might be wrong */
  64         sbox.depth = 1;
  65         ctx->resource_copy_region(ctx, texture, transfer->level,
  66                                   transfer->box.x, transfer->box.y, transfer->box.z,
  67                                   rtransfer->staging_texture,
  68                                   0, &sbox);
  69
  70         ctx->flush(ctx, 0, NULL);
  71 }
  72
  73 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  74                                         unsigned level, unsigned layer)
  75 {
  76         unsigned offset = rtex->offset[level];
  77
  78         switch (rtex->resource.b.b.b.target) {
  79         case PIPE_TEXTURE_3D:
  80         case PIPE_TEXTURE_CUBE:
  81                 return offset + layer * rtex->layer_size[level];
  82         default:
  83                 assert(layer == 0);
  84                 return offset;
  85         }
  86 }
  87
  88 static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
  89                                          enum pipe_format format,
  90                                          unsigned array_mode)
  91 {
  92         struct r600_screen* rscreen = (struct r600_screen *)screen;
  93         unsigned pixsize = util_format_get_blocksize(format);
  94         int p_align;
  95
  96         switch(array_mode) {
  97         case V_038000_ARRAY_1D_TILED_THIN1:
  98                 p_align = MAX2(8,
  99                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
 100                 break;
 101         case V_038000_ARRAY_2D_TILED_THIN1:
 102                 p_align = MAX2(rscreen->tiling_info->num_banks,
 103                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 104                                 rscreen->tiling_info->num_banks)) * 8;
 105                 break;
 106         case V_038000_ARRAY_LINEAR_ALIGNED:
 107                 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
 108                 break;
 109         case V_038000_ARRAY_LINEAR_GENERAL:
 110         default:
 111                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 112                 break;
 113         }
 114         return p_align;
 115 }
 116
 117 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 118                                           unsigned array_mode)
 119 {
 120         struct r600_screen* rscreen = (struct r600_screen *)screen;
 121         int h_align;
 122
 123         switch (array_mode) {
 124         case V_038000_ARRAY_2D_TILED_THIN1:
 125                 h_align = rscreen->tiling_info->num_channels * 8;
 126                 break;
 127         case V_038000_ARRAY_1D_TILED_THIN1:
 128         case V_038000_ARRAY_LINEAR_ALIGNED:
 129                 h_align = 8;
 130                 break;
 131         default:
 132                 h_align = 1;
 133                 break;
 134         }
 135         return h_align;
 136 }
 137
 138 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 139                                         enum pipe_format format,
 140                                         unsigned array_mode)
 141 {
 142         struct r600_screen* rscreen = (struct r600_screen *)screen;
 143         unsigned pixsize = util_format_get_blocksize(format);
 144         int p_align = r600_get_pixel_alignment(screen, format, array_mode);
 145         int h_align = r600_get_height_alignment(screen, array_mode);
 146         int b_align;
 147
 148         switch (array_mode) {
 149         case V_038000_ARRAY_2D_TILED_THIN1:
 150                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 151                                p_align * pixsize * h_align);
 152                 break;
 153         case V_038000_ARRAY_1D_TILED_THIN1:
 154         case V_038000_ARRAY_LINEAR_ALIGNED:
 155         case V_038000_ARRAY_LINEAR_GENERAL:
 156         default:
 157                 b_align = rscreen->tiling_info->group_bytes;
 158                 break;
 159         }
 160         return b_align;
 161 }
 162
 163 static unsigned mip_minify(unsigned size, unsigned level)
 164 {
 165         unsigned val;
 166         val = u_minify(size, level);
 167         if (level > 0)
 168                 val = util_next_power_of_two(val);
 169         return val;
 170 }
 171
 172 static unsigned r600_texture_get_stride(struct pipe_screen *screen,
 173                                         struct r600_resource_texture *rtex,
 174                                         unsigned level)
 175 {
 176         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 177         unsigned width, stride, tile_width;
 178
 179         if (rtex->pitch_override)
 180                 return rtex->pitch_override;
 181
 182         width = mip_minify(ptex->width0, level);
 183         if (util_format_is_plain(ptex->format)) {
 184                 tile_width = r600_get_pixel_alignment(screen, ptex->format,
 185                                                       rtex->array_mode[level]);
 186                 width = align(width, tile_width);
 187         }
 188         stride = util_format_get_stride(ptex->format, width);
 189
 190         return stride;
 191 }
 192
 193 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 194                                           struct r600_resource_texture *rtex,
 195                                           unsigned level)
 196 {
 197         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 198         unsigned height, tile_height;
 199
 200         height = mip_minify(ptex->height0, level);
 201         if (util_format_is_plain(ptex->format)) {
 202                 tile_height = r600_get_height_alignment(screen,
 203                                                         rtex->array_mode[level]);
 204                 height = align(height, tile_height);
 205         }
 206         return util_format_get_nblocksy(ptex->format, height);
 207 }
 208
 209 /* Get a width in pixels from a stride in bytes. */
 210 static unsigned pitch_to_width(enum pipe_format format, unsigned pitch_in_bytes)
 211 {
 212         return (pitch_in_bytes / util_format_get_blocksize(format)) *
 213                 util_format_get_blockwidth(format);
 214 }
 215
 216 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 217                                         struct r600_resource_texture *rtex,
 218                                         unsigned level, unsigned array_mode)
 219 {
 220         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 221
 222         switch (array_mode) {
 223         case V_0280A0_ARRAY_LINEAR_GENERAL:
 224         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 225         case V_0280A0_ARRAY_1D_TILED_THIN1:
 226         default:
 227                 rtex->array_mode[level] = array_mode;
 228                 break;
 229         case V_0280A0_ARRAY_2D_TILED_THIN1:
 230         {
 231                 unsigned w, h, tile_height, tile_width;
 232
 233                 tile_height = r600_get_height_alignment(screen, array_mode);
 234                 tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode);
 235
 236                 w = mip_minify(ptex->width0, level);
 237                 h = mip_minify(ptex->height0, level);
 238                 if (w < tile_width || h < tile_height)
 239                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 240                 else
 241                         rtex->array_mode[level] = array_mode;
 242         }
 243         break;
 244         }
 245 }
 246
 247 static void r600_setup_miptree(struct pipe_screen *screen,
 248                                struct r600_resource_texture *rtex,
 249                                unsigned array_mode)
 250 {
 251         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 252         struct radeon *radeon = (struct radeon *)screen->winsys;
 253         enum chip_class chipc = r600_get_family_class(radeon);
 254         unsigned pitch, size, layer_size, i, offset;
 255         unsigned nblocksy;
 256
 257         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 258                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 259
 260                 pitch = r600_texture_get_stride(screen, rtex, i);
 261                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 262
 263                 layer_size = pitch * nblocksy;
 264
 265                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 266                         if (chipc >= R700)
 267                                 size = layer_size * 8;
 268                         else
 269                                 size = layer_size * 6;
 270                 }
 271                 else
 272                         size = layer_size * u_minify(ptex->depth0, i);
 273                 /* align base image and start of miptree */
 274                 if ((i == 0) || (i == 1))
 275                         offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
 276                 rtex->offset[i] = offset;
 277                 rtex->layer_size[i] = layer_size;
 278                 rtex->pitch_in_bytes[i] = pitch;
 279                 rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
 280                 offset += size;
 281         }
 282         rtex->size = offset;
 283 }
 284
 285 /* Figure out whether u_blitter will fallback to a transfer operation.
 286  * If so, don't use a staging resource.
 287  */
 288 static boolean permit_hardware_blit(struct pipe_screen *screen,
 289                                         const struct pipe_resource *res)
 290 {
 291         unsigned bind;
 292
 293         if (util_format_is_depth_or_stencil(res->format))
 294                 bind = PIPE_BIND_DEPTH_STENCIL;
 295         else
 296                 bind = PIPE_BIND_RENDER_TARGET;
 297
 298         if (!screen->is_format_supported(screen,
 299                                 res->format,
 300                                 res->target,
 301                                 res->nr_samples,
 302                                 bind, 0))
 303                 return FALSE;
 304
 305         if (!screen->is_format_supported(screen,
 306                                 res->format,
 307                                 res->target,
 308                                 res->nr_samples,
 309                                 PIPE_BIND_SAMPLER_VIEW, 0))
 310                 return FALSE;
 311
 312         return TRUE;
 313 }
 314
 315 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 316                                         struct pipe_resource *ptex,
 317                                         struct winsys_handle *whandle)
 318 {
 319         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 320         struct r600_resource *resource = &rtex->resource;
 321         struct radeon *radeon = (struct radeon *)screen->winsys;
 322
 323         return r600_bo_get_winsys_handle(radeon, resource->bo,
 324                         rtex->pitch_in_bytes[0], whandle);
 325 }
 326
 327 static void r600_texture_destroy(struct pipe_screen *screen,
 328                                  struct pipe_resource *ptex)
 329 {
 330         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 331         struct r600_resource *resource = &rtex->resource;
 332         struct radeon *radeon = (struct radeon *)screen->winsys;
 333
 334         if (rtex->flushed_depth_texture)
 335                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 336
 337         if (resource->bo) {
 338                 r600_bo_reference(radeon, &resource->bo, NULL);
 339         }
 340         FREE(rtex);
 341 }
 342
 343 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 344                                                 struct pipe_resource *texture,
 345                                                 unsigned level, int layer)
 346 {
 347         /* FIXME */
 348         return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 349 }
 350
 351 static const struct u_resource_vtbl r600_texture_vtbl =
 352 {
 353         r600_texture_get_handle,        /* get_handle */
 354         r600_texture_destroy,           /* resource_destroy */
 355         r600_texture_is_referenced,     /* is_resource_referenced */
 356         r600_texture_get_transfer,      /* get_transfer */
 357         r600_texture_transfer_destroy,  /* transfer_destroy */
 358         r600_texture_transfer_map,      /* transfer_map */
 359         u_default_transfer_flush_region,/* transfer_flush_region */
 360         r600_texture_transfer_unmap,    /* transfer_unmap */
 361         u_default_transfer_inline_write /* transfer_inline_write */
 362 };
 363
 364 static struct r600_resource_texture *
 365 r600_texture_create_object(struct pipe_screen *screen,
 366                            const struct pipe_resource *base,
 367                            unsigned array_mode,
 368                            unsigned pitch_in_bytes_override,
 369                            unsigned max_buffer_size,
 370                            struct r600_bo *bo)
 371 {
 372         struct r600_resource_texture *rtex;
 373         struct r600_resource *resource;
 374         struct radeon *radeon = (struct radeon *)screen->winsys;
 375
 376         rtex = CALLOC_STRUCT(r600_resource_texture);
 377         if (rtex == NULL)
 378                 return NULL;
 379
 380         resource = &rtex->resource;
 381         resource->b.b.b = *base;
 382         resource->b.b.vtbl = &r600_texture_vtbl;
 383         pipe_reference_init(&resource->b.b.b.reference, 1);
 384         resource->b.b.b.screen = screen;
 385         resource->bo = bo;
 386         rtex->pitch_override = pitch_in_bytes_override;
 387         /* only mark depth textures the HW can hit as depth textures */
 388         if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
 389                 rtex->depth = 1;
 390
 391         if (array_mode)
 392                 rtex->tiled = 1;
 393         r600_setup_miptree(screen, rtex, array_mode);
 394
 395         resource->size = rtex->size;
 396
 397         if (!resource->bo) {
 398                 struct pipe_resource *ptex = &rtex->resource.b.b.b;
 399                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 400
 401                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 402                 if (!resource->bo) {
 403                         FREE(rtex);
 404                         return NULL;
 405                 }
 406         }
 407         return rtex;
 408 }
 409
 410 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 411                                                 const struct pipe_resource *templ)
 412 {
 413         unsigned array_mode = 0;
 414         static int force_tiling = -1;
 415
 416         /* Would like some magic "get_bool_option_once" routine.
 417          */
 418         if (force_tiling == -1)
 419                 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
 420
 421         if (force_tiling && permit_hardware_blit(screen, templ)) {
 422                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 423                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 424                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 425                 }
 426         }
 427
 428         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 429                                                                   0, 0, NULL);
 430
 431 }
 432
 433 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 434                                                 struct pipe_resource *texture,
 435                                                 const struct pipe_surface *surf_tmpl)
 436 {
 437         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 438         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 439         unsigned level = surf_tmpl->u.tex.level;
 440
 441         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 442         if (surface == NULL)
 443                 return NULL;
 444         /* XXX no offset */
 445 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 446         pipe_reference_init(&surface->base.reference, 1);
 447         pipe_resource_reference(&surface->base.texture, texture);
 448         surface->base.context = pipe;
 449         surface->base.format = surf_tmpl->format;
 450         surface->base.width = mip_minify(texture->width0, level);
 451         surface->base.height = mip_minify(texture->height0, level);
 452         surface->base.usage = surf_tmpl->usage;
 453         surface->base.texture = texture;
 454         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 455         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 456         surface->base.u.tex.level = level;
 457
 458         surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
 459                                                             rtex, level);
 460         return &surface->base;
 461 }
 462
 463 static void r600_surface_destroy(struct pipe_context *pipe,
 464                                  struct pipe_surface *surface)
 465 {
 466         pipe_resource_reference(&surface->texture, NULL);
 467         FREE(surface);
 468 }
 469
 470
 471 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 472                                                const struct pipe_resource *templ,
 473                                                struct winsys_handle *whandle)
 474 {
 475         struct radeon *rw = (struct radeon*)screen->winsys;
 476         struct r600_bo *bo = NULL;
 477         unsigned array_mode = 0;
 478
 479         /* Support only 2D textures without mipmaps */
 480         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 481               templ->depth0 != 1 || templ->last_level != 0)
 482                 return NULL;
 483
 484         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 485         if (bo == NULL) {
 486                 return NULL;
 487         }
 488
 489         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 490                                                                   whandle->stride,
 491                                                                   0,
 492                                                                   bo);
 493 }
 494
 495 int r600_texture_depth_flush(struct pipe_context *ctx,
 496                              struct pipe_resource *texture, boolean just_create)
 497 {
 498         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 499         struct pipe_resource resource;
 500
 501         if (rtex->flushed_depth_texture)
 502                 goto out;
 503
 504         resource.target = PIPE_TEXTURE_2D;
 505         resource.format = texture->format;
 506         resource.width0 = texture->width0;
 507         resource.height0 = texture->height0;
 508         resource.depth0 = 1;
 509         resource.last_level = texture->last_level;
 510         resource.nr_samples = 0;
 511         resource.usage = PIPE_USAGE_DYNAMIC;
 512         resource.bind = 0;
 513         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 514
 515         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 516
 517         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 518         if (rtex->flushed_depth_texture == NULL) {
 519                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 520                 return -ENOMEM;
 521         }
 522
 523         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 524 out:
 525         if (just_create)
 526                 return 0;
 527
 528         /* XXX: only do this if the depth texture has actually changed:
 529          */
 530         r600_blit_uncompress_depth(ctx, rtex);
 531         return 0;
 532 }
 533
 534 /* Needs adjustment for pixelformat:
 535  */
 536 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 537 {
 538         return box->width * box->depth * box->height;
 539 };
 540
 541 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 542                                                 struct pipe_resource *texture,
 543                                                 unsigned level,
 544                                                 unsigned usage,
 545                                                 const struct pipe_box *box)
 546 {
 547         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 548         struct pipe_resource resource;
 549         struct r600_transfer *trans;
 550         int r;
 551         boolean use_staging_texture = FALSE;
 552
 553         /* We cannot map a tiled texture directly because the data is
 554          * in a different order, therefore we do detiling using a blit.
 555          *
 556          * Also, use a temporary in GTT memory for read transfers, as
 557          * the CPU is much happier reading out of cached system memory
 558          * than uncached VRAM.
 559          */
 560         if (rtex->tiled)
 561                 use_staging_texture = TRUE;
 562
 563         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 564                 use_staging_texture = TRUE;
 565
 566         /* XXX: Use a staging texture for uploads if the underlying BO
 567          * is busy.  No interface for checking that currently? so do
 568          * it eagerly whenever the transfer doesn't require a readback
 569          * and might block.
 570          */
 571         if ((usage & PIPE_TRANSFER_WRITE) &&
 572                         !(usage & (PIPE_TRANSFER_READ |
 573                                         PIPE_TRANSFER_DONTBLOCK |
 574                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 575                 use_staging_texture = TRUE;
 576
 577         if (!permit_hardware_blit(ctx->screen, texture) ||
 578                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 579                 use_staging_texture = FALSE;
 580
 581         trans = CALLOC_STRUCT(r600_transfer);
 582         if (trans == NULL)
 583                 return NULL;
 584         pipe_resource_reference(&trans->transfer.resource, texture);
 585         trans->transfer.level = level;
 586         trans->transfer.usage = usage;
 587         trans->transfer.box = *box;
 588         if (rtex->depth) {
 589                 /* XXX: only readback the rectangle which is being mapped?
 590                 */
 591                 /* XXX: when discard is true, no need to read back from depth texture
 592                 */
 593                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 594                 if (r < 0) {
 595                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 596                         pipe_resource_reference(&trans->transfer.resource, NULL);
 597                         FREE(trans);
 598                         return NULL;
 599                 }
 600                 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
 601                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 602                 return &trans->transfer;
 603         } else if (use_staging_texture) {
 604                 resource.target = PIPE_TEXTURE_2D;
 605                 resource.format = texture->format;
 606                 resource.width0 = box->width;
 607                 resource.height0 = box->height;
 608                 resource.depth0 = 1;
 609                 resource.array_size = 1;
 610                 resource.last_level = 0;
 611                 resource.nr_samples = 0;
 612                 resource.usage = PIPE_USAGE_STAGING;
 613                 resource.bind = 0;
 614                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 615                 /* For texture reading, the temporary (detiled) texture is used as
 616                  * a render target when blitting from a tiled texture. */
 617                 if (usage & PIPE_TRANSFER_READ) {
 618                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 619                 }
 620                 /* For texture writing, the temporary texture is used as a sampler
 621                  * when blitting into a tiled texture. */
 622                 if (usage & PIPE_TRANSFER_WRITE) {
 623                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 624                 }
 625                 /* Create the temporary texture. */
 626                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 627                 if (trans->staging_texture == NULL) {
 628                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 629                         pipe_resource_reference(&trans->transfer.resource, NULL);
 630                         FREE(trans);
 631                         return NULL;
 632                 }
 633
 634                 trans->transfer.stride =
 635                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 636                 if (usage & PIPE_TRANSFER_READ) {
 637                         r600_copy_to_staging_texture(ctx, trans);
 638                         /* Always referenced in the blit. */
 639                         ctx->flush(ctx, 0, NULL);
 640                 }
 641                 return &trans->transfer;
 642         }
 643         trans->transfer.stride = rtex->pitch_in_bytes[level];
 644         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 645         return &trans->transfer;
 646 }
 647
 648 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 649                                    struct pipe_transfer *transfer)
 650 {
 651         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 652         struct pipe_resource *texture = transfer->resource;
 653         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 654
 655         if (rtransfer->staging_texture) {
 656                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 657                         r600_copy_from_staging_texture(ctx, rtransfer);
 658                 }
 659                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 660         }
 661
 662         if (rtex->depth && !rtex->is_flushing_texture) {
 663                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 664                         r600_blit_push_depth(ctx, rtex);
 665         }
 666
 667         pipe_resource_reference(&transfer->resource, NULL);
 668         FREE(transfer);
 669 }
 670
 671 void* r600_texture_transfer_map(struct pipe_context *ctx,
 672                                 struct pipe_transfer* transfer)
 673 {
 674         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 675         struct r600_bo *bo;
 676         enum pipe_format format = transfer->resource->format;
 677         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 678         unsigned offset = 0;
 679         unsigned usage = 0;
 680         char *map;
 681
 682         if (rtransfer->staging_texture) {
 683                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 684         } else {
 685                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 686
 687                 if (rtex->flushed_depth_texture)
 688                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 689                 else
 690                         bo = ((struct r600_resource *)transfer->resource)->bo;
 691
 692                 offset = rtransfer->offset +
 693                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 694                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 695         }
 696
 697         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 698                 usage |= PB_USAGE_CPU_WRITE;
 699
 700                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 701                 }
 702
 703                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 704                 }
 705         }
 706
 707         if (transfer->usage & PIPE_TRANSFER_READ) {
 708                 usage |= PB_USAGE_CPU_READ;
 709         }
 710
 711         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 712                 usage |= PB_USAGE_DONTBLOCK;
 713         }
 714
 715         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 716                 usage |= PB_USAGE_UNSYNCHRONIZED;
 717         }
 718
 719         map = r600_bo_map(radeon, bo, usage, ctx);
 720         if (!map) {
 721                 return NULL;
 722         }
 723
 724         return map + offset;
 725 }
 726
 727 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 728                                  struct pipe_transfer* transfer)
 729 {
 730         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 731         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 732         struct r600_bo *bo;
 733
 734         if (rtransfer->staging_texture) {
 735                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 736         } else {
 737                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 738
 739                 if (rtex->flushed_depth_texture) {
 740                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 741                 } else {
 742                         bo = ((struct r600_resource *)transfer->resource)->bo;
 743                 }
 744         }
 745         r600_bo_unmap(radeon, bo);
 746 }
 747
 748 void r600_init_surface_functions(struct r600_pipe_context *r600)
 749 {
 750         r600->context.create_surface = r600_create_surface;
 751         r600->context.surface_destroy = r600_surface_destroy;
 752 }
 753
 754 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 755                 const unsigned char *swizzle_view)
 756 {
 757         unsigned i;
 758         unsigned char swizzle[4];
 759         unsigned result = 0;
 760         const uint32_t swizzle_shift[4] = {
 761                 16, 19, 22, 25,
 762         };
 763         const uint32_t swizzle_bit[4] = {
 764                 0, 1, 2, 3,
 765         };
 766
 767         if (swizzle_view) {
 768                 /* Combine two sets of swizzles. */
 769                 for (i = 0; i < 4; i++) {
 770                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 771                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 772                 }
 773         } else {
 774                 memcpy(swizzle, swizzle_format, 4);
 775         }
 776
 777         /* Get swizzle. */
 778         for (i = 0; i < 4; i++) {
 779                 switch (swizzle[i]) {
 780                 case UTIL_FORMAT_SWIZZLE_Y:
 781                         result |= swizzle_bit[1] << swizzle_shift[i];
 782                         break;
 783                 case UTIL_FORMAT_SWIZZLE_Z:
 784                         result |= swizzle_bit[2] << swizzle_shift[i];
 785                         break;
 786                 case UTIL_FORMAT_SWIZZLE_W:
 787                         result |= swizzle_bit[3] << swizzle_shift[i];
 788                         break;
 789                 case UTIL_FORMAT_SWIZZLE_0:
 790                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 791                         break;
 792                 case UTIL_FORMAT_SWIZZLE_1:
 793                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 794                         break;
 795                 default: /* UTIL_FORMAT_SWIZZLE_X */
 796                         result |= swizzle_bit[0] << swizzle_shift[i];
 797                 }
 798         }
 799         return result;
 800 }
 801
 802 /* texture format translate */
 803 uint32_t r600_translate_texformat(enum pipe_format format,
 804                                   const unsigned char *swizzle_view,
 805                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 806 {
 807         uint32_t result = 0, word4 = 0, yuv_format = 0;
 808         const struct util_format_description *desc;
 809         boolean uniform = TRUE;
 810         int i;
 811         const uint32_t sign_bit[4] = {
 812                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 813                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 814                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 815                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 816         };
 817         desc = util_format_description(format);
 818
 819         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 820
 821         /* Colorspace (return non-RGB formats directly). */
 822         switch (desc->colorspace) {
 823                 /* Depth stencil formats */
 824         case UTIL_FORMAT_COLORSPACE_ZS:
 825                 switch (format) {
 826                 case PIPE_FORMAT_Z16_UNORM:
 827                         result = FMT_16;
 828                         goto out_word4;
 829                 case PIPE_FORMAT_X24S8_USCALED:
 830                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 831                 case PIPE_FORMAT_Z24X8_UNORM:
 832                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 833                         result = FMT_8_24;
 834                         goto out_word4;
 835                 case PIPE_FORMAT_S8X24_USCALED:
 836                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 837                 case PIPE_FORMAT_X8Z24_UNORM:
 838                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 839                         result = FMT_24_8;
 840                         goto out_word4;
 841                 case PIPE_FORMAT_S8_USCALED:
 842                         result = FMT_8;
 843                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 844                         goto out_word4;
 845                 default:
 846                         goto out_unknown;
 847                 }
 848
 849         case UTIL_FORMAT_COLORSPACE_YUV:
 850                 yuv_format |= (1 << 30);
 851                 switch (format) {
 852                 case PIPE_FORMAT_UYVY:
 853                 case PIPE_FORMAT_YUYV:
 854                 default:
 855                         break;
 856                 }
 857                 goto out_unknown; /* TODO */
 858
 859         case UTIL_FORMAT_COLORSPACE_SRGB:
 860                 word4 |= S_038010_FORCE_DEGAMMA(1);
 861                 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
 862                         goto out_unknown; /* fails for some reason - TODO */
 863                 break;
 864
 865         default:
 866                 break;
 867         }
 868
 869         /* S3TC formats. TODO */
 870         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 871                 static int r600_enable_s3tc = -1;
 872
 873                 if (r600_enable_s3tc == -1)
 874                         r600_enable_s3tc =
 875                                 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 876
 877                 if (!r600_enable_s3tc)
 878                         goto out_unknown;
 879
 880                 switch (format) {
 881                 case PIPE_FORMAT_DXT1_RGB:
 882                 case PIPE_FORMAT_DXT1_RGBA:
 883                         result = FMT_BC1;
 884                         goto out_word4;
 885                 case PIPE_FORMAT_DXT3_RGBA:
 886                         result = FMT_BC2;
 887                         goto out_word4;
 888                 case PIPE_FORMAT_DXT5_RGBA:
 889                         result = FMT_BC3;
 890                         goto out_word4;
 891                 default:
 892                         goto out_unknown;
 893                 }
 894         }
 895
 896
 897         for (i = 0; i < desc->nr_channels; i++) {
 898                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 899                         word4 |= sign_bit[i];
 900                 }
 901         }
 902
 903         /* R8G8Bx_SNORM - TODO CxV8U8 */
 904
 905         /* RGTC - TODO */
 906
 907         /* See whether the components are of the same size. */
 908         for (i = 1; i < desc->nr_channels; i++) {
 909                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 910         }
 911
 912         /* Non-uniform formats. */
 913         if (!uniform) {
 914                 switch(desc->nr_channels) {
 915                 case 3:
 916                         if (desc->channel[0].size == 5 &&
 917                             desc->channel[1].size == 6 &&
 918                             desc->channel[2].size == 5) {
 919                                 result = FMT_5_6_5;
 920                                 goto out_word4;
 921                         }
 922                         goto out_unknown;
 923                 case 4:
 924                         if (desc->channel[0].size == 5 &&
 925                             desc->channel[1].size == 5 &&
 926                             desc->channel[2].size == 5 &&
 927                             desc->channel[3].size == 1) {
 928                                 result = FMT_1_5_5_5;
 929                                 goto out_word4;
 930                         }
 931                         if (desc->channel[0].size == 10 &&
 932                             desc->channel[1].size == 10 &&
 933                             desc->channel[2].size == 10 &&
 934                             desc->channel[3].size == 2) {
 935                                 result = FMT_2_10_10_10;
 936                                 goto out_word4;
 937                         }
 938                         goto out_unknown;
 939                 }
 940                 goto out_unknown;
 941         }
 942
 943         /* Find the first non-VOID channel. */
 944         for (i = 0; i < 4; i++) {
 945                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 946                         break;
 947                 }
 948         }
 949
 950         if (i == 4)
 951                 goto out_unknown;
 952
 953         /* uniform formats */
 954         switch (desc->channel[i].type) {
 955         case UTIL_FORMAT_TYPE_UNSIGNED:
 956         case UTIL_FORMAT_TYPE_SIGNED:
 957                 if (!desc->channel[i].normalized &&
 958                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 959                         goto out_unknown;
 960                 }
 961
 962                 switch (desc->channel[i].size) {
 963                 case 4:
 964                         switch (desc->nr_channels) {
 965                         case 2:
 966                                 result = FMT_4_4;
 967                                 goto out_word4;
 968                         case 4:
 969                                 result = FMT_4_4_4_4;
 970                                 goto out_word4;
 971                         }
 972                         goto out_unknown;
 973                 case 8:
 974                         switch (desc->nr_channels) {
 975                         case 1:
 976                                 result = FMT_8;
 977                                 goto out_word4;
 978                         case 2:
 979                                 result = FMT_8_8;
 980                                 goto out_word4;
 981                         case 4:
 982                                 result = FMT_8_8_8_8;
 983                                 goto out_word4;
 984                         }
 985                         goto out_unknown;
 986                 case 16:
 987                         switch (desc->nr_channels) {
 988                         case 1:
 989                                 result = FMT_16;
 990                                 goto out_word4;
 991                         case 2:
 992                                 result = FMT_16_16;
 993                                 goto out_word4;
 994                         case 4:
 995                                 result = FMT_16_16_16_16;
 996                                 goto out_word4;
 997                         }
 998                         goto out_unknown;
 999                 case 32:
1000                         switch (desc->nr_channels) {
1001                         case 1:
1002                                 result = FMT_32;
1003                                 goto out_word4;
1004                         case 2:
1005                                 result = FMT_32_32;
1006                                 goto out_word4;
1007                         case 4:
1008                                 result = FMT_32_32_32_32;
1009                                 goto out_word4;
1010                         }
1011                 }
1012                 goto out_unknown;
1013
1014         case UTIL_FORMAT_TYPE_FLOAT:
1015                 switch (desc->channel[i].size) {
1016                 case 16:
1017                         switch (desc->nr_channels) {
1018                         case 1:
1019                                 result = FMT_16_FLOAT;
1020                                 goto out_word4;
1021                         case 2:
1022                                 result = FMT_16_16_FLOAT;
1023                                 goto out_word4;
1024                         case 4:
1025                                 result = FMT_16_16_16_16_FLOAT;
1026                                 goto out_word4;
1027                         }
1028                         goto out_unknown;
1029                 case 32:
1030                         switch (desc->nr_channels) {
1031                         case 1:
1032                                 result = FMT_32_FLOAT;
1033                                 goto out_word4;
1034                         case 2:
1035                                 result = FMT_32_32_FLOAT;
1036                                 goto out_word4;
1037                         case 4:
1038                                 result = FMT_32_32_32_32_FLOAT;
1039                                 goto out_word4;
1040                         }
1041                 }
1042
1043         }
1044 out_word4:
1045         if (word4_p)
1046                 *word4_p = word4;
1047         if (yuv_format_p)
1048                 *yuv_format_p = yuv_format;
1049         return result;
1050 out_unknown:
1051 //      R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1052         return ~0;
1053 }