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r600g: fix miptree calculations
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <errno.h>
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_math.h>
31 #include <util/u_inlines.h>
32 #include <util/u_memory.h>
33 #include "state_tracker/drm_driver.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
38 #include "r600d.h"
39 #include "r600_formats.h"
40
41 /* Copy from a full GPU texture to a transfer's staging one. */
42 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
43 {
44 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
45 struct pipe_resource *texture = transfer->resource;
46
47 ctx->resource_copy_region(ctx, rtransfer->staging_texture,
48 0, 0, 0, 0, texture, transfer->level,
49 &transfer->box);
50 }
51
52
53 /* Copy from a transfer's staging texture to a full GPU one. */
54 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
55 {
56 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
57 struct pipe_resource *texture = transfer->resource;
58 struct pipe_box sbox;
59
60 sbox.x = sbox.y = sbox.z = 0;
61 sbox.width = transfer->box.width;
62 sbox.height = transfer->box.height;
63 /* XXX that might be wrong */
64 sbox.depth = 1;
65 ctx->resource_copy_region(ctx, texture, transfer->level,
66 transfer->box.x, transfer->box.y, transfer->box.z,
67 rtransfer->staging_texture,
68 0, &sbox);
69
70 ctx->flush(ctx, 0, NULL);
71 }
72
73 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
74 unsigned level, unsigned layer)
75 {
76 unsigned offset = rtex->offset[level];
77
78 switch (rtex->resource.b.b.b.target) {
79 case PIPE_TEXTURE_3D:
80 case PIPE_TEXTURE_CUBE:
81 return offset + layer * rtex->layer_size[level];
82 default:
83 assert(layer == 0);
84 return offset;
85 }
86 }
87
88 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
89 enum pipe_format format,
90 unsigned array_mode)
91 {
92 struct r600_screen* rscreen = (struct r600_screen *)screen;
93 unsigned pixsize = util_format_get_blocksize(format);
94 int p_align;
95
96 switch(array_mode) {
97 case V_038000_ARRAY_1D_TILED_THIN1:
98 p_align = MAX2(8,
99 ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
100 break;
101 case V_038000_ARRAY_2D_TILED_THIN1:
102 p_align = MAX2(rscreen->tiling_info->num_banks,
103 (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
104 rscreen->tiling_info->num_banks)) * 8;
105 break;
106 case V_038000_ARRAY_LINEAR_ALIGNED:
107 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
108 break;
109 case V_038000_ARRAY_LINEAR_GENERAL:
110 default:
111 p_align = rscreen->tiling_info->group_bytes / pixsize;
112 break;
113 }
114 return p_align;
115 }
116
117 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
118 unsigned array_mode)
119 {
120 struct r600_screen* rscreen = (struct r600_screen *)screen;
121 int h_align;
122
123 switch (array_mode) {
124 case V_038000_ARRAY_2D_TILED_THIN1:
125 h_align = rscreen->tiling_info->num_channels * 8;
126 break;
127 case V_038000_ARRAY_1D_TILED_THIN1:
128 case V_038000_ARRAY_LINEAR_ALIGNED:
129 h_align = 8;
130 break;
131 case V_038000_ARRAY_LINEAR_GENERAL:
132 default:
133 h_align = 1;
134 break;
135 }
136 return h_align;
137 }
138
139 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
140 enum pipe_format format,
141 unsigned array_mode)
142 {
143 struct r600_screen* rscreen = (struct r600_screen *)screen;
144 unsigned pixsize = util_format_get_blocksize(format);
145 int p_align = r600_get_block_alignment(screen, format, array_mode);
146 int h_align = r600_get_height_alignment(screen, array_mode);
147 int b_align;
148
149 switch (array_mode) {
150 case V_038000_ARRAY_2D_TILED_THIN1:
151 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
152 p_align * pixsize * h_align);
153 break;
154 case V_038000_ARRAY_1D_TILED_THIN1:
155 case V_038000_ARRAY_LINEAR_ALIGNED:
156 case V_038000_ARRAY_LINEAR_GENERAL:
157 default:
158 b_align = rscreen->tiling_info->group_bytes;
159 break;
160 }
161 return b_align;
162 }
163
164 static unsigned mip_minify(unsigned size, unsigned level)
165 {
166 unsigned val;
167 val = u_minify(size, level);
168 if (level > 0)
169 val = util_next_power_of_two(val);
170 return val;
171 }
172
173 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
174 struct r600_resource_texture *rtex,
175 unsigned level)
176 {
177 struct pipe_resource *ptex = &rtex->resource.b.b.b;
178 unsigned nblocksx, block_align, width;
179 unsigned blocksize = util_format_get_blocksize(ptex->format);
180
181 if (rtex->pitch_override)
182 return rtex->pitch_override / blocksize;
183
184 width = mip_minify(ptex->width0, level);
185 nblocksx = util_format_get_nblocksx(ptex->format, width);
186
187 block_align = r600_get_block_alignment(screen, ptex->format,
188 rtex->array_mode[level]);
189 nblocksx = align(nblocksx, block_align);
190 return nblocksx;
191 }
192
193 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
194 struct r600_resource_texture *rtex,
195 unsigned level)
196 {
197 struct pipe_resource *ptex = &rtex->resource.b.b.b;
198 unsigned height, tile_height;
199
200 height = mip_minify(ptex->height0, level);
201 height = util_format_get_nblocksy(ptex->format, height);
202 tile_height = r600_get_height_alignment(screen,
203 rtex->array_mode[level]);
204 height = align(height, tile_height);
205 return height;
206 }
207
208 static void r600_texture_set_array_mode(struct pipe_screen *screen,
209 struct r600_resource_texture *rtex,
210 unsigned level, unsigned array_mode)
211 {
212 struct pipe_resource *ptex = &rtex->resource.b.b.b;
213
214 switch (array_mode) {
215 case V_0280A0_ARRAY_LINEAR_GENERAL:
216 case V_0280A0_ARRAY_LINEAR_ALIGNED:
217 case V_0280A0_ARRAY_1D_TILED_THIN1:
218 default:
219 rtex->array_mode[level] = array_mode;
220 break;
221 case V_0280A0_ARRAY_2D_TILED_THIN1:
222 {
223 unsigned w, h, tile_height, tile_width;
224
225 tile_height = r600_get_height_alignment(screen, array_mode);
226 tile_width = r600_get_block_alignment(screen, ptex->format, array_mode);
227
228 w = mip_minify(ptex->width0, level);
229 h = mip_minify(ptex->height0, level);
230 if (w < tile_width || h < tile_height)
231 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
232 else
233 rtex->array_mode[level] = array_mode;
234 }
235 break;
236 }
237 }
238
239 static void r600_setup_miptree(struct pipe_screen *screen,
240 struct r600_resource_texture *rtex,
241 unsigned array_mode)
242 {
243 struct pipe_resource *ptex = &rtex->resource.b.b.b;
244 struct radeon *radeon = (struct radeon *)screen->winsys;
245 enum chip_class chipc = r600_get_family_class(radeon);
246 unsigned size, layer_size, i, offset;
247 unsigned nblocksx, nblocksy;
248
249 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
250 unsigned blocksize = util_format_get_blocksize(ptex->format);
251
252 r600_texture_set_array_mode(screen, rtex, i, array_mode);
253
254 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
255 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
256
257 layer_size = nblocksx * nblocksy * blocksize;
258 if (ptex->target == PIPE_TEXTURE_CUBE) {
259 if (chipc >= R700)
260 size = layer_size * 8;
261 else
262 size = layer_size * 6;
263 }
264 else
265 size = layer_size * u_minify(ptex->depth0, i);
266 /* align base image and start of miptree */
267 if ((i == 0) || (i == 1))
268 offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
269 rtex->offset[i] = offset;
270 rtex->layer_size[i] = layer_size;
271 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
272 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
273
274 offset += size;
275 }
276 rtex->size = offset;
277 }
278
279 /* Figure out whether u_blitter will fallback to a transfer operation.
280 * If so, don't use a staging resource.
281 */
282 static boolean permit_hardware_blit(struct pipe_screen *screen,
283 const struct pipe_resource *res)
284 {
285 unsigned bind;
286
287 if (util_format_is_depth_or_stencil(res->format))
288 bind = PIPE_BIND_DEPTH_STENCIL;
289 else
290 bind = PIPE_BIND_RENDER_TARGET;
291
292 if (!screen->is_format_supported(screen,
293 res->format,
294 res->target,
295 res->nr_samples,
296 bind, 0))
297 return FALSE;
298
299 if (!screen->is_format_supported(screen,
300 res->format,
301 res->target,
302 res->nr_samples,
303 PIPE_BIND_SAMPLER_VIEW, 0))
304 return FALSE;
305
306 return TRUE;
307 }
308
309 static boolean r600_texture_get_handle(struct pipe_screen* screen,
310 struct pipe_resource *ptex,
311 struct winsys_handle *whandle)
312 {
313 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
314 struct r600_resource *resource = &rtex->resource;
315 struct radeon *radeon = (struct radeon *)screen->winsys;
316
317 return r600_bo_get_winsys_handle(radeon, resource->bo,
318 rtex->pitch_in_bytes[0], whandle);
319 }
320
321 static void r600_texture_destroy(struct pipe_screen *screen,
322 struct pipe_resource *ptex)
323 {
324 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
325 struct r600_resource *resource = &rtex->resource;
326 struct radeon *radeon = (struct radeon *)screen->winsys;
327
328 if (rtex->flushed_depth_texture)
329 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
330
331 if (resource->bo) {
332 r600_bo_reference(radeon, &resource->bo, NULL);
333 }
334 FREE(rtex);
335 }
336
337 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
338 struct pipe_resource *texture,
339 unsigned level, int layer)
340 {
341 /* FIXME */
342 return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
343 }
344
345 static const struct u_resource_vtbl r600_texture_vtbl =
346 {
347 r600_texture_get_handle, /* get_handle */
348 r600_texture_destroy, /* resource_destroy */
349 r600_texture_is_referenced, /* is_resource_referenced */
350 r600_texture_get_transfer, /* get_transfer */
351 r600_texture_transfer_destroy, /* transfer_destroy */
352 r600_texture_transfer_map, /* transfer_map */
353 u_default_transfer_flush_region,/* transfer_flush_region */
354 r600_texture_transfer_unmap, /* transfer_unmap */
355 u_default_transfer_inline_write /* transfer_inline_write */
356 };
357
358 static struct r600_resource_texture *
359 r600_texture_create_object(struct pipe_screen *screen,
360 const struct pipe_resource *base,
361 unsigned array_mode,
362 unsigned pitch_in_bytes_override,
363 unsigned max_buffer_size,
364 struct r600_bo *bo)
365 {
366 struct r600_resource_texture *rtex;
367 struct r600_resource *resource;
368 struct radeon *radeon = (struct radeon *)screen->winsys;
369
370 rtex = CALLOC_STRUCT(r600_resource_texture);
371 if (rtex == NULL)
372 return NULL;
373
374 resource = &rtex->resource;
375 resource->b.b.b = *base;
376 resource->b.b.vtbl = &r600_texture_vtbl;
377 pipe_reference_init(&resource->b.b.b.reference, 1);
378 resource->b.b.b.screen = screen;
379 resource->bo = bo;
380 rtex->pitch_override = pitch_in_bytes_override;
381 /* only mark depth textures the HW can hit as depth textures */
382 if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
383 rtex->depth = 1;
384
385 r600_setup_miptree(screen, rtex, array_mode);
386
387 resource->size = rtex->size;
388
389 if (!resource->bo) {
390 struct pipe_resource *ptex = &rtex->resource.b.b.b;
391 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
392
393 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
394 if (!resource->bo) {
395 FREE(rtex);
396 return NULL;
397 }
398 }
399 return rtex;
400 }
401
402 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
403 const struct pipe_resource *templ)
404 {
405 unsigned array_mode = 0;
406 static int force_tiling = -1;
407
408 /* Would like some magic "get_bool_option_once" routine.
409 */
410 if (force_tiling == -1)
411 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
412
413 if (force_tiling && permit_hardware_blit(screen, templ)) {
414 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
415 !(templ->bind & PIPE_BIND_SCANOUT)) {
416 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
417 }
418 }
419
420 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
421 0, 0, NULL);
422
423 }
424
425 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
426 struct pipe_resource *texture,
427 const struct pipe_surface *surf_tmpl)
428 {
429 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
430 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
431 unsigned level = surf_tmpl->u.tex.level;
432
433 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
434 if (surface == NULL)
435 return NULL;
436 /* XXX no offset */
437 /* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
438 pipe_reference_init(&surface->base.reference, 1);
439 pipe_resource_reference(&surface->base.texture, texture);
440 surface->base.context = pipe;
441 surface->base.format = surf_tmpl->format;
442 surface->base.width = mip_minify(texture->width0, level);
443 surface->base.height = mip_minify(texture->height0, level);
444 surface->base.usage = surf_tmpl->usage;
445 surface->base.texture = texture;
446 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
447 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
448 surface->base.u.tex.level = level;
449
450 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
451 rtex, level);
452 return &surface->base;
453 }
454
455 static void r600_surface_destroy(struct pipe_context *pipe,
456 struct pipe_surface *surface)
457 {
458 pipe_resource_reference(&surface->texture, NULL);
459 FREE(surface);
460 }
461
462
463 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
464 const struct pipe_resource *templ,
465 struct winsys_handle *whandle)
466 {
467 struct radeon *rw = (struct radeon*)screen->winsys;
468 struct r600_bo *bo = NULL;
469 unsigned array_mode = 0;
470
471 /* Support only 2D textures without mipmaps */
472 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
473 templ->depth0 != 1 || templ->last_level != 0)
474 return NULL;
475
476 bo = r600_bo_handle(rw, whandle->handle, &array_mode);
477 if (bo == NULL) {
478 return NULL;
479 }
480
481 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
482 whandle->stride,
483 0,
484 bo);
485 }
486
487 int r600_texture_depth_flush(struct pipe_context *ctx,
488 struct pipe_resource *texture, boolean just_create)
489 {
490 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
491 struct pipe_resource resource;
492
493 if (rtex->flushed_depth_texture)
494 goto out;
495
496 resource.target = PIPE_TEXTURE_2D;
497 resource.format = texture->format;
498 resource.width0 = texture->width0;
499 resource.height0 = texture->height0;
500 resource.depth0 = 1;
501 resource.last_level = texture->last_level;
502 resource.nr_samples = 0;
503 resource.usage = PIPE_USAGE_DYNAMIC;
504 resource.bind = 0;
505 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
506
507 resource.bind |= PIPE_BIND_DEPTH_STENCIL;
508
509 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
510 if (rtex->flushed_depth_texture == NULL) {
511 R600_ERR("failed to create temporary texture to hold untiled copy\n");
512 return -ENOMEM;
513 }
514
515 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
516 out:
517 if (just_create)
518 return 0;
519
520 /* XXX: only do this if the depth texture has actually changed:
521 */
522 r600_blit_uncompress_depth(ctx, rtex);
523 return 0;
524 }
525
526 /* Needs adjustment for pixelformat:
527 */
528 static INLINE unsigned u_box_volume( const struct pipe_box *box )
529 {
530 return box->width * box->depth * box->height;
531 };
532
533 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
534 struct pipe_resource *texture,
535 unsigned level,
536 unsigned usage,
537 const struct pipe_box *box)
538 {
539 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
540 struct pipe_resource resource;
541 struct r600_transfer *trans;
542 int r;
543 boolean use_staging_texture = FALSE;
544
545 /* We cannot map a tiled texture directly because the data is
546 * in a different order, therefore we do detiling using a blit.
547 *
548 * Also, use a temporary in GTT memory for read transfers, as
549 * the CPU is much happier reading out of cached system memory
550 * than uncached VRAM.
551 */
552 if (R600_TEX_IS_TILED(rtex, level))
553 use_staging_texture = TRUE;
554
555 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
556 use_staging_texture = TRUE;
557
558 /* XXX: Use a staging texture for uploads if the underlying BO
559 * is busy. No interface for checking that currently? so do
560 * it eagerly whenever the transfer doesn't require a readback
561 * and might block.
562 */
563 if ((usage & PIPE_TRANSFER_WRITE) &&
564 !(usage & (PIPE_TRANSFER_READ |
565 PIPE_TRANSFER_DONTBLOCK |
566 PIPE_TRANSFER_UNSYNCHRONIZED)))
567 use_staging_texture = TRUE;
568
569 if (!permit_hardware_blit(ctx->screen, texture) ||
570 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
571 use_staging_texture = FALSE;
572
573 trans = CALLOC_STRUCT(r600_transfer);
574 if (trans == NULL)
575 return NULL;
576 pipe_resource_reference(&trans->transfer.resource, texture);
577 trans->transfer.level = level;
578 trans->transfer.usage = usage;
579 trans->transfer.box = *box;
580 if (rtex->depth) {
581 /* XXX: only readback the rectangle which is being mapped?
582 */
583 /* XXX: when discard is true, no need to read back from depth texture
584 */
585 r = r600_texture_depth_flush(ctx, texture, FALSE);
586 if (r < 0) {
587 R600_ERR("failed to create temporary texture to hold untiled copy\n");
588 pipe_resource_reference(&trans->transfer.resource, NULL);
589 FREE(trans);
590 return NULL;
591 }
592 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
593 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
594 return &trans->transfer;
595 } else if (use_staging_texture) {
596 resource.target = PIPE_TEXTURE_2D;
597 resource.format = texture->format;
598 resource.width0 = box->width;
599 resource.height0 = box->height;
600 resource.depth0 = 1;
601 resource.array_size = 1;
602 resource.last_level = 0;
603 resource.nr_samples = 0;
604 resource.usage = PIPE_USAGE_STAGING;
605 resource.bind = 0;
606 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
607 /* For texture reading, the temporary (detiled) texture is used as
608 * a render target when blitting from a tiled texture. */
609 if (usage & PIPE_TRANSFER_READ) {
610 resource.bind |= PIPE_BIND_RENDER_TARGET;
611 }
612 /* For texture writing, the temporary texture is used as a sampler
613 * when blitting into a tiled texture. */
614 if (usage & PIPE_TRANSFER_WRITE) {
615 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
616 }
617 /* Create the temporary texture. */
618 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
619 if (trans->staging_texture == NULL) {
620 R600_ERR("failed to create temporary texture to hold untiled copy\n");
621 pipe_resource_reference(&trans->transfer.resource, NULL);
622 FREE(trans);
623 return NULL;
624 }
625
626 trans->transfer.stride =
627 ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
628 if (usage & PIPE_TRANSFER_READ) {
629 r600_copy_to_staging_texture(ctx, trans);
630 /* Always referenced in the blit. */
631 ctx->flush(ctx, 0, NULL);
632 }
633 return &trans->transfer;
634 }
635 trans->transfer.stride = rtex->pitch_in_bytes[level];
636 trans->offset = r600_texture_get_offset(rtex, level, box->z);
637 return &trans->transfer;
638 }
639
640 void r600_texture_transfer_destroy(struct pipe_context *ctx,
641 struct pipe_transfer *transfer)
642 {
643 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
644 struct pipe_resource *texture = transfer->resource;
645 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
646
647 if (rtransfer->staging_texture) {
648 if (transfer->usage & PIPE_TRANSFER_WRITE) {
649 r600_copy_from_staging_texture(ctx, rtransfer);
650 }
651 pipe_resource_reference(&rtransfer->staging_texture, NULL);
652 }
653
654 if (rtex->depth && !rtex->is_flushing_texture) {
655 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
656 r600_blit_push_depth(ctx, rtex);
657 }
658
659 pipe_resource_reference(&transfer->resource, NULL);
660 FREE(transfer);
661 }
662
663 void* r600_texture_transfer_map(struct pipe_context *ctx,
664 struct pipe_transfer* transfer)
665 {
666 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
667 struct r600_bo *bo;
668 enum pipe_format format = transfer->resource->format;
669 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
670 unsigned offset = 0;
671 unsigned usage = 0;
672 char *map;
673
674 if (rtransfer->staging_texture) {
675 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
676 } else {
677 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
678
679 if (rtex->flushed_depth_texture)
680 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
681 else
682 bo = ((struct r600_resource *)transfer->resource)->bo;
683
684 offset = rtransfer->offset +
685 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
686 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
687 }
688
689 if (transfer->usage & PIPE_TRANSFER_WRITE) {
690 usage |= PB_USAGE_CPU_WRITE;
691
692 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
693 }
694
695 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
696 }
697 }
698
699 if (transfer->usage & PIPE_TRANSFER_READ) {
700 usage |= PB_USAGE_CPU_READ;
701 }
702
703 if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
704 usage |= PB_USAGE_DONTBLOCK;
705 }
706
707 if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
708 usage |= PB_USAGE_UNSYNCHRONIZED;
709 }
710
711 map = r600_bo_map(radeon, bo, usage, ctx);
712 if (!map) {
713 return NULL;
714 }
715
716 return map + offset;
717 }
718
719 void r600_texture_transfer_unmap(struct pipe_context *ctx,
720 struct pipe_transfer* transfer)
721 {
722 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
723 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
724 struct r600_bo *bo;
725
726 if (rtransfer->staging_texture) {
727 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
728 } else {
729 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
730
731 if (rtex->flushed_depth_texture) {
732 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
733 } else {
734 bo = ((struct r600_resource *)transfer->resource)->bo;
735 }
736 }
737 r600_bo_unmap(radeon, bo);
738 }
739
740 void r600_init_surface_functions(struct r600_pipe_context *r600)
741 {
742 r600->context.create_surface = r600_create_surface;
743 r600->context.surface_destroy = r600_surface_destroy;
744 }
745
746 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
747 const unsigned char *swizzle_view)
748 {
749 unsigned i;
750 unsigned char swizzle[4];
751 unsigned result = 0;
752 const uint32_t swizzle_shift[4] = {
753 16, 19, 22, 25,
754 };
755 const uint32_t swizzle_bit[4] = {
756 0, 1, 2, 3,
757 };
758
759 if (swizzle_view) {
760 /* Combine two sets of swizzles. */
761 for (i = 0; i < 4; i++) {
762 swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
763 swizzle_format[swizzle_view[i]] : swizzle_view[i];
764 }
765 } else {
766 memcpy(swizzle, swizzle_format, 4);
767 }
768
769 /* Get swizzle. */
770 for (i = 0; i < 4; i++) {
771 switch (swizzle[i]) {
772 case UTIL_FORMAT_SWIZZLE_Y:
773 result |= swizzle_bit[1] << swizzle_shift[i];
774 break;
775 case UTIL_FORMAT_SWIZZLE_Z:
776 result |= swizzle_bit[2] << swizzle_shift[i];
777 break;
778 case UTIL_FORMAT_SWIZZLE_W:
779 result |= swizzle_bit[3] << swizzle_shift[i];
780 break;
781 case UTIL_FORMAT_SWIZZLE_0:
782 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
783 break;
784 case UTIL_FORMAT_SWIZZLE_1:
785 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
786 break;
787 default: /* UTIL_FORMAT_SWIZZLE_X */
788 result |= swizzle_bit[0] << swizzle_shift[i];
789 }
790 }
791 return result;
792 }
793
794 /* texture format translate */
795 uint32_t r600_translate_texformat(enum pipe_format format,
796 const unsigned char *swizzle_view,
797 uint32_t *word4_p, uint32_t *yuv_format_p)
798 {
799 uint32_t result = 0, word4 = 0, yuv_format = 0;
800 const struct util_format_description *desc;
801 boolean uniform = TRUE;
802 int i;
803 const uint32_t sign_bit[4] = {
804 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
805 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
806 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
807 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
808 };
809 desc = util_format_description(format);
810
811 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
812
813 /* Colorspace (return non-RGB formats directly). */
814 switch (desc->colorspace) {
815 /* Depth stencil formats */
816 case UTIL_FORMAT_COLORSPACE_ZS:
817 switch (format) {
818 case PIPE_FORMAT_Z16_UNORM:
819 result = FMT_16;
820 goto out_word4;
821 case PIPE_FORMAT_X24S8_USCALED:
822 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
823 case PIPE_FORMAT_Z24X8_UNORM:
824 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
825 result = FMT_8_24;
826 goto out_word4;
827 case PIPE_FORMAT_S8X24_USCALED:
828 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
829 case PIPE_FORMAT_X8Z24_UNORM:
830 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
831 result = FMT_24_8;
832 goto out_word4;
833 case PIPE_FORMAT_S8_USCALED:
834 result = FMT_8;
835 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
836 goto out_word4;
837 default:
838 goto out_unknown;
839 }
840
841 case UTIL_FORMAT_COLORSPACE_YUV:
842 yuv_format |= (1 << 30);
843 switch (format) {
844 case PIPE_FORMAT_UYVY:
845 case PIPE_FORMAT_YUYV:
846 default:
847 break;
848 }
849 goto out_unknown; /* TODO */
850
851 case UTIL_FORMAT_COLORSPACE_SRGB:
852 word4 |= S_038010_FORCE_DEGAMMA(1);
853 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
854 goto out_unknown; /* fails for some reason - TODO */
855 break;
856
857 default:
858 break;
859 }
860
861 /* S3TC formats. TODO */
862 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
863 static int r600_enable_s3tc = -1;
864
865 if (r600_enable_s3tc == -1)
866 r600_enable_s3tc =
867 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
868
869 if (!r600_enable_s3tc)
870 goto out_unknown;
871
872 switch (format) {
873 case PIPE_FORMAT_DXT1_RGB:
874 case PIPE_FORMAT_DXT1_RGBA:
875 result = FMT_BC1;
876 goto out_word4;
877 case PIPE_FORMAT_DXT3_RGBA:
878 result = FMT_BC2;
879 goto out_word4;
880 case PIPE_FORMAT_DXT5_RGBA:
881 result = FMT_BC3;
882 goto out_word4;
883 default:
884 goto out_unknown;
885 }
886 }
887
888
889 for (i = 0; i < desc->nr_channels; i++) {
890 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
891 word4 |= sign_bit[i];
892 }
893 }
894
895 /* R8G8Bx_SNORM - TODO CxV8U8 */
896
897 /* RGTC - TODO */
898
899 /* See whether the components are of the same size. */
900 for (i = 1; i < desc->nr_channels; i++) {
901 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
902 }
903
904 /* Non-uniform formats. */
905 if (!uniform) {
906 switch(desc->nr_channels) {
907 case 3:
908 if (desc->channel[0].size == 5 &&
909 desc->channel[1].size == 6 &&
910 desc->channel[2].size == 5) {
911 result = FMT_5_6_5;
912 goto out_word4;
913 }
914 goto out_unknown;
915 case 4:
916 if (desc->channel[0].size == 5 &&
917 desc->channel[1].size == 5 &&
918 desc->channel[2].size == 5 &&
919 desc->channel[3].size == 1) {
920 result = FMT_1_5_5_5;
921 goto out_word4;
922 }
923 if (desc->channel[0].size == 10 &&
924 desc->channel[1].size == 10 &&
925 desc->channel[2].size == 10 &&
926 desc->channel[3].size == 2) {
927 result = FMT_2_10_10_10;
928 goto out_word4;
929 }
930 goto out_unknown;
931 }
932 goto out_unknown;
933 }
934
935 /* Find the first non-VOID channel. */
936 for (i = 0; i < 4; i++) {
937 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
938 break;
939 }
940 }
941
942 if (i == 4)
943 goto out_unknown;
944
945 /* uniform formats */
946 switch (desc->channel[i].type) {
947 case UTIL_FORMAT_TYPE_UNSIGNED:
948 case UTIL_FORMAT_TYPE_SIGNED:
949 if (!desc->channel[i].normalized &&
950 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
951 goto out_unknown;
952 }
953
954 switch (desc->channel[i].size) {
955 case 4:
956 switch (desc->nr_channels) {
957 case 2:
958 result = FMT_4_4;
959 goto out_word4;
960 case 4:
961 result = FMT_4_4_4_4;
962 goto out_word4;
963 }
964 goto out_unknown;
965 case 8:
966 switch (desc->nr_channels) {
967 case 1:
968 result = FMT_8;
969 goto out_word4;
970 case 2:
971 result = FMT_8_8;
972 goto out_word4;
973 case 4:
974 result = FMT_8_8_8_8;
975 goto out_word4;
976 }
977 goto out_unknown;
978 case 16:
979 switch (desc->nr_channels) {
980 case 1:
981 result = FMT_16;
982 goto out_word4;
983 case 2:
984 result = FMT_16_16;
985 goto out_word4;
986 case 4:
987 result = FMT_16_16_16_16;
988 goto out_word4;
989 }
990 goto out_unknown;
991 case 32:
992 switch (desc->nr_channels) {
993 case 1:
994 result = FMT_32;
995 goto out_word4;
996 case 2:
997 result = FMT_32_32;
998 goto out_word4;
999 case 4:
1000 result = FMT_32_32_32_32;
1001 goto out_word4;
1002 }
1003 }
1004 goto out_unknown;
1005
1006 case UTIL_FORMAT_TYPE_FLOAT:
1007 switch (desc->channel[i].size) {
1008 case 16:
1009 switch (desc->nr_channels) {
1010 case 1:
1011 result = FMT_16_FLOAT;
1012 goto out_word4;
1013 case 2:
1014 result = FMT_16_16_FLOAT;
1015 goto out_word4;
1016 case 4:
1017 result = FMT_16_16_16_16_FLOAT;
1018 goto out_word4;
1019 }
1020 goto out_unknown;
1021 case 32:
1022 switch (desc->nr_channels) {
1023 case 1:
1024 result = FMT_32_FLOAT;
1025 goto out_word4;
1026 case 2:
1027 result = FMT_32_32_FLOAT;
1028 goto out_word4;
1029 case 4:
1030 result = FMT_32_32_32_32_FLOAT;
1031 goto out_word4;
1032 }
1033 }
1034
1035 }
1036 out_word4:
1037 if (word4_p)
1038 *word4_p = word4;
1039 if (yuv_format_p)
1040 *yuv_format_p = yuv_format;
1041 return result;
1042 out_unknown:
1043 // R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1044 return ~0;
1045 }