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r600g: add multi ring support with dma as first second ring v4
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34
35 /* Copy from a full GPU texture to a transfer's staging one. */
36 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
37 {
38 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
39 struct pipe_resource *dst = &rtransfer->staging->b.b;
40 struct pipe_resource *src = transfer->resource;
41
42 if (src->nr_samples <= 1) {
43 ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
44 src, transfer->level, &transfer->box);
45 } else {
46 /* Resolve the resource. */
47 struct pipe_blit_info blit;
48
49 memset(&blit, 0, sizeof(blit));
50 blit.src.resource = src;
51 blit.src.format = src->format;
52 blit.src.level = transfer->level;
53 blit.src.box = transfer->box;
54 blit.dst.resource = dst;
55 blit.dst.format = dst->format;
56 blit.dst.box.width = transfer->box.width;
57 blit.dst.box.height = transfer->box.height;
58 blit.dst.box.depth = transfer->box.depth;
59 blit.mask = PIPE_MASK_RGBA;
60 blit.filter = PIPE_TEX_FILTER_NEAREST;
61
62 ctx->blit(ctx, &blit);
63 }
64 }
65
66 /* Copy from a transfer's staging texture to a full GPU one. */
67 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
68 {
69 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
70 struct pipe_resource *texture = transfer->resource;
71 struct pipe_box sbox;
72
73 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
74
75 ctx->resource_copy_region(ctx, texture, transfer->level,
76 transfer->box.x, transfer->box.y, transfer->box.z,
77 &rtransfer->staging->b.b,
78 0, &sbox);
79 }
80
81 unsigned r600_texture_get_offset(struct r600_texture *rtex,
82 unsigned level, unsigned layer)
83 {
84 return rtex->surface.level[level].offset +
85 layer * rtex->surface.level[level].slice_size;
86 }
87
88 static int r600_init_surface(struct r600_screen *rscreen,
89 struct radeon_surface *surface,
90 const struct pipe_resource *ptex,
91 unsigned array_mode,
92 bool is_flushed_depth)
93 {
94 const struct util_format_description *desc =
95 util_format_description(ptex->format);
96 bool is_depth, is_stencil;
97
98 is_depth = util_format_has_depth(desc);
99 is_stencil = util_format_has_stencil(desc);
100
101 surface->npix_x = ptex->width0;
102 surface->npix_y = ptex->height0;
103 surface->npix_z = ptex->depth0;
104 surface->blk_w = util_format_get_blockwidth(ptex->format);
105 surface->blk_h = util_format_get_blockheight(ptex->format);
106 surface->blk_d = 1;
107 surface->array_size = 1;
108 surface->last_level = ptex->last_level;
109
110 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
111 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
112 surface->bpe = 4; /* stencil is allocated separately on evergreen */
113 } else {
114 surface->bpe = util_format_get_blocksize(ptex->format);
115 /* align byte per element on dword */
116 if (surface->bpe == 3) {
117 surface->bpe = 4;
118 }
119 }
120
121 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
122 surface->flags = 0;
123
124 switch (array_mode) {
125 case V_038000_ARRAY_1D_TILED_THIN1:
126 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
127 break;
128 case V_038000_ARRAY_2D_TILED_THIN1:
129 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
130 break;
131 case V_038000_ARRAY_LINEAR_ALIGNED:
132 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
133 break;
134 case V_038000_ARRAY_LINEAR_GENERAL:
135 default:
136 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
137 break;
138 }
139 switch (ptex->target) {
140 case PIPE_TEXTURE_1D:
141 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
142 break;
143 case PIPE_TEXTURE_RECT:
144 case PIPE_TEXTURE_2D:
145 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
146 break;
147 case PIPE_TEXTURE_3D:
148 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
149 break;
150 case PIPE_TEXTURE_1D_ARRAY:
151 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
152 surface->array_size = ptex->array_size;
153 break;
154 case PIPE_TEXTURE_2D_ARRAY:
155 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d layout for now */
156 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
157 surface->array_size = ptex->array_size;
158 break;
159 case PIPE_TEXTURE_CUBE:
160 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
161 break;
162 case PIPE_BUFFER:
163 default:
164 return -EINVAL;
165 }
166 if (ptex->bind & PIPE_BIND_SCANOUT) {
167 surface->flags |= RADEON_SURF_SCANOUT;
168 }
169
170 if (!is_flushed_depth && is_depth) {
171 surface->flags |= RADEON_SURF_ZBUFFER;
172
173 if (is_stencil) {
174 surface->flags |= RADEON_SURF_SBUFFER |
175 RADEON_SURF_HAS_SBUFFER_MIPTREE;
176 }
177 }
178 return 0;
179 }
180
181 static int r600_setup_surface(struct pipe_screen *screen,
182 struct r600_texture *rtex,
183 unsigned pitch_in_bytes_override)
184 {
185 struct pipe_resource *ptex = &rtex->resource.b.b;
186 struct r600_screen *rscreen = (struct r600_screen*)screen;
187 unsigned i;
188 int r;
189
190 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
191 if (r) {
192 return r;
193 }
194 rtex->size = rtex->surface.bo_size;
195 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
196 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
197 * for those
198 */
199 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
200 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
201 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
202 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
203 rtex->surface.stencil_offset =
204 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
205 }
206 }
207 for (i = 0; i <= ptex->last_level; i++) {
208 switch (rtex->surface.level[i].mode) {
209 case RADEON_SURF_MODE_LINEAR_ALIGNED:
210 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
211 break;
212 case RADEON_SURF_MODE_1D:
213 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
214 break;
215 case RADEON_SURF_MODE_2D:
216 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
217 break;
218 default:
219 case RADEON_SURF_MODE_LINEAR:
220 rtex->array_mode[i] = 0;
221 break;
222 }
223 }
224 return 0;
225 }
226
227 static boolean r600_texture_get_handle(struct pipe_screen* screen,
228 struct pipe_resource *ptex,
229 struct winsys_handle *whandle)
230 {
231 struct r600_texture *rtex = (struct r600_texture*)ptex;
232 struct r600_resource *resource = &rtex->resource;
233 struct radeon_surface *surface = &rtex->surface;
234 struct r600_screen *rscreen = (struct r600_screen*)screen;
235
236 rscreen->ws->buffer_set_tiling(resource->buf,
237 NULL,
238 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
239 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
240 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
241 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
242 surface->bankw, surface->bankh,
243 surface->tile_split,
244 surface->stencil_tile_split,
245 surface->mtilea,
246 rtex->surface.level[0].pitch_bytes);
247
248 return rscreen->ws->buffer_get_handle(resource->buf,
249 rtex->surface.level[0].pitch_bytes, whandle);
250 }
251
252 static void r600_texture_destroy(struct pipe_screen *screen,
253 struct pipe_resource *ptex)
254 {
255 struct r600_texture *rtex = (struct r600_texture*)ptex;
256 struct r600_resource *resource = &rtex->resource;
257
258 if (rtex->flushed_depth_texture)
259 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
260
261 pb_reference(&resource->buf, NULL);
262 FREE(rtex);
263 }
264
265 static const struct u_resource_vtbl r600_texture_vtbl;
266
267 /* The number of samples can be specified independently of the texture. */
268 void r600_texture_get_fmask_info(struct r600_screen *rscreen,
269 struct r600_texture *rtex,
270 unsigned nr_samples,
271 struct r600_fmask_info *out)
272 {
273 /* FMASK is allocated pretty much like an ordinary texture.
274 * Here we use bpe in the units of bits, not bytes. */
275 struct radeon_surface fmask = rtex->surface;
276
277 switch (nr_samples) {
278 case 2:
279 /* This should be 8,1, but we should set nsamples > 1
280 * for the allocator to treat it as a multisample surface.
281 * Let's set 4,2 then. */
282 case 4:
283 fmask.bpe = 4;
284 fmask.nsamples = 2;
285 break;
286 case 8:
287 fmask.bpe = 8;
288 fmask.nsamples = 4;
289 break;
290 case 16:
291 fmask.bpe = 16;
292 fmask.nsamples = 4;
293 break;
294 default:
295 R600_ERR("Invalid sample count for FMASK allocation.\n");
296 return;
297 }
298
299 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
300 if (rscreen->chip_class <= R700) {
301 fmask.bpe *= 2;
302 }
303
304 if (rscreen->chip_class >= EVERGREEN) {
305 fmask.bankh = nr_samples <= 4 ? 4 : 1;
306 }
307
308 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
309 R600_ERR("Got error in surface_init while allocating FMASK.\n");
310 return;
311 }
312 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
313
314 out->bank_height = fmask.bankh;
315 out->alignment = MAX2(256, fmask.bo_alignment);
316 out->size = (fmask.bo_size + 7) / 8;
317 }
318
319 static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
320 struct r600_texture *rtex)
321 {
322 struct r600_fmask_info fmask;
323
324 r600_texture_get_fmask_info(rscreen, rtex,
325 rtex->resource.b.b.nr_samples, &fmask);
326
327 rtex->fmask_bank_height = fmask.bank_height;
328 rtex->fmask_offset = align(rtex->size, fmask.alignment);
329 rtex->fmask_size = fmask.size;
330 rtex->size = rtex->fmask_offset + rtex->fmask_size;
331 #if 0
332 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
333 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
334 #endif
335 }
336
337 void r600_texture_get_cmask_info(struct r600_screen *rscreen,
338 struct r600_texture *rtex,
339 struct r600_cmask_info *out)
340 {
341 unsigned cmask_tile_width = 8;
342 unsigned cmask_tile_height = 8;
343 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
344 unsigned element_bits = 4;
345 unsigned cmask_cache_bits = 1024;
346 unsigned num_pipes = rscreen->tiling_info.num_channels;
347 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
348
349 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
350 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
351 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
352 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
353 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
354
355 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
356 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
357
358 unsigned base_align = num_pipes * pipe_interleave_bytes;
359 unsigned slice_bytes =
360 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
361
362 assert(macro_tile_width % 128 == 0);
363 assert(macro_tile_height % 128 == 0);
364
365 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
366 out->alignment = MAX2(256, base_align);
367 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
368 }
369
370 static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
371 struct r600_texture *rtex)
372 {
373 struct r600_cmask_info cmask;
374
375 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
376
377 rtex->cmask_slice_tile_max = cmask.slice_tile_max;
378 rtex->cmask_offset = align(rtex->size, cmask.alignment);
379 rtex->cmask_size = cmask.size;
380 rtex->size = rtex->cmask_offset + rtex->cmask_size;
381 #if 0
382 printf("CMASK: macro tile width = %u, macro tile height = %u, "
383 "pitch elements = %u, height = %u, slice tile max = %u\n",
384 macro_tile_width, macro_tile_height, pitch_elements, height,
385 rtex->cmask_slice_tile_max);
386 #endif
387 }
388
389 DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "R600_PRINT_TEXDEPTH", FALSE);
390
391 static struct r600_texture *
392 r600_texture_create_object(struct pipe_screen *screen,
393 const struct pipe_resource *base,
394 unsigned pitch_in_bytes_override,
395 struct pb_buffer *buf,
396 struct radeon_surface *surface)
397 {
398 struct r600_texture *rtex;
399 struct r600_resource *resource;
400 struct r600_screen *rscreen = (struct r600_screen*)screen;
401 int r;
402
403 rtex = CALLOC_STRUCT(r600_texture);
404 if (rtex == NULL)
405 return NULL;
406
407 resource = &rtex->resource;
408 resource->b.b = *base;
409 resource->b.vtbl = &r600_texture_vtbl;
410 pipe_reference_init(&resource->b.b.reference, 1);
411 resource->b.b.screen = screen;
412 rtex->pitch_override = pitch_in_bytes_override;
413
414 /* don't include stencil-only formats which we don't support for rendering */
415 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
416
417 rtex->surface = *surface;
418 r = r600_setup_surface(screen, rtex,
419 pitch_in_bytes_override);
420 if (r) {
421 FREE(rtex);
422 return NULL;
423 }
424
425 if (base->nr_samples > 1 && !rtex->is_depth && !buf) {
426 r600_texture_allocate_cmask(rscreen, rtex);
427 r600_texture_allocate_fmask(rscreen, rtex);
428 }
429
430 if (!rtex->is_depth && base->nr_samples > 1 &&
431 (!rtex->fmask_size || !rtex->cmask_size)) {
432 FREE(rtex);
433 return NULL;
434 }
435
436 /* Tiled depth textures utilize the non-displayable tile order. */
437 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
438
439 /* only enable hyperz for PIPE_TEXTURE_2D not for PIPE_TEXTURE_2D_ARRAY
440 * Thought it might still be interessting to use hyperz for texture
441 * array without using fast clear features
442 */
443 rtex->htile = NULL;
444 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER | R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
445 util_format_is_depth_or_stencil(base->format) &&
446 rscreen->use_hyperz &&
447 base->target == PIPE_TEXTURE_2D &&
448 rtex->surface.level[0].nblk_x >= 32 &&
449 rtex->surface.level[0].nblk_y >= 32) {
450 unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
451 unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
452 unsigned htile_size;
453 unsigned npipes = rscreen->info.r600_num_tile_pipes;
454
455 /* this alignment and htile size only apply to linear htile buffer */
456 sw = align(sw, 16 << 3);
457 sh = align(sh, npipes << 3);
458 htile_size = (sw >> 3) * (sh >> 3) * 4;
459 /* must be aligned with 2K * npipes */
460 htile_size = align(htile_size, (2 << 10) * npipes);
461
462 rtex->htile = (struct r600_resource*)pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
463 PIPE_USAGE_STATIC, htile_size);
464 if (rtex->htile == NULL) {
465 /* this is not a fatal error as we can still keep rendering
466 * without htile buffer
467 */
468 R600_ERR("r600: failed to create bo for htile buffers\n");
469 } else {
470 void *ptr;
471 ptr = rscreen->ws->buffer_map(rtex->htile->cs_buf, NULL, PIPE_TRANSFER_WRITE);
472 memset(ptr, 0x0, htile_size);
473 rscreen->ws->buffer_unmap(rtex->htile->cs_buf);
474 }
475 }
476
477 /* Now create the backing buffer. */
478 if (!buf) {
479 unsigned base_align = rtex->surface.bo_alignment;
480 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
481
482 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
483 FREE(rtex);
484 return NULL;
485 }
486 } else {
487 /* This is usually the window framebuffer. We want it in VRAM, always. */
488 resource->buf = buf;
489 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
490 resource->domains = RADEON_DOMAIN_VRAM;
491 }
492
493 if (rtex->cmask_size) {
494 /* Initialize the cmask to 0xCC (= compressed state). */
495 char *ptr = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE);
496 memset(ptr + rtex->cmask_offset, 0xCC, rtex->cmask_size);
497 rscreen->ws->buffer_unmap(resource->cs_buf);
498 }
499
500 if (debug_get_option_print_texdepth() && rtex->is_depth && rtex->non_disp_tiling) {
501 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
502 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
503 "bpe=%u, nsamples=%u, flags=%u\n",
504 rtex->surface.npix_x, rtex->surface.npix_y,
505 rtex->surface.npix_z, rtex->surface.blk_w,
506 rtex->surface.blk_h, rtex->surface.blk_d,
507 rtex->surface.array_size, rtex->surface.last_level,
508 rtex->surface.bpe, rtex->surface.nsamples,
509 rtex->surface.flags);
510 if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
511 for (int i = 0; i <= rtex->surface.last_level; i++) {
512 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
513 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
514 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
515 i, (unsigned long long)rtex->surface.level[i].offset,
516 (unsigned long long)rtex->surface.level[i].slice_size,
517 u_minify(rtex->resource.b.b.width0, i),
518 u_minify(rtex->resource.b.b.height0, i),
519 u_minify(rtex->resource.b.b.depth0, i),
520 rtex->surface.level[i].nblk_x,
521 rtex->surface.level[i].nblk_y,
522 rtex->surface.level[i].nblk_z,
523 rtex->surface.level[i].pitch_bytes,
524 rtex->surface.level[i].mode);
525 }
526 }
527 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
528 for (int i = 0; i <= rtex->surface.last_level; i++) {
529 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
530 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
531 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
532 i, (unsigned long long)rtex->surface.stencil_level[i].offset,
533 (unsigned long long)rtex->surface.stencil_level[i].slice_size,
534 u_minify(rtex->resource.b.b.width0, i),
535 u_minify(rtex->resource.b.b.height0, i),
536 u_minify(rtex->resource.b.b.depth0, i),
537 rtex->surface.stencil_level[i].nblk_x,
538 rtex->surface.stencil_level[i].nblk_y,
539 rtex->surface.stencil_level[i].nblk_z,
540 rtex->surface.stencil_level[i].pitch_bytes,
541 rtex->surface.stencil_level[i].mode);
542 }
543 }
544 }
545 return rtex;
546 }
547
548 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
549 const struct pipe_resource *templ)
550 {
551 struct r600_screen *rscreen = (struct r600_screen*)screen;
552 struct radeon_surface surface;
553 const struct util_format_description *desc = util_format_description(templ->format);
554 unsigned array_mode;
555 int r;
556
557 /* Default tiling mode for staging textures. */
558 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
559
560 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
561 * because 422 formats are used for videos, which prefer linear buffers
562 * for fast uploads anyway. */
563 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
564 desc->layout != UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
565 if (templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) {
566 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
567 } else if (!(templ->bind & PIPE_BIND_SCANOUT) &&
568 templ->usage != PIPE_USAGE_STAGING &&
569 templ->usage != PIPE_USAGE_STREAM &&
570 templ->target != PIPE_TEXTURE_1D &&
571 templ->target != PIPE_TEXTURE_1D_ARRAY &&
572 templ->height0 > 3) {
573 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
574 } else if (util_format_is_compressed(templ->format)) {
575 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
576 }
577 }
578
579 r = r600_init_surface(rscreen, &surface, templ, array_mode,
580 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
581 if (r) {
582 return NULL;
583 }
584 r = rscreen->ws->surface_best(rscreen->ws, &surface);
585 if (r) {
586 return NULL;
587 }
588 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
589 0, NULL, &surface);
590 }
591
592 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
593 struct pipe_resource *texture,
594 const struct pipe_surface *templ,
595 unsigned width, unsigned height)
596 {
597 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
598
599 assert(templ->u.tex.first_layer <= u_max_layer(texture, templ->u.tex.level));
600 assert(templ->u.tex.last_layer <= u_max_layer(texture, templ->u.tex.level));
601 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
602 if (surface == NULL)
603 return NULL;
604 pipe_reference_init(&surface->base.reference, 1);
605 pipe_resource_reference(&surface->base.texture, texture);
606 surface->base.context = pipe;
607 surface->base.format = templ->format;
608 surface->base.width = width;
609 surface->base.height = height;
610 surface->base.u = templ->u;
611 return &surface->base;
612 }
613
614 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
615 struct pipe_resource *tex,
616 const struct pipe_surface *templ)
617 {
618 unsigned level = templ->u.tex.level;
619
620 return r600_create_surface_custom(pipe, tex, templ,
621 u_minify(tex->width0, level),
622 u_minify(tex->height0, level));
623 }
624
625 static void r600_surface_destroy(struct pipe_context *pipe,
626 struct pipe_surface *surface)
627 {
628 struct r600_surface *surf = (struct r600_surface*)surface;
629 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
630 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
631 pipe_resource_reference(&surface->texture, NULL);
632 FREE(surface);
633 }
634
635 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
636 const struct pipe_resource *templ,
637 struct winsys_handle *whandle)
638 {
639 struct r600_screen *rscreen = (struct r600_screen*)screen;
640 struct pb_buffer *buf = NULL;
641 unsigned stride = 0;
642 unsigned array_mode = 0;
643 enum radeon_bo_layout micro, macro;
644 struct radeon_surface surface;
645 int r;
646
647 /* Support only 2D textures without mipmaps */
648 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
649 templ->depth0 != 1 || templ->last_level != 0)
650 return NULL;
651
652 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
653 if (!buf)
654 return NULL;
655
656 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
657 &surface.bankw, &surface.bankh,
658 &surface.tile_split,
659 &surface.stencil_tile_split,
660 &surface.mtilea);
661
662 if (macro == RADEON_LAYOUT_TILED)
663 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
664 else if (micro == RADEON_LAYOUT_TILED)
665 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
666 else
667 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
668
669 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
670 if (r) {
671 return NULL;
672 }
673 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
674 stride, buf, &surface);
675 }
676
677 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
678 struct pipe_resource *texture,
679 struct r600_texture **staging)
680 {
681 struct r600_texture *rtex = (struct r600_texture*)texture;
682 struct pipe_resource resource;
683 struct r600_texture **flushed_depth_texture = staging ?
684 staging : &rtex->flushed_depth_texture;
685
686 if (!staging && rtex->flushed_depth_texture)
687 return true; /* it's ready */
688
689 resource.target = texture->target;
690 resource.format = texture->format;
691 resource.width0 = texture->width0;
692 resource.height0 = texture->height0;
693 resource.depth0 = texture->depth0;
694 resource.array_size = texture->array_size;
695 resource.last_level = texture->last_level;
696 resource.nr_samples = texture->nr_samples;
697 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
698 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
699 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
700
701 if (staging)
702 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
703
704 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
705 if (*flushed_depth_texture == NULL) {
706 R600_ERR("failed to create temporary texture to hold flushed depth\n");
707 return false;
708 }
709
710 (*flushed_depth_texture)->is_flushing_texture = TRUE;
711 (*flushed_depth_texture)->non_disp_tiling = false;
712 return true;
713 }
714
715 static void *r600_texture_transfer_map(struct pipe_context *ctx,
716 struct pipe_resource *texture,
717 unsigned level,
718 unsigned usage,
719 const struct pipe_box *box,
720 struct pipe_transfer **ptransfer)
721 {
722 struct r600_context *rctx = (struct r600_context*)ctx;
723 struct r600_texture *rtex = (struct r600_texture*)texture;
724 struct r600_transfer *trans;
725 boolean use_staging_texture = FALSE;
726 enum pipe_format format = texture->format;
727 struct r600_resource *buf;
728 unsigned offset = 0;
729 char *map;
730
731 if ((texture->bind & PIPE_BIND_GLOBAL) && texture->target == PIPE_BUFFER) {
732 return r600_compute_global_transfer_map(ctx, texture, level, usage, box, ptransfer);
733 }
734
735 /* We cannot map a tiled texture directly because the data is
736 * in a different order, therefore we do detiling using a blit.
737 *
738 * Also, use a temporary in GTT memory for read transfers, as
739 * the CPU is much happier reading out of cached system memory
740 * than uncached VRAM.
741 */
742 if (R600_TEX_IS_TILED(rtex, level)) {
743 use_staging_texture = TRUE;
744 }
745
746 /* Use a staging texture for uploads if the underlying BO is busy. */
747 if (!(usage & PIPE_TRANSFER_READ) &&
748 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
749 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
750 use_staging_texture = TRUE;
751 }
752
753 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
754 use_staging_texture = FALSE;
755 }
756
757 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
758 return NULL;
759 }
760
761 trans = CALLOC_STRUCT(r600_transfer);
762 if (trans == NULL)
763 return NULL;
764 trans->transfer.resource = texture;
765 trans->transfer.level = level;
766 trans->transfer.usage = usage;
767 trans->transfer.box = *box;
768 if (rtex->is_depth) {
769 /* XXX: only readback the rectangle which is being mapped?
770 */
771 /* XXX: when discard is true, no need to read back from depth texture
772 */
773 struct r600_texture *staging_depth;
774
775 assert(rtex->resource.b.b.nr_samples <= 1);
776 if (rtex->resource.b.b.nr_samples > 1) {
777 R600_ERR("mapping MSAA zbuffer unimplemented\n");
778 FREE(trans);
779 return NULL;
780 }
781
782 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
783 R600_ERR("failed to create temporary texture to hold untiled copy\n");
784 FREE(trans);
785 return NULL;
786 }
787
788 r600_blit_decompress_depth(ctx, rtex, staging_depth,
789 level, level,
790 box->z, box->z + box->depth - 1,
791 0, 0);
792
793 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
794 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
795 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
796 trans->staging = (struct r600_resource*)staging_depth;
797 } else if (use_staging_texture) {
798 struct pipe_resource resource;
799 struct r600_texture *staging;
800
801 memset(&resource, 0, sizeof(resource));
802 resource.format = texture->format;
803 resource.width0 = box->width;
804 resource.height0 = box->height;
805 resource.depth0 = 1;
806 resource.array_size = 1;
807 resource.usage = PIPE_USAGE_STAGING;
808 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
809
810 /* We must set the correct texture target and dimensions if needed for a 3D transfer. */
811 if (box->depth > 1 && u_max_layer(texture, level) > 0)
812 resource.target = texture->target;
813 else
814 resource.target = PIPE_TEXTURE_2D;
815
816 switch (resource.target) {
817 case PIPE_TEXTURE_1D_ARRAY:
818 case PIPE_TEXTURE_2D_ARRAY:
819 case PIPE_TEXTURE_CUBE_ARRAY:
820 resource.array_size = box->depth;
821 break;
822 case PIPE_TEXTURE_3D:
823 resource.depth0 = box->depth;
824 break;
825 default:;
826 }
827
828
829 /* Create the temporary texture. */
830 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
831 if (staging == NULL) {
832 R600_ERR("failed to create temporary texture to hold untiled copy\n");
833 FREE(trans);
834 return NULL;
835 }
836 trans->staging = &staging->resource;
837 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
838 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
839 if (usage & PIPE_TRANSFER_READ) {
840 r600_copy_to_staging_texture(ctx, trans);
841 /* flush gfx & dma ring, order does not matter as only one can be live */
842 rctx->rings.dma.flush(rctx, 0);
843 rctx->rings.gfx.flush(rctx, 0);
844 }
845 } else {
846 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
847 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
848 trans->offset = r600_texture_get_offset(rtex, level, box->z);
849 }
850
851 if (trans->staging) {
852 buf = trans->staging;
853 } else {
854 buf = &rtex->resource;
855 }
856
857 if (rtex->is_depth || !trans->staging)
858 offset = trans->offset +
859 box->y / util_format_get_blockheight(format) * trans->transfer.stride +
860 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
861
862 if (!(map = r600_buffer_mmap_sync_with_rings(rctx, buf, usage))) {
863 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
864 FREE(trans);
865 return NULL;
866 }
867
868 *ptransfer = &trans->transfer;
869 return map + offset;
870 }
871
872 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
873 struct pipe_transfer* transfer)
874 {
875 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
876 struct r600_context *rctx = (struct r600_context*)ctx;
877 struct radeon_winsys_cs_handle *buf;
878 struct pipe_resource *texture = transfer->resource;
879 struct r600_texture *rtex = (struct r600_texture*)texture;
880
881 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
882 return r600_compute_global_transfer_unmap(ctx, transfer);
883 }
884
885 if (rtransfer->staging) {
886 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
887 } else {
888 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
889 }
890 rctx->ws->buffer_unmap(buf);
891
892 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
893 if (rtex->is_depth) {
894 ctx->resource_copy_region(ctx, texture, transfer->level,
895 transfer->box.x, transfer->box.y, transfer->box.z,
896 &rtransfer->staging->b.b, transfer->level,
897 &transfer->box);
898 } else {
899 r600_copy_from_staging_texture(ctx, rtransfer);
900 }
901 }
902
903 if (rtransfer->staging)
904 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
905
906 FREE(transfer);
907 }
908
909 void r600_init_surface_functions(struct r600_context *r600)
910 {
911 r600->context.create_surface = r600_create_surface;
912 r600->context.surface_destroy = r600_surface_destroy;
913 }
914
915 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
916 const unsigned char *swizzle_view,
917 boolean vtx)
918 {
919 unsigned i;
920 unsigned char swizzle[4];
921 unsigned result = 0;
922 const uint32_t tex_swizzle_shift[4] = {
923 16, 19, 22, 25,
924 };
925 const uint32_t vtx_swizzle_shift[4] = {
926 3, 6, 9, 12,
927 };
928 const uint32_t swizzle_bit[4] = {
929 0, 1, 2, 3,
930 };
931 const uint32_t *swizzle_shift = tex_swizzle_shift;
932
933 if (vtx)
934 swizzle_shift = vtx_swizzle_shift;
935
936 if (swizzle_view) {
937 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
938 } else {
939 memcpy(swizzle, swizzle_format, 4);
940 }
941
942 /* Get swizzle. */
943 for (i = 0; i < 4; i++) {
944 switch (swizzle[i]) {
945 case UTIL_FORMAT_SWIZZLE_Y:
946 result |= swizzle_bit[1] << swizzle_shift[i];
947 break;
948 case UTIL_FORMAT_SWIZZLE_Z:
949 result |= swizzle_bit[2] << swizzle_shift[i];
950 break;
951 case UTIL_FORMAT_SWIZZLE_W:
952 result |= swizzle_bit[3] << swizzle_shift[i];
953 break;
954 case UTIL_FORMAT_SWIZZLE_0:
955 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
956 break;
957 case UTIL_FORMAT_SWIZZLE_1:
958 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
959 break;
960 default: /* UTIL_FORMAT_SWIZZLE_X */
961 result |= swizzle_bit[0] << swizzle_shift[i];
962 }
963 }
964 return result;
965 }
966
967 /* texture format translate */
968 uint32_t r600_translate_texformat(struct pipe_screen *screen,
969 enum pipe_format format,
970 const unsigned char *swizzle_view,
971 uint32_t *word4_p, uint32_t *yuv_format_p)
972 {
973 uint32_t result = 0, word4 = 0, yuv_format = 0;
974 const struct util_format_description *desc;
975 boolean uniform = TRUE;
976 static int r600_enable_s3tc = -1;
977 bool is_srgb_valid = FALSE;
978
979 int i;
980 const uint32_t sign_bit[4] = {
981 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
982 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
983 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
984 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
985 };
986 desc = util_format_description(format);
987
988 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
989
990 /* Colorspace (return non-RGB formats directly). */
991 switch (desc->colorspace) {
992 /* Depth stencil formats */
993 case UTIL_FORMAT_COLORSPACE_ZS:
994 switch (format) {
995 case PIPE_FORMAT_Z16_UNORM:
996 result = FMT_16;
997 goto out_word4;
998 case PIPE_FORMAT_X24S8_UINT:
999 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1000 case PIPE_FORMAT_Z24X8_UNORM:
1001 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1002 result = FMT_8_24;
1003 goto out_word4;
1004 case PIPE_FORMAT_S8X24_UINT:
1005 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1006 case PIPE_FORMAT_X8Z24_UNORM:
1007 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1008 result = FMT_24_8;
1009 goto out_word4;
1010 case PIPE_FORMAT_S8_UINT:
1011 result = FMT_8;
1012 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1013 goto out_word4;
1014 case PIPE_FORMAT_Z32_FLOAT:
1015 result = FMT_32_FLOAT;
1016 goto out_word4;
1017 case PIPE_FORMAT_X32_S8X24_UINT:
1018 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1019 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1020 result = FMT_X24_8_32_FLOAT;
1021 goto out_word4;
1022 default:
1023 goto out_unknown;
1024 }
1025
1026 case UTIL_FORMAT_COLORSPACE_YUV:
1027 yuv_format |= (1 << 30);
1028 switch (format) {
1029 case PIPE_FORMAT_UYVY:
1030 case PIPE_FORMAT_YUYV:
1031 default:
1032 break;
1033 }
1034 goto out_unknown; /* XXX */
1035
1036 case UTIL_FORMAT_COLORSPACE_SRGB:
1037 word4 |= S_038010_FORCE_DEGAMMA(1);
1038 break;
1039
1040 default:
1041 break;
1042 }
1043
1044 if (r600_enable_s3tc == -1) {
1045 struct r600_screen *rscreen = (struct r600_screen *)screen;
1046 if (rscreen->info.drm_minor >= 9)
1047 r600_enable_s3tc = 1;
1048 else
1049 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
1050 }
1051
1052 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1053 if (!r600_enable_s3tc)
1054 goto out_unknown;
1055
1056 switch (format) {
1057 case PIPE_FORMAT_RGTC1_SNORM:
1058 case PIPE_FORMAT_LATC1_SNORM:
1059 word4 |= sign_bit[0];
1060 case PIPE_FORMAT_RGTC1_UNORM:
1061 case PIPE_FORMAT_LATC1_UNORM:
1062 result = FMT_BC4;
1063 goto out_word4;
1064 case PIPE_FORMAT_RGTC2_SNORM:
1065 case PIPE_FORMAT_LATC2_SNORM:
1066 word4 |= sign_bit[0] | sign_bit[1];
1067 case PIPE_FORMAT_RGTC2_UNORM:
1068 case PIPE_FORMAT_LATC2_UNORM:
1069 result = FMT_BC5;
1070 goto out_word4;
1071 default:
1072 goto out_unknown;
1073 }
1074 }
1075
1076 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1077
1078 if (!r600_enable_s3tc)
1079 goto out_unknown;
1080
1081 if (!util_format_s3tc_enabled) {
1082 goto out_unknown;
1083 }
1084
1085 switch (format) {
1086 case PIPE_FORMAT_DXT1_RGB:
1087 case PIPE_FORMAT_DXT1_RGBA:
1088 case PIPE_FORMAT_DXT1_SRGB:
1089 case PIPE_FORMAT_DXT1_SRGBA:
1090 result = FMT_BC1;
1091 is_srgb_valid = TRUE;
1092 goto out_word4;
1093 case PIPE_FORMAT_DXT3_RGBA:
1094 case PIPE_FORMAT_DXT3_SRGBA:
1095 result = FMT_BC2;
1096 is_srgb_valid = TRUE;
1097 goto out_word4;
1098 case PIPE_FORMAT_DXT5_RGBA:
1099 case PIPE_FORMAT_DXT5_SRGBA:
1100 result = FMT_BC3;
1101 is_srgb_valid = TRUE;
1102 goto out_word4;
1103 default:
1104 goto out_unknown;
1105 }
1106 }
1107
1108 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1109 switch (format) {
1110 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1111 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1112 result = FMT_GB_GR;
1113 goto out_word4;
1114 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1115 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1116 result = FMT_BG_RG;
1117 goto out_word4;
1118 default:
1119 goto out_unknown;
1120 }
1121 }
1122
1123 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1124 result = FMT_5_9_9_9_SHAREDEXP;
1125 goto out_word4;
1126 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1127 result = FMT_10_11_11_FLOAT;
1128 goto out_word4;
1129 }
1130
1131
1132 for (i = 0; i < desc->nr_channels; i++) {
1133 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1134 word4 |= sign_bit[i];
1135 }
1136 }
1137
1138 /* R8G8Bx_SNORM - XXX CxV8U8 */
1139
1140 /* See whether the components are of the same size. */
1141 for (i = 1; i < desc->nr_channels; i++) {
1142 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1143 }
1144
1145 /* Non-uniform formats. */
1146 if (!uniform) {
1147 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1148 desc->channel[0].pure_integer)
1149 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1150 switch(desc->nr_channels) {
1151 case 3:
1152 if (desc->channel[0].size == 5 &&
1153 desc->channel[1].size == 6 &&
1154 desc->channel[2].size == 5) {
1155 result = FMT_5_6_5;
1156 goto out_word4;
1157 }
1158 goto out_unknown;
1159 case 4:
1160 if (desc->channel[0].size == 5 &&
1161 desc->channel[1].size == 5 &&
1162 desc->channel[2].size == 5 &&
1163 desc->channel[3].size == 1) {
1164 result = FMT_1_5_5_5;
1165 goto out_word4;
1166 }
1167 if (desc->channel[0].size == 10 &&
1168 desc->channel[1].size == 10 &&
1169 desc->channel[2].size == 10 &&
1170 desc->channel[3].size == 2) {
1171 result = FMT_2_10_10_10;
1172 goto out_word4;
1173 }
1174 goto out_unknown;
1175 }
1176 goto out_unknown;
1177 }
1178
1179 /* Find the first non-VOID channel. */
1180 for (i = 0; i < 4; i++) {
1181 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1182 break;
1183 }
1184 }
1185
1186 if (i == 4)
1187 goto out_unknown;
1188
1189 /* uniform formats */
1190 switch (desc->channel[i].type) {
1191 case UTIL_FORMAT_TYPE_UNSIGNED:
1192 case UTIL_FORMAT_TYPE_SIGNED:
1193 #if 0
1194 if (!desc->channel[i].normalized &&
1195 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1196 goto out_unknown;
1197 }
1198 #endif
1199 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1200 desc->channel[i].pure_integer)
1201 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1202
1203 switch (desc->channel[i].size) {
1204 case 4:
1205 switch (desc->nr_channels) {
1206 case 2:
1207 result = FMT_4_4;
1208 goto out_word4;
1209 case 4:
1210 result = FMT_4_4_4_4;
1211 goto out_word4;
1212 }
1213 goto out_unknown;
1214 case 8:
1215 switch (desc->nr_channels) {
1216 case 1:
1217 result = FMT_8;
1218 goto out_word4;
1219 case 2:
1220 result = FMT_8_8;
1221 goto out_word4;
1222 case 4:
1223 result = FMT_8_8_8_8;
1224 is_srgb_valid = TRUE;
1225 goto out_word4;
1226 }
1227 goto out_unknown;
1228 case 16:
1229 switch (desc->nr_channels) {
1230 case 1:
1231 result = FMT_16;
1232 goto out_word4;
1233 case 2:
1234 result = FMT_16_16;
1235 goto out_word4;
1236 case 4:
1237 result = FMT_16_16_16_16;
1238 goto out_word4;
1239 }
1240 goto out_unknown;
1241 case 32:
1242 switch (desc->nr_channels) {
1243 case 1:
1244 result = FMT_32;
1245 goto out_word4;
1246 case 2:
1247 result = FMT_32_32;
1248 goto out_word4;
1249 case 4:
1250 result = FMT_32_32_32_32;
1251 goto out_word4;
1252 }
1253 }
1254 goto out_unknown;
1255
1256 case UTIL_FORMAT_TYPE_FLOAT:
1257 switch (desc->channel[i].size) {
1258 case 16:
1259 switch (desc->nr_channels) {
1260 case 1:
1261 result = FMT_16_FLOAT;
1262 goto out_word4;
1263 case 2:
1264 result = FMT_16_16_FLOAT;
1265 goto out_word4;
1266 case 4:
1267 result = FMT_16_16_16_16_FLOAT;
1268 goto out_word4;
1269 }
1270 goto out_unknown;
1271 case 32:
1272 switch (desc->nr_channels) {
1273 case 1:
1274 result = FMT_32_FLOAT;
1275 goto out_word4;
1276 case 2:
1277 result = FMT_32_32_FLOAT;
1278 goto out_word4;
1279 case 4:
1280 result = FMT_32_32_32_32_FLOAT;
1281 goto out_word4;
1282 }
1283 }
1284 goto out_unknown;
1285 }
1286
1287 out_word4:
1288
1289 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1290 return ~0;
1291 if (word4_p)
1292 *word4_p = word4;
1293 if (yuv_format_p)
1294 *yuv_format_p = yuv_format;
1295 return result;
1296 out_unknown:
1297 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1298 return ~0;
1299 }
1300
1301 static const struct u_resource_vtbl r600_texture_vtbl =
1302 {
1303 r600_texture_get_handle, /* get_handle */
1304 r600_texture_destroy, /* resource_destroy */
1305 r600_texture_transfer_map, /* transfer_map */
1306 NULL, /* transfer_flush_region */
1307 r600_texture_transfer_unmap, /* transfer_unmap */
1308 NULL /* transfer_inline_write */
1309 };