2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_formats.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
37 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
38 struct pipe_resource
*texture
= transfer
->resource
;
40 ctx
->resource_copy_region(ctx
, &rtransfer
->staging
->b
.b
,
41 0, 0, 0, 0, texture
, transfer
->level
,
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
49 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
50 struct pipe_resource
*texture
= transfer
->resource
;
53 u_box_origin_2d(transfer
->box
.width
, transfer
->box
.height
, &sbox
);
55 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
56 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
57 &rtransfer
->staging
->b
.b
,
61 unsigned r600_texture_get_offset(struct r600_texture
*rtex
,
62 unsigned level
, unsigned layer
)
64 return rtex
->surface
.level
[level
].offset
+
65 layer
* rtex
->surface
.level
[level
].slice_size
;
68 static int r600_init_surface(struct r600_screen
*rscreen
,
69 struct radeon_surface
*surface
,
70 const struct pipe_resource
*ptex
,
72 bool is_flushed_depth
)
74 const struct util_format_description
*desc
=
75 util_format_description(ptex
->format
);
76 bool is_depth
, is_stencil
;
78 is_depth
= util_format_has_depth(desc
);
79 is_stencil
= util_format_has_stencil(desc
);
81 surface
->npix_x
= ptex
->width0
;
82 surface
->npix_y
= ptex
->height0
;
83 surface
->npix_z
= ptex
->depth0
;
84 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
85 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
87 surface
->array_size
= 1;
88 surface
->last_level
= ptex
->last_level
;
90 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
91 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
92 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
94 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
95 /* align byte per element on dword */
96 if (surface
->bpe
== 3) {
101 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
104 switch (array_mode
) {
105 case V_038000_ARRAY_1D_TILED_THIN1
:
106 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
108 case V_038000_ARRAY_2D_TILED_THIN1
:
109 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
111 case V_038000_ARRAY_LINEAR_ALIGNED
:
112 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
114 case V_038000_ARRAY_LINEAR_GENERAL
:
116 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR
, MODE
);
119 switch (ptex
->target
) {
120 case PIPE_TEXTURE_1D
:
121 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
123 case PIPE_TEXTURE_RECT
:
124 case PIPE_TEXTURE_2D
:
125 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
127 case PIPE_TEXTURE_3D
:
128 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
130 case PIPE_TEXTURE_1D_ARRAY
:
131 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
132 surface
->array_size
= ptex
->array_size
;
134 case PIPE_TEXTURE_2D_ARRAY
:
135 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d layout for now */
136 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
137 surface
->array_size
= ptex
->array_size
;
139 case PIPE_TEXTURE_CUBE
:
140 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
146 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
147 surface
->flags
|= RADEON_SURF_SCANOUT
;
150 if (!is_flushed_depth
&& is_depth
) {
151 surface
->flags
|= RADEON_SURF_ZBUFFER
;
154 surface
->flags
|= RADEON_SURF_SBUFFER
|
155 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
161 static int r600_setup_surface(struct pipe_screen
*screen
,
162 struct r600_texture
*rtex
,
163 unsigned pitch_in_bytes_override
)
165 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
166 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
170 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
174 rtex
->size
= rtex
->surface
.bo_size
;
175 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
176 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
179 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
180 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
181 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
182 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
183 rtex
->surface
.stencil_offset
=
184 rtex
->surface
.stencil_level
[0].offset
= rtex
->surface
.level
[0].slice_size
;
187 for (i
= 0; i
<= ptex
->last_level
; i
++) {
188 switch (rtex
->surface
.level
[i
].mode
) {
189 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
190 rtex
->array_mode
[i
] = V_038000_ARRAY_LINEAR_ALIGNED
;
192 case RADEON_SURF_MODE_1D
:
193 rtex
->array_mode
[i
] = V_038000_ARRAY_1D_TILED_THIN1
;
195 case RADEON_SURF_MODE_2D
:
196 rtex
->array_mode
[i
] = V_038000_ARRAY_2D_TILED_THIN1
;
199 case RADEON_SURF_MODE_LINEAR
:
200 rtex
->array_mode
[i
] = 0;
207 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
208 struct pipe_resource
*ptex
,
209 struct winsys_handle
*whandle
)
211 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
212 struct r600_resource
*resource
= &rtex
->resource
;
213 struct radeon_surface
*surface
= &rtex
->surface
;
214 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
216 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
218 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
219 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
220 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
221 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
222 surface
->bankw
, surface
->bankh
,
224 surface
->stencil_tile_split
,
226 rtex
->surface
.level
[0].pitch_bytes
);
228 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
229 rtex
->surface
.level
[0].pitch_bytes
, whandle
);
232 static void r600_texture_destroy(struct pipe_screen
*screen
,
233 struct pipe_resource
*ptex
)
235 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
236 struct r600_resource
*resource
= &rtex
->resource
;
238 if (rtex
->flushed_depth_texture
)
239 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
241 pb_reference(&resource
->buf
, NULL
);
245 static const struct u_resource_vtbl r600_texture_vtbl
;
247 /* The number of samples can be specified independently of the texture. */
248 void r600_texture_get_fmask_info(struct r600_screen
*rscreen
,
249 struct r600_texture
*rtex
,
251 struct r600_fmask_info
*out
)
253 /* FMASK is allocated pretty much like an ordinary texture.
254 * Here we use bpe in the units of bits, not bytes. */
255 struct radeon_surface fmask
= rtex
->surface
;
257 switch (nr_samples
) {
259 /* This should be 8,1, but we should set nsamples > 1
260 * for the allocator to treat it as a multisample surface.
261 * Let's set 4,2 then. */
275 R600_ERR("Invalid sample count for FMASK allocation.\n");
279 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
280 if (rscreen
->chip_class
<= R700
) {
284 if (rscreen
->chip_class
>= EVERGREEN
) {
285 fmask
.bankh
= nr_samples
<= 4 ? 4 : 1;
288 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
289 R600_ERR("Got error in surface_init while allocating FMASK.\n");
292 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
294 out
->bank_height
= fmask
.bankh
;
295 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
296 out
->size
= (fmask
.bo_size
+ 7) / 8;
299 static void r600_texture_allocate_fmask(struct r600_screen
*rscreen
,
300 struct r600_texture
*rtex
)
302 struct r600_fmask_info fmask
;
304 r600_texture_get_fmask_info(rscreen
, rtex
,
305 rtex
->resource
.b
.b
.nr_samples
, &fmask
);
307 /* Reserve space for FMASK while converting bits back to bytes. */
308 rtex
->fmask_bank_height
= fmask
.bank_height
;
309 rtex
->fmask_offset
= align(rtex
->size
, fmask
.alignment
);
310 rtex
->fmask_size
= fmask
.size
;
311 rtex
->size
= rtex
->fmask_offset
+ rtex
->fmask_size
;
313 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
314 fmask
.npix_x
, fmask
.npix_y
, fmask
.bpe
* fmask
.nsamples
, rtex
->fmask_size
);
318 void r600_texture_get_cmask_info(struct r600_screen
*rscreen
,
319 struct r600_texture
*rtex
,
320 struct r600_cmask_info
*out
)
322 unsigned cmask_tile_width
= 8;
323 unsigned cmask_tile_height
= 8;
324 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
325 unsigned element_bits
= 4;
326 unsigned cmask_cache_bits
= 1024;
327 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
328 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
330 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
331 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
332 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
333 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
334 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
336 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
337 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
339 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
340 unsigned slice_bytes
=
341 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
343 assert(macro_tile_width
% 128 == 0);
344 assert(macro_tile_height
% 128 == 0);
346 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
347 out
->alignment
= MAX2(256, base_align
);
348 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
351 static void r600_texture_allocate_cmask(struct r600_screen
*rscreen
,
352 struct r600_texture
*rtex
)
354 struct r600_cmask_info cmask
;
356 r600_texture_get_cmask_info(rscreen
, rtex
, &cmask
);
358 rtex
->cmask_slice_tile_max
= cmask
.slice_tile_max
;
359 rtex
->cmask_offset
= align(rtex
->size
, cmask
.alignment
);
360 rtex
->cmask_size
= cmask
.size
;
361 rtex
->size
= rtex
->cmask_offset
+ rtex
->cmask_size
;
363 printf("CMASK: macro tile width = %u, macro tile height = %u, "
364 "pitch elements = %u, height = %u, slice tile max = %u\n",
365 macro_tile_width
, macro_tile_height
, pitch_elements
, height
,
366 rtex
->cmask_slice_tile_max
);
370 DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth
, "R600_PRINT_TEXDEPTH", FALSE
);
372 static struct r600_texture
*
373 r600_texture_create_object(struct pipe_screen
*screen
,
374 const struct pipe_resource
*base
,
375 unsigned pitch_in_bytes_override
,
376 struct pb_buffer
*buf
,
378 struct radeon_surface
*surface
)
380 struct r600_texture
*rtex
;
381 struct r600_resource
*resource
;
382 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
385 rtex
= CALLOC_STRUCT(r600_texture
);
389 resource
= &rtex
->resource
;
390 resource
->b
.b
= *base
;
391 resource
->b
.vtbl
= &r600_texture_vtbl
;
392 pipe_reference_init(&resource
->b
.b
.reference
, 1);
393 resource
->b
.b
.screen
= screen
;
394 rtex
->pitch_override
= pitch_in_bytes_override
;
396 /* don't include stencil-only formats which we don't support for rendering */
397 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
399 rtex
->surface
= *surface
;
400 r
= r600_setup_surface(screen
, rtex
,
401 pitch_in_bytes_override
);
407 if (base
->nr_samples
> 1 && !rtex
->is_depth
&& alloc_bo
) {
408 r600_texture_allocate_cmask(rscreen
, rtex
);
409 r600_texture_allocate_fmask(rscreen
, rtex
);
412 if (!rtex
->is_depth
&& base
->nr_samples
> 1 &&
413 (!rtex
->fmask_size
|| !rtex
->cmask_size
)) {
418 /* Tiled depth textures utilize the non-displayable tile order. */
419 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
421 /* Now create the backing buffer. */
422 if (!buf
&& alloc_bo
) {
423 unsigned base_align
= rtex
->surface
.bo_alignment
;
424 unsigned usage
= R600_TEX_IS_TILED(rtex
, 0) ? PIPE_USAGE_STATIC
: base
->usage
;
426 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, base
->bind
, usage
)) {
431 /* This is usually the window framebuffer. We want it in VRAM, always. */
433 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
434 resource
->domains
= RADEON_DOMAIN_VRAM
;
437 if (rtex
->cmask_size
) {
438 /* Initialize the cmask to 0xCC (= compressed state). */
439 char *ptr
= rscreen
->ws
->buffer_map(resource
->cs_buf
, NULL
, PIPE_TRANSFER_WRITE
);
440 memset(ptr
+ rtex
->cmask_offset
, 0xCC, rtex
->cmask_size
);
441 rscreen
->ws
->buffer_unmap(resource
->cs_buf
);
444 if (debug_get_option_print_texdepth() && rtex
->is_depth
&& rtex
->non_disp_tiling
) {
445 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
446 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
447 "bpe=%u, nsamples=%u, flags=%u\n",
448 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
449 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
450 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
451 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
452 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
453 rtex
->surface
.flags
);
454 if (rtex
->surface
.flags
& RADEON_SURF_ZBUFFER
) {
455 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
456 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
457 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
458 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
459 i
, (unsigned long long)rtex
->surface
.level
[i
].offset
,
460 (unsigned long long)rtex
->surface
.level
[i
].slice_size
,
461 rtex
->surface
.level
[i
].npix_x
,
462 rtex
->surface
.level
[i
].npix_y
,
463 rtex
->surface
.level
[i
].npix_z
,
464 rtex
->surface
.level
[i
].nblk_x
,
465 rtex
->surface
.level
[i
].nblk_y
,
466 rtex
->surface
.level
[i
].nblk_z
,
467 rtex
->surface
.level
[i
].pitch_bytes
,
468 rtex
->surface
.level
[i
].mode
);
471 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
472 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
473 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
474 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
475 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
476 i
, (unsigned long long)rtex
->surface
.stencil_level
[i
].offset
,
477 (unsigned long long)rtex
->surface
.stencil_level
[i
].slice_size
,
478 rtex
->surface
.stencil_level
[i
].npix_x
,
479 rtex
->surface
.stencil_level
[i
].npix_y
,
480 rtex
->surface
.stencil_level
[i
].npix_z
,
481 rtex
->surface
.stencil_level
[i
].nblk_x
,
482 rtex
->surface
.stencil_level
[i
].nblk_y
,
483 rtex
->surface
.stencil_level
[i
].nblk_z
,
484 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
485 rtex
->surface
.stencil_level
[i
].mode
);
492 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
493 const struct pipe_resource
*templ
)
495 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
496 struct radeon_surface surface
;
497 const struct util_format_description
*desc
= util_format_description(templ
->format
);
501 /* Default tiling mode for staging textures. */
502 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
504 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
505 * because 422 formats are used for videos, which prefer linear buffers
506 * for fast uploads anyway. */
507 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
) &&
508 desc
->layout
!= UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
509 if (!(templ
->bind
& PIPE_BIND_SCANOUT
) &&
510 templ
->usage
!= PIPE_USAGE_STAGING
&&
511 templ
->usage
!= PIPE_USAGE_STREAM
&&
512 templ
->target
!= PIPE_TEXTURE_1D
) {
513 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
514 } else if (util_format_is_compressed(templ
->format
)) {
515 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
519 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
,
520 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
524 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
528 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
529 0, NULL
, TRUE
, &surface
);
532 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
533 struct pipe_resource
*texture
,
534 const struct pipe_surface
*templ
,
535 unsigned width
, unsigned height
)
537 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
539 assert(templ
->u
.tex
.first_layer
== templ
->u
.tex
.last_layer
);
542 pipe_reference_init(&surface
->base
.reference
, 1);
543 pipe_resource_reference(&surface
->base
.texture
, texture
);
544 surface
->base
.context
= pipe
;
545 surface
->base
.format
= templ
->format
;
546 surface
->base
.width
= width
;
547 surface
->base
.height
= height
;
548 surface
->base
.usage
= templ
->usage
;
549 surface
->base
.u
= templ
->u
;
550 return &surface
->base
;
553 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
554 struct pipe_resource
*texture
,
555 const struct pipe_surface
*templ
)
557 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
558 unsigned level
= templ
->u
.tex
.level
;
560 return r600_create_surface_custom(pipe
, texture
, templ
,
561 rtex
->surface
.level
[level
].npix_x
,
562 rtex
->surface
.level
[level
].npix_y
);
565 static void r600_surface_destroy(struct pipe_context
*pipe
,
566 struct pipe_surface
*surface
)
568 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
569 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
, NULL
);
570 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
, NULL
);
571 pipe_resource_reference(&surface
->texture
, NULL
);
575 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
576 const struct pipe_resource
*templ
,
577 struct winsys_handle
*whandle
)
579 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
580 struct pb_buffer
*buf
= NULL
;
582 unsigned array_mode
= 0;
583 enum radeon_bo_layout micro
, macro
;
584 struct radeon_surface surface
;
587 /* Support only 2D textures without mipmaps */
588 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
589 templ
->depth0
!= 1 || templ
->last_level
!= 0)
592 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
596 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
597 &surface
.bankw
, &surface
.bankh
,
599 &surface
.stencil_tile_split
,
602 if (macro
== RADEON_LAYOUT_TILED
)
603 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
604 else if (micro
== RADEON_LAYOUT_TILED
)
605 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
609 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
613 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
614 stride
, buf
, FALSE
, &surface
);
617 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
618 struct pipe_resource
*texture
,
619 struct r600_texture
**staging
)
621 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
622 struct pipe_resource resource
;
623 struct r600_texture
**flushed_depth_texture
= staging
?
624 staging
: &rtex
->flushed_depth_texture
;
626 if (!staging
&& rtex
->flushed_depth_texture
)
627 return true; /* it's ready */
629 resource
.target
= texture
->target
;
630 resource
.format
= texture
->format
;
631 resource
.width0
= texture
->width0
;
632 resource
.height0
= texture
->height0
;
633 resource
.depth0
= texture
->depth0
;
634 resource
.array_size
= texture
->array_size
;
635 resource
.last_level
= texture
->last_level
;
636 resource
.nr_samples
= texture
->nr_samples
;
637 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_STATIC
;
638 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
639 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
642 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
644 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
645 if (*flushed_depth_texture
== NULL
) {
646 R600_ERR("failed to create temporary texture to hold flushed depth\n");
650 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
651 (*flushed_depth_texture
)->non_disp_tiling
= false;
655 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
656 struct pipe_resource
*texture
,
659 const struct pipe_box
*box
,
660 struct pipe_transfer
**ptransfer
)
662 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
663 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
664 struct pipe_resource resource
;
665 struct r600_transfer
*trans
;
666 boolean use_staging_texture
= FALSE
;
667 enum pipe_format format
= texture
->format
;
668 struct radeon_winsys_cs_handle
*buf
;
672 if ((texture
->bind
& PIPE_BIND_GLOBAL
) && texture
->target
== PIPE_BUFFER
) {
673 return r600_compute_global_transfer_map(ctx
, texture
, level
, usage
, box
, ptransfer
);
676 /* We cannot map a tiled texture directly because the data is
677 * in a different order, therefore we do detiling using a blit.
679 * Also, use a temporary in GTT memory for read transfers, as
680 * the CPU is much happier reading out of cached system memory
681 * than uncached VRAM.
683 if (R600_TEX_IS_TILED(rtex
, level
)) {
684 use_staging_texture
= TRUE
;
687 /* Use a staging texture for uploads if the underlying BO is busy. */
688 if (!(usage
& PIPE_TRANSFER_READ
) &&
689 (rctx
->ws
->cs_is_buffer_referenced(rctx
->cs
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
690 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
))) {
691 use_staging_texture
= TRUE
;
694 if (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
) {
695 use_staging_texture
= FALSE
;
698 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
702 trans
= CALLOC_STRUCT(r600_transfer
);
705 trans
->transfer
.resource
= texture
;
706 trans
->transfer
.level
= level
;
707 trans
->transfer
.usage
= usage
;
708 trans
->transfer
.box
= *box
;
709 if (rtex
->is_depth
) {
710 /* XXX: only readback the rectangle which is being mapped?
712 /* XXX: when discard is true, no need to read back from depth texture
714 struct r600_texture
*staging_depth
;
716 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
717 R600_ERR("failed to create temporary texture to hold untiled copy\n");
722 r600_blit_decompress_depth(ctx
, rtex
, staging_depth
,
724 box
->z
, box
->z
+ box
->depth
- 1,
727 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
728 trans
->offset
= r600_texture_get_offset(staging_depth
, level
, box
->z
);
729 trans
->staging
= (struct r600_resource
*)staging_depth
;
730 } else if (use_staging_texture
) {
731 resource
.target
= PIPE_TEXTURE_2D
;
732 resource
.format
= texture
->format
;
733 resource
.width0
= box
->width
;
734 resource
.height0
= box
->height
;
736 resource
.array_size
= 1;
737 resource
.last_level
= 0;
738 resource
.nr_samples
= 0;
739 resource
.usage
= PIPE_USAGE_STAGING
;
741 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
742 /* For texture reading, the temporary (detiled) texture is used as
743 * a render target when blitting from a tiled texture. */
744 if (usage
& PIPE_TRANSFER_READ
) {
745 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
747 /* For texture writing, the temporary texture is used as a sampler
748 * when blitting into a tiled texture. */
749 if (usage
& PIPE_TRANSFER_WRITE
) {
750 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
752 /* Create the temporary texture. */
753 trans
->staging
= (struct r600_resource
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
754 if (trans
->staging
== NULL
) {
755 R600_ERR("failed to create temporary texture to hold untiled copy\n");
760 trans
->transfer
.stride
=
761 ((struct r600_texture
*)trans
->staging
)->surface
.level
[0].pitch_bytes
;
762 if (usage
& PIPE_TRANSFER_READ
) {
763 r600_copy_to_staging_texture(ctx
, trans
);
764 /* Always referenced in the blit. */
765 r600_flush(ctx
, NULL
, 0);
768 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
769 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
770 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
773 if (trans
->staging
) {
774 buf
= ((struct r600_resource
*)trans
->staging
)->cs_buf
;
776 buf
= ((struct r600_resource
*)texture
)->cs_buf
;
779 if (rtex
->is_depth
|| !trans
->staging
)
780 offset
= trans
->offset
+
781 box
->y
/ util_format_get_blockheight(format
) * trans
->transfer
.stride
+
782 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
784 if (!(map
= rctx
->ws
->buffer_map(buf
, rctx
->cs
, usage
))) {
785 pipe_resource_reference((struct pipe_resource
**)&trans
->staging
, NULL
);
790 *ptransfer
= &trans
->transfer
;
794 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
795 struct pipe_transfer
* transfer
)
797 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
798 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
799 struct radeon_winsys_cs_handle
*buf
;
800 struct pipe_resource
*texture
= transfer
->resource
;
801 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
803 if ((transfer
->resource
->bind
& PIPE_BIND_GLOBAL
) && transfer
->resource
->target
== PIPE_BUFFER
) {
804 return r600_compute_global_transfer_unmap(ctx
, transfer
);
807 if (rtransfer
->staging
) {
808 buf
= ((struct r600_resource
*)rtransfer
->staging
)->cs_buf
;
810 buf
= ((struct r600_resource
*)transfer
->resource
)->cs_buf
;
812 rctx
->ws
->buffer_unmap(buf
);
814 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
815 if (rtex
->is_depth
) {
816 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
817 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
818 &rtransfer
->staging
->b
.b
, transfer
->level
,
821 r600_copy_from_staging_texture(ctx
, rtransfer
);
825 if (rtransfer
->staging
)
826 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
831 void r600_init_surface_functions(struct r600_context
*r600
)
833 r600
->context
.create_surface
= r600_create_surface
;
834 r600
->context
.surface_destroy
= r600_surface_destroy
;
837 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
838 const unsigned char *swizzle_view
)
841 unsigned char swizzle
[4];
843 const uint32_t swizzle_shift
[4] = {
846 const uint32_t swizzle_bit
[4] = {
851 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
853 memcpy(swizzle
, swizzle_format
, 4);
857 for (i
= 0; i
< 4; i
++) {
858 switch (swizzle
[i
]) {
859 case UTIL_FORMAT_SWIZZLE_Y
:
860 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
862 case UTIL_FORMAT_SWIZZLE_Z
:
863 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
865 case UTIL_FORMAT_SWIZZLE_W
:
866 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
868 case UTIL_FORMAT_SWIZZLE_0
:
869 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
871 case UTIL_FORMAT_SWIZZLE_1
:
872 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
874 default: /* UTIL_FORMAT_SWIZZLE_X */
875 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
881 /* texture format translate */
882 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
883 enum pipe_format format
,
884 const unsigned char *swizzle_view
,
885 uint32_t *word4_p
, uint32_t *yuv_format_p
)
887 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
888 const struct util_format_description
*desc
;
889 boolean uniform
= TRUE
;
890 static int r600_enable_s3tc
= -1;
891 bool is_srgb_valid
= FALSE
;
894 const uint32_t sign_bit
[4] = {
895 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
896 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
897 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
898 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
900 desc
= util_format_description(format
);
902 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
904 /* Colorspace (return non-RGB formats directly). */
905 switch (desc
->colorspace
) {
906 /* Depth stencil formats */
907 case UTIL_FORMAT_COLORSPACE_ZS
:
909 case PIPE_FORMAT_Z16_UNORM
:
912 case PIPE_FORMAT_X24S8_UINT
:
913 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
914 case PIPE_FORMAT_Z24X8_UNORM
:
915 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
918 case PIPE_FORMAT_S8X24_UINT
:
919 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
920 case PIPE_FORMAT_X8Z24_UNORM
:
921 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
924 case PIPE_FORMAT_S8_UINT
:
926 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
928 case PIPE_FORMAT_Z32_FLOAT
:
929 result
= FMT_32_FLOAT
;
931 case PIPE_FORMAT_X32_S8X24_UINT
:
932 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
933 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
934 result
= FMT_X24_8_32_FLOAT
;
940 case UTIL_FORMAT_COLORSPACE_YUV
:
941 yuv_format
|= (1 << 30);
943 case PIPE_FORMAT_UYVY
:
944 case PIPE_FORMAT_YUYV
:
948 goto out_unknown
; /* XXX */
950 case UTIL_FORMAT_COLORSPACE_SRGB
:
951 word4
|= S_038010_FORCE_DEGAMMA(1);
958 if (r600_enable_s3tc
== -1) {
959 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
960 if (rscreen
->info
.drm_minor
>= 9)
961 r600_enable_s3tc
= 1;
963 r600_enable_s3tc
= debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
966 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
967 if (!r600_enable_s3tc
)
971 case PIPE_FORMAT_RGTC1_SNORM
:
972 case PIPE_FORMAT_LATC1_SNORM
:
973 word4
|= sign_bit
[0];
974 case PIPE_FORMAT_RGTC1_UNORM
:
975 case PIPE_FORMAT_LATC1_UNORM
:
978 case PIPE_FORMAT_RGTC2_SNORM
:
979 case PIPE_FORMAT_LATC2_SNORM
:
980 word4
|= sign_bit
[0] | sign_bit
[1];
981 case PIPE_FORMAT_RGTC2_UNORM
:
982 case PIPE_FORMAT_LATC2_UNORM
:
990 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
992 if (!r600_enable_s3tc
)
995 if (!util_format_s3tc_enabled
) {
1000 case PIPE_FORMAT_DXT1_RGB
:
1001 case PIPE_FORMAT_DXT1_RGBA
:
1002 case PIPE_FORMAT_DXT1_SRGB
:
1003 case PIPE_FORMAT_DXT1_SRGBA
:
1005 is_srgb_valid
= TRUE
;
1007 case PIPE_FORMAT_DXT3_RGBA
:
1008 case PIPE_FORMAT_DXT3_SRGBA
:
1010 is_srgb_valid
= TRUE
;
1012 case PIPE_FORMAT_DXT5_RGBA
:
1013 case PIPE_FORMAT_DXT5_SRGBA
:
1015 is_srgb_valid
= TRUE
;
1022 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1024 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1025 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1028 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1029 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1037 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1038 result
= FMT_5_9_9_9_SHAREDEXP
;
1040 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1041 result
= FMT_10_11_11_FLOAT
;
1046 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1047 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1048 word4
|= sign_bit
[i
];
1052 /* R8G8Bx_SNORM - XXX CxV8U8 */
1054 /* See whether the components are of the same size. */
1055 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1056 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1059 /* Non-uniform formats. */
1061 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1062 desc
->channel
[0].pure_integer
)
1063 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1064 switch(desc
->nr_channels
) {
1066 if (desc
->channel
[0].size
== 5 &&
1067 desc
->channel
[1].size
== 6 &&
1068 desc
->channel
[2].size
== 5) {
1074 if (desc
->channel
[0].size
== 5 &&
1075 desc
->channel
[1].size
== 5 &&
1076 desc
->channel
[2].size
== 5 &&
1077 desc
->channel
[3].size
== 1) {
1078 result
= FMT_1_5_5_5
;
1081 if (desc
->channel
[0].size
== 10 &&
1082 desc
->channel
[1].size
== 10 &&
1083 desc
->channel
[2].size
== 10 &&
1084 desc
->channel
[3].size
== 2) {
1085 result
= FMT_2_10_10_10
;
1093 /* Find the first non-VOID channel. */
1094 for (i
= 0; i
< 4; i
++) {
1095 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1103 /* uniform formats */
1104 switch (desc
->channel
[i
].type
) {
1105 case UTIL_FORMAT_TYPE_UNSIGNED
:
1106 case UTIL_FORMAT_TYPE_SIGNED
:
1108 if (!desc
->channel
[i
].normalized
&&
1109 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
1113 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1114 desc
->channel
[i
].pure_integer
)
1115 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1117 switch (desc
->channel
[i
].size
) {
1119 switch (desc
->nr_channels
) {
1124 result
= FMT_4_4_4_4
;
1129 switch (desc
->nr_channels
) {
1137 result
= FMT_8_8_8_8
;
1138 is_srgb_valid
= TRUE
;
1143 switch (desc
->nr_channels
) {
1151 result
= FMT_16_16_16_16
;
1156 switch (desc
->nr_channels
) {
1164 result
= FMT_32_32_32_32
;
1170 case UTIL_FORMAT_TYPE_FLOAT
:
1171 switch (desc
->channel
[i
].size
) {
1173 switch (desc
->nr_channels
) {
1175 result
= FMT_16_FLOAT
;
1178 result
= FMT_16_16_FLOAT
;
1181 result
= FMT_16_16_16_16_FLOAT
;
1186 switch (desc
->nr_channels
) {
1188 result
= FMT_32_FLOAT
;
1191 result
= FMT_32_32_FLOAT
;
1194 result
= FMT_32_32_32_32_FLOAT
;
1203 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
1208 *yuv_format_p
= yuv_format
;
1211 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1215 static const struct u_resource_vtbl r600_texture_vtbl
=
1217 r600_texture_get_handle
, /* get_handle */
1218 r600_texture_destroy
, /* resource_destroy */
1219 r600_texture_transfer_map
, /* transfer_map */
1220 NULL
, /* transfer_flush_region */
1221 r600_texture_transfer_unmap
, /* transfer_unmap */
1222 NULL
/* transfer_inline_write */