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[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_pack_color.h"
34 #include "util/u_surface.h"
35 #include "util/os_time.h"
36 #include <errno.h>
37 #include <inttypes.h>
38
39 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
40 struct r600_texture *rtex);
41 static enum radeon_surf_mode
42 r600_choose_tiling(struct r600_common_screen *rscreen,
43 const struct pipe_resource *templ);
44
45
46 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
47 struct r600_texture *rdst,
48 unsigned dst_level, unsigned dstx,
49 unsigned dsty, unsigned dstz,
50 struct r600_texture *rsrc,
51 unsigned src_level,
52 const struct pipe_box *src_box)
53 {
54 if (!rctx->dma.cs)
55 return false;
56
57 if (rdst->surface.bpe != rsrc->surface.bpe)
58 return false;
59
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc->resource.b.b.nr_samples > 1 ||
62 rdst->resource.b.b.nr_samples > 1)
63 return false;
64
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
68 */
69 if (rsrc->is_depth || rdst->is_depth)
70 return false;
71
72 /* CMASK as:
73 * src: Both texture and SDMA paths need decompression. Use SDMA.
74 * dst: If overwriting the whole texture, discard CMASK and use
75 * SDMA. Otherwise, use the 3D path.
76 */
77 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
78 /* The CMASK clear is only enabled for the first level. */
79 assert(dst_level == 0);
80 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
81 dstx, dsty, dstz, src_box->width,
82 src_box->height, src_box->depth))
83 return false;
84
85 r600_texture_discard_cmask(rctx->screen, rdst);
86 }
87
88 /* All requirements are met. Prepare textures for SDMA. */
89 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
90 rctx->b.flush_resource(&rctx->b, &rsrc->resource.b.b);
91
92 assert(!(rsrc->dirty_level_mask & (1 << src_level)));
93 assert(!(rdst->dirty_level_mask & (1 << dst_level)));
94
95 return true;
96 }
97
98 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
99 static void r600_copy_region_with_blit(struct pipe_context *pipe,
100 struct pipe_resource *dst,
101 unsigned dst_level,
102 unsigned dstx, unsigned dsty, unsigned dstz,
103 struct pipe_resource *src,
104 unsigned src_level,
105 const struct pipe_box *src_box)
106 {
107 struct pipe_blit_info blit;
108
109 memset(&blit, 0, sizeof(blit));
110 blit.src.resource = src;
111 blit.src.format = src->format;
112 blit.src.level = src_level;
113 blit.src.box = *src_box;
114 blit.dst.resource = dst;
115 blit.dst.format = dst->format;
116 blit.dst.level = dst_level;
117 blit.dst.box.x = dstx;
118 blit.dst.box.y = dsty;
119 blit.dst.box.z = dstz;
120 blit.dst.box.width = src_box->width;
121 blit.dst.box.height = src_box->height;
122 blit.dst.box.depth = src_box->depth;
123 blit.mask = util_format_get_mask(src->format) &
124 util_format_get_mask(dst->format);
125 blit.filter = PIPE_TEX_FILTER_NEAREST;
126
127 if (blit.mask) {
128 pipe->blit(pipe, &blit);
129 }
130 }
131
132 /* Copy from a full GPU texture to a transfer's staging one. */
133 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
134 {
135 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
136 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
137 struct pipe_resource *dst = &rtransfer->staging->b.b;
138 struct pipe_resource *src = transfer->resource;
139
140 if (src->nr_samples > 1) {
141 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
142 src, transfer->level, &transfer->box);
143 return;
144 }
145
146 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
147 &transfer->box);
148 }
149
150 /* Copy from a transfer's staging texture to a full GPU one. */
151 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
152 {
153 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
154 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
155 struct pipe_resource *dst = transfer->resource;
156 struct pipe_resource *src = &rtransfer->staging->b.b;
157 struct pipe_box sbox;
158
159 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
160
161 if (dst->nr_samples > 1) {
162 r600_copy_region_with_blit(ctx, dst, transfer->level,
163 transfer->box.x, transfer->box.y, transfer->box.z,
164 src, 0, &sbox);
165 return;
166 }
167
168 rctx->dma_copy(ctx, dst, transfer->level,
169 transfer->box.x, transfer->box.y, transfer->box.z,
170 src, 0, &sbox);
171 }
172
173 static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
174 struct r600_texture *rtex, unsigned level,
175 const struct pipe_box *box,
176 unsigned *stride,
177 unsigned *layer_stride)
178 {
179 *stride = rtex->surface.u.legacy.level[level].nblk_x *
180 rtex->surface.bpe;
181 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
182 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
183
184 if (!box)
185 return rtex->surface.u.legacy.level[level].offset;
186
187 /* Each texture is an array of mipmap levels. Each level is
188 * an array of slices. */
189 return rtex->surface.u.legacy.level[level].offset +
190 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
191 (box->y / rtex->surface.blk_h *
192 rtex->surface.u.legacy.level[level].nblk_x +
193 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
194 }
195
196 static int r600_init_surface(struct r600_common_screen *rscreen,
197 struct radeon_surf *surface,
198 const struct pipe_resource *ptex,
199 enum radeon_surf_mode array_mode,
200 unsigned pitch_in_bytes_override,
201 unsigned offset,
202 bool is_imported,
203 bool is_scanout,
204 bool is_flushed_depth)
205 {
206 const struct util_format_description *desc =
207 util_format_description(ptex->format);
208 bool is_depth, is_stencil;
209 int r;
210 unsigned i, bpe, flags = 0;
211
212 is_depth = util_format_has_depth(desc);
213 is_stencil = util_format_has_stencil(desc);
214
215 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
216 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
217 bpe = 4; /* stencil is allocated separately on evergreen */
218 } else {
219 bpe = util_format_get_blocksize(ptex->format);
220 assert(util_is_power_of_two_or_zero(bpe));
221 }
222
223 if (!is_flushed_depth && is_depth) {
224 flags |= RADEON_SURF_ZBUFFER;
225
226 if (is_stencil)
227 flags |= RADEON_SURF_SBUFFER;
228 }
229
230 if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
231 /* This should catch bugs in gallium users setting incorrect flags. */
232 assert(ptex->nr_samples <= 1 &&
233 ptex->array_size == 1 &&
234 ptex->depth0 == 1 &&
235 ptex->last_level == 0 &&
236 !(flags & RADEON_SURF_Z_OR_SBUFFER));
237
238 flags |= RADEON_SURF_SCANOUT;
239 }
240
241 if (ptex->bind & PIPE_BIND_SHARED)
242 flags |= RADEON_SURF_SHAREABLE;
243 if (is_imported)
244 flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
245 if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
246 flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
247
248 r = rscreen->ws->surface_init(rscreen->ws, ptex,
249 flags, bpe, array_mode, surface);
250 if (r) {
251 return r;
252 }
253
254 if (pitch_in_bytes_override &&
255 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
256 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
257 * for those
258 */
259 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe;
260 surface->u.legacy.level[0].slice_size_dw =
261 ((uint64_t)pitch_in_bytes_override * surface->u.legacy.level[0].nblk_y) / 4;
262 }
263
264 if (offset) {
265 for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
266 surface->u.legacy.level[i].offset += offset;
267 }
268
269 return 0;
270 }
271
272 static void r600_texture_init_metadata(struct r600_common_screen *rscreen,
273 struct r600_texture *rtex,
274 struct radeon_bo_metadata *metadata)
275 {
276 struct radeon_surf *surface = &rtex->surface;
277
278 memset(metadata, 0, sizeof(*metadata));
279
280 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
281 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
282 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
283 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
284 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
285 metadata->u.legacy.bankw = surface->u.legacy.bankw;
286 metadata->u.legacy.bankh = surface->u.legacy.bankh;
287 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
288 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
289 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
290 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
291 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
292 }
293
294 static void r600_surface_import_metadata(struct r600_common_screen *rscreen,
295 struct radeon_surf *surf,
296 struct radeon_bo_metadata *metadata,
297 enum radeon_surf_mode *array_mode,
298 bool *is_scanout)
299 {
300 surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config;
301 surf->u.legacy.bankw = metadata->u.legacy.bankw;
302 surf->u.legacy.bankh = metadata->u.legacy.bankh;
303 surf->u.legacy.tile_split = metadata->u.legacy.tile_split;
304 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
305 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
306
307 if (metadata->u.legacy.macrotile == RADEON_LAYOUT_TILED)
308 *array_mode = RADEON_SURF_MODE_2D;
309 else if (metadata->u.legacy.microtile == RADEON_LAYOUT_TILED)
310 *array_mode = RADEON_SURF_MODE_1D;
311 else
312 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
313
314 *is_scanout = metadata->u.legacy.scanout;
315 }
316
317 static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
318 struct r600_texture *rtex)
319 {
320 struct r600_common_screen *rscreen = rctx->screen;
321 struct pipe_context *ctx = &rctx->b;
322
323 if (ctx == rscreen->aux_context)
324 mtx_lock(&rscreen->aux_context_lock);
325
326 ctx->flush_resource(ctx, &rtex->resource.b.b);
327 ctx->flush(ctx, NULL, 0);
328
329 if (ctx == rscreen->aux_context)
330 mtx_unlock(&rscreen->aux_context_lock);
331 }
332
333 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
334 struct r600_texture *rtex)
335 {
336 if (!rtex->cmask.size)
337 return;
338
339 assert(rtex->resource.b.b.nr_samples <= 1);
340
341 /* Disable CMASK. */
342 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
343 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
344 rtex->dirty_level_mask = 0;
345
346 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
347
348 if (rtex->cmask_buffer != &rtex->resource)
349 r600_resource_reference(&rtex->cmask_buffer, NULL);
350
351 /* Notify all contexts about the change. */
352 p_atomic_inc(&rscreen->dirty_tex_counter);
353 p_atomic_inc(&rscreen->compressed_colortex_counter);
354 }
355
356 static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
357 struct r600_texture *rtex,
358 unsigned new_bind_flag,
359 bool invalidate_storage)
360 {
361 struct pipe_screen *screen = rctx->b.screen;
362 struct r600_texture *new_tex;
363 struct pipe_resource templ = rtex->resource.b.b;
364 unsigned i;
365
366 templ.bind |= new_bind_flag;
367
368 /* r600g doesn't react to dirty_tex_descriptor_counter */
369 if (rctx->chip_class < GFX6)
370 return;
371
372 if (rtex->resource.b.is_shared)
373 return;
374
375 if (new_bind_flag == PIPE_BIND_LINEAR) {
376 if (rtex->surface.is_linear)
377 return;
378
379 /* This fails with MSAA, depth, and compressed textures. */
380 if (r600_choose_tiling(rctx->screen, &templ) !=
381 RADEON_SURF_MODE_LINEAR_ALIGNED)
382 return;
383 }
384
385 new_tex = (struct r600_texture*)screen->resource_create(screen, &templ);
386 if (!new_tex)
387 return;
388
389 /* Copy the pixels to the new texture. */
390 if (!invalidate_storage) {
391 for (i = 0; i <= templ.last_level; i++) {
392 struct pipe_box box;
393
394 u_box_3d(0, 0, 0,
395 u_minify(templ.width0, i), u_minify(templ.height0, i),
396 util_num_layers(&templ, i), &box);
397
398 rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
399 &rtex->resource.b.b, i, &box);
400 }
401 }
402
403 if (new_bind_flag == PIPE_BIND_LINEAR) {
404 r600_texture_discard_cmask(rctx->screen, rtex);
405 }
406
407 /* Replace the structure fields of rtex. */
408 rtex->resource.b.b.bind = templ.bind;
409 pb_reference(&rtex->resource.buf, new_tex->resource.buf);
410 rtex->resource.gpu_address = new_tex->resource.gpu_address;
411 rtex->resource.vram_usage = new_tex->resource.vram_usage;
412 rtex->resource.gart_usage = new_tex->resource.gart_usage;
413 rtex->resource.bo_size = new_tex->resource.bo_size;
414 rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
415 rtex->resource.domains = new_tex->resource.domains;
416 rtex->resource.flags = new_tex->resource.flags;
417 rtex->size = new_tex->size;
418 rtex->db_render_format = new_tex->db_render_format;
419 rtex->db_compatible = new_tex->db_compatible;
420 rtex->can_sample_z = new_tex->can_sample_z;
421 rtex->can_sample_s = new_tex->can_sample_s;
422 rtex->surface = new_tex->surface;
423 rtex->fmask = new_tex->fmask;
424 rtex->cmask = new_tex->cmask;
425 rtex->cb_color_info = new_tex->cb_color_info;
426 rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
427 rtex->htile_offset = new_tex->htile_offset;
428 rtex->depth_cleared = new_tex->depth_cleared;
429 rtex->stencil_cleared = new_tex->stencil_cleared;
430 rtex->non_disp_tiling = new_tex->non_disp_tiling;
431 rtex->framebuffers_bound = new_tex->framebuffers_bound;
432
433 if (new_bind_flag == PIPE_BIND_LINEAR) {
434 assert(!rtex->htile_offset);
435 assert(!rtex->cmask.size);
436 assert(!rtex->fmask.size);
437 assert(!rtex->is_depth);
438 }
439
440 r600_texture_reference(&new_tex, NULL);
441
442 p_atomic_inc(&rctx->screen->dirty_tex_counter);
443 }
444
445 static void r600_texture_get_info(struct pipe_screen* screen,
446 struct pipe_resource *resource,
447 unsigned *pstride,
448 unsigned *poffset)
449 {
450 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
451 struct r600_texture *rtex = (struct r600_texture*)resource;
452 unsigned stride = 0;
453 unsigned offset = 0;
454
455 if (!rscreen || !rtex)
456 return;
457
458 if (resource->target != PIPE_BUFFER) {
459 offset = rtex->surface.u.legacy.level[0].offset;
460 stride = rtex->surface.u.legacy.level[0].nblk_x *
461 rtex->surface.bpe;
462 }
463
464 if (pstride)
465 *pstride = stride;
466
467 if (poffset)
468 *poffset = offset;
469 }
470
471 static boolean r600_texture_get_handle(struct pipe_screen* screen,
472 struct pipe_context *ctx,
473 struct pipe_resource *resource,
474 struct winsys_handle *whandle,
475 unsigned usage)
476 {
477 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
478 struct r600_common_context *rctx;
479 struct r600_resource *res = (struct r600_resource*)resource;
480 struct r600_texture *rtex = (struct r600_texture*)resource;
481 struct radeon_bo_metadata metadata;
482 bool update_metadata = false;
483 unsigned stride, offset, slice_size;
484
485 ctx = threaded_context_unwrap_sync(ctx);
486 rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
487
488 if (resource->target != PIPE_BUFFER) {
489 /* This is not supported now, but it might be required for OpenCL
490 * interop in the future.
491 */
492 if (resource->nr_samples > 1 || rtex->is_depth)
493 return false;
494
495 /* Move a suballocated texture into a non-suballocated allocation. */
496 if (rscreen->ws->buffer_is_suballocated(res->buf) ||
497 rtex->surface.tile_swizzle) {
498 assert(!res->b.is_shared);
499 r600_reallocate_texture_inplace(rctx, rtex,
500 PIPE_BIND_SHARED, false);
501 rctx->b.flush(&rctx->b, NULL, 0);
502 assert(res->b.b.bind & PIPE_BIND_SHARED);
503 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
504 assert(rtex->surface.tile_swizzle == 0);
505 }
506
507 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
508 rtex->cmask.size) {
509 /* Eliminate fast clear (CMASK) */
510 r600_eliminate_fast_color_clear(rctx, rtex);
511
512 /* Disable CMASK if flush_resource isn't going
513 * to be called.
514 */
515 if (rtex->cmask.size)
516 r600_texture_discard_cmask(rscreen, rtex);
517 }
518
519 /* Set metadata. */
520 if (!res->b.is_shared || update_metadata) {
521 r600_texture_init_metadata(rscreen, rtex, &metadata);
522 if (rscreen->query_opaque_metadata)
523 rscreen->query_opaque_metadata(rscreen, rtex,
524 &metadata);
525
526 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
527 }
528
529 slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4;
530 } else {
531 /* Move a suballocated buffer into a non-suballocated allocation. */
532 if (rscreen->ws->buffer_is_suballocated(res->buf)) {
533 assert(!res->b.is_shared);
534
535 /* Allocate a new buffer with PIPE_BIND_SHARED. */
536 struct pipe_resource templ = res->b.b;
537 templ.bind |= PIPE_BIND_SHARED;
538
539 struct pipe_resource *newb =
540 screen->resource_create(screen, &templ);
541 if (!newb)
542 return false;
543
544 /* Copy the old buffer contents to the new one. */
545 struct pipe_box box;
546 u_box_1d(0, newb->width0, &box);
547 rctx->b.resource_copy_region(&rctx->b, newb, 0, 0, 0, 0,
548 &res->b.b, 0, &box);
549 /* Move the new buffer storage to the old pipe_resource. */
550 r600_replace_buffer_storage(&rctx->b, &res->b.b, newb);
551 pipe_resource_reference(&newb, NULL);
552
553 assert(res->b.b.bind & PIPE_BIND_SHARED);
554 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
555 }
556
557 /* Buffers */
558 slice_size = 0;
559 }
560
561 r600_texture_get_info(screen, resource, &stride, &offset);
562
563 if (res->b.is_shared) {
564 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
565 * doesn't set it.
566 */
567 res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
568 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
569 res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
570 } else {
571 res->b.is_shared = true;
572 res->external_usage = usage;
573 }
574
575 return rscreen->ws->buffer_get_handle(res->buf, stride, offset,
576 slice_size, whandle);
577 }
578
579 static void r600_texture_destroy(struct pipe_screen *screen,
580 struct pipe_resource *ptex)
581 {
582 struct r600_texture *rtex = (struct r600_texture*)ptex;
583 struct r600_resource *resource = &rtex->resource;
584
585 r600_texture_reference(&rtex->flushed_depth_texture, NULL);
586 pipe_resource_reference((struct pipe_resource**)&resource->immed_buffer, NULL);
587
588 if (rtex->cmask_buffer != &rtex->resource) {
589 r600_resource_reference(&rtex->cmask_buffer, NULL);
590 }
591 pb_reference(&resource->buf, NULL);
592 FREE(rtex);
593 }
594
595 static const struct u_resource_vtbl r600_texture_vtbl;
596
597 /* The number of samples can be specified independently of the texture. */
598 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
599 struct r600_texture *rtex,
600 unsigned nr_samples,
601 struct r600_fmask_info *out)
602 {
603 /* FMASK is allocated like an ordinary texture. */
604 struct pipe_resource templ = rtex->resource.b.b;
605 struct radeon_surf fmask = {};
606 unsigned flags, bpe;
607
608 memset(out, 0, sizeof(*out));
609
610 templ.nr_samples = 1;
611 flags = rtex->surface.flags | RADEON_SURF_FMASK;
612
613 /* Use the same parameters and tile mode. */
614 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
615 fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh;
616 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
617 fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split;
618
619 if (nr_samples <= 4)
620 fmask.u.legacy.bankh = 4;
621
622 switch (nr_samples) {
623 case 2:
624 case 4:
625 bpe = 1;
626 break;
627 case 8:
628 bpe = 4;
629 break;
630 default:
631 R600_ERR("Invalid sample count for FMASK allocation.\n");
632 return;
633 }
634
635 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
636 * This can be fixed by writing a separate FMASK allocator specifically
637 * for R600-R700 asics. */
638 if (rscreen->chip_class <= R700) {
639 bpe *= 2;
640 }
641
642 if (rscreen->ws->surface_init(rscreen->ws, &templ,
643 flags, bpe, RADEON_SURF_MODE_2D, &fmask)) {
644 R600_ERR("Got error in surface_init while allocating FMASK.\n");
645 return;
646 }
647
648 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
649
650 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
651 if (out->slice_tile_max)
652 out->slice_tile_max -= 1;
653
654 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
655 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
656 out->bank_height = fmask.u.legacy.bankh;
657 out->tile_swizzle = fmask.tile_swizzle;
658 out->alignment = MAX2(256, fmask.surf_alignment);
659 out->size = fmask.surf_size;
660 }
661
662 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
663 struct r600_texture *rtex)
664 {
665 r600_texture_get_fmask_info(rscreen, rtex,
666 rtex->resource.b.b.nr_samples, &rtex->fmask);
667
668 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
669 rtex->size = rtex->fmask.offset + rtex->fmask.size;
670 }
671
672 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
673 struct r600_texture *rtex,
674 struct r600_cmask_info *out)
675 {
676 unsigned cmask_tile_width = 8;
677 unsigned cmask_tile_height = 8;
678 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
679 unsigned element_bits = 4;
680 unsigned cmask_cache_bits = 1024;
681 unsigned num_pipes = rscreen->info.num_tile_pipes;
682 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
683
684 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
685 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
686 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
687 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
688 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
689
690 unsigned pitch_elements = align(rtex->resource.b.b.width0, macro_tile_width);
691 unsigned height = align(rtex->resource.b.b.height0, macro_tile_height);
692
693 unsigned base_align = num_pipes * pipe_interleave_bytes;
694 unsigned slice_bytes =
695 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
696
697 assert(macro_tile_width % 128 == 0);
698 assert(macro_tile_height % 128 == 0);
699
700 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
701 out->alignment = MAX2(256, base_align);
702 out->size = util_num_layers(&rtex->resource.b.b, 0) *
703 align(slice_bytes, base_align);
704 }
705
706 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
707 struct r600_texture *rtex)
708 {
709 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
710
711 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
712 rtex->size = rtex->cmask.offset + rtex->cmask.size;
713
714 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
715 }
716
717 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
718 struct r600_texture *rtex)
719 {
720 if (rtex->cmask_buffer)
721 return;
722
723 assert(rtex->cmask.size == 0);
724
725 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
726
727 rtex->cmask_buffer = (struct r600_resource *)
728 r600_aligned_buffer_create(&rscreen->b,
729 R600_RESOURCE_FLAG_UNMAPPABLE,
730 PIPE_USAGE_DEFAULT,
731 rtex->cmask.size,
732 rtex->cmask.alignment);
733 if (rtex->cmask_buffer == NULL) {
734 rtex->cmask.size = 0;
735 return;
736 }
737
738 /* update colorbuffer state bits */
739 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
740
741 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
742
743 p_atomic_inc(&rscreen->compressed_colortex_counter);
744 }
745
746 void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
747 struct r600_resource *res,
748 unsigned immed_size)
749 {
750 res->immed_buffer = (struct r600_resource *)
751 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
752 PIPE_USAGE_DEFAULT, immed_size);
753 }
754
755 static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
756 struct r600_texture *rtex)
757 {
758 unsigned cl_width, cl_height, width, height;
759 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
760 unsigned num_pipes = rscreen->info.num_tile_pipes;
761
762 rtex->surface.htile_size = 0;
763
764 if (rscreen->chip_class <= EVERGREEN &&
765 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
766 return;
767
768 /* HW bug on R6xx. */
769 if (rscreen->chip_class == R600 &&
770 (rtex->resource.b.b.width0 > 7680 ||
771 rtex->resource.b.b.height0 > 7680))
772 return;
773
774 switch (num_pipes) {
775 case 1:
776 cl_width = 32;
777 cl_height = 16;
778 break;
779 case 2:
780 cl_width = 32;
781 cl_height = 32;
782 break;
783 case 4:
784 cl_width = 64;
785 cl_height = 32;
786 break;
787 case 8:
788 cl_width = 64;
789 cl_height = 64;
790 break;
791 case 16:
792 cl_width = 128;
793 cl_height = 64;
794 break;
795 default:
796 assert(0);
797 return;
798 }
799
800 width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
801 height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8);
802
803 slice_elements = (width * height) / (8 * 8);
804 slice_bytes = slice_elements * 4;
805
806 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
807 base_align = num_pipes * pipe_interleave_bytes;
808
809 rtex->surface.htile_alignment = base_align;
810 rtex->surface.htile_size =
811 util_num_layers(&rtex->resource.b.b, 0) *
812 align(slice_bytes, base_align);
813 }
814
815 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
816 struct r600_texture *rtex)
817 {
818 r600_texture_get_htile_size(rscreen, rtex);
819
820 if (!rtex->surface.htile_size)
821 return;
822
823 rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment);
824 rtex->size = rtex->htile_offset + rtex->surface.htile_size;
825 }
826
827 void r600_print_texture_info(struct r600_common_screen *rscreen,
828 struct r600_texture *rtex, struct u_log_context *log)
829 {
830 int i;
831
832 /* Common parameters. */
833 u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
834 "blk_h=%u, array_size=%u, last_level=%u, "
835 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
836 rtex->resource.b.b.width0, rtex->resource.b.b.height0,
837 rtex->resource.b.b.depth0, rtex->surface.blk_w,
838 rtex->surface.blk_h,
839 rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
840 rtex->surface.bpe, rtex->resource.b.b.nr_samples,
841 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
842
843 u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
844 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
845 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw,
846 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
847 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
848 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
849
850 if (rtex->fmask.size)
851 u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
852 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
853 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
854 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
855 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
856
857 if (rtex->cmask.size)
858 u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
859 "slice_tile_max=%u\n",
860 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
861 rtex->cmask.slice_tile_max);
862
863 if (rtex->htile_offset)
864 u_log_printf(log, " HTile: offset=%"PRIu64", size=%u "
865 "alignment=%u\n",
866 rtex->htile_offset, rtex->surface.htile_size,
867 rtex->surface.htile_alignment);
868
869 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
870 u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
871 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
872 "mode=%u, tiling_index = %u\n",
873 i, rtex->surface.u.legacy.level[i].offset,
874 (uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4,
875 u_minify(rtex->resource.b.b.width0, i),
876 u_minify(rtex->resource.b.b.height0, i),
877 u_minify(rtex->resource.b.b.depth0, i),
878 rtex->surface.u.legacy.level[i].nblk_x,
879 rtex->surface.u.legacy.level[i].nblk_y,
880 rtex->surface.u.legacy.level[i].mode,
881 rtex->surface.u.legacy.tiling_index[i]);
882
883 if (rtex->surface.has_stencil) {
884 u_log_printf(log, " StencilLayout: tilesplit=%u\n",
885 rtex->surface.u.legacy.stencil_tile_split);
886 for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
887 u_log_printf(log, " StencilLevel[%i]: offset=%"PRIu64", "
888 "slice_size=%"PRIu64", npix_x=%u, "
889 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
890 "mode=%u, tiling_index = %u\n",
891 i, rtex->surface.u.legacy.stencil_level[i].offset,
892 (uint64_t)rtex->surface.u.legacy.stencil_level[i].slice_size_dw * 4,
893 u_minify(rtex->resource.b.b.width0, i),
894 u_minify(rtex->resource.b.b.height0, i),
895 u_minify(rtex->resource.b.b.depth0, i),
896 rtex->surface.u.legacy.stencil_level[i].nblk_x,
897 rtex->surface.u.legacy.stencil_level[i].nblk_y,
898 rtex->surface.u.legacy.stencil_level[i].mode,
899 rtex->surface.u.legacy.stencil_tiling_index[i]);
900 }
901 }
902 }
903
904 /* Common processing for r600_texture_create and r600_texture_from_handle */
905 static struct r600_texture *
906 r600_texture_create_object(struct pipe_screen *screen,
907 const struct pipe_resource *base,
908 struct pb_buffer *buf,
909 struct radeon_surf *surface)
910 {
911 struct r600_texture *rtex;
912 struct r600_resource *resource;
913 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
914
915 rtex = CALLOC_STRUCT(r600_texture);
916 if (!rtex)
917 return NULL;
918
919 resource = &rtex->resource;
920 resource->b.b = *base;
921 resource->b.b.next = NULL;
922 resource->b.vtbl = &r600_texture_vtbl;
923 pipe_reference_init(&resource->b.b.reference, 1);
924 resource->b.b.screen = screen;
925
926 /* don't include stencil-only formats which we don't support for rendering */
927 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
928
929 rtex->surface = *surface;
930 rtex->size = rtex->surface.surf_size;
931 rtex->db_render_format = base->format;
932
933 /* Tiled depth textures utilize the non-displayable tile order.
934 * This must be done after r600_setup_surface.
935 * Applies to R600-Cayman. */
936 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.u.legacy.level[0].mode >= RADEON_SURF_MODE_1D;
937 /* Applies to GCN. */
938 rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
939
940 if (rtex->is_depth) {
941 if (base->flags & (R600_RESOURCE_FLAG_TRANSFER |
942 R600_RESOURCE_FLAG_FLUSHED_DEPTH) ||
943 rscreen->chip_class >= EVERGREEN) {
944 rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
945 rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
946 } else {
947 if (rtex->resource.b.b.nr_samples <= 1 &&
948 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
949 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT))
950 rtex->can_sample_z = true;
951 }
952
953 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
954 R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
955 rtex->db_compatible = true;
956
957 if (!(rscreen->debug_flags & DBG_NO_HYPERZ))
958 r600_texture_allocate_htile(rscreen, rtex);
959 }
960 } else {
961 if (base->nr_samples > 1) {
962 if (!buf) {
963 r600_texture_allocate_fmask(rscreen, rtex);
964 r600_texture_allocate_cmask(rscreen, rtex);
965 rtex->cmask_buffer = &rtex->resource;
966 }
967 if (!rtex->fmask.size || !rtex->cmask.size) {
968 FREE(rtex);
969 return NULL;
970 }
971 }
972 }
973
974 /* Now create the backing buffer. */
975 if (!buf) {
976 r600_init_resource_fields(rscreen, resource, rtex->size,
977 rtex->surface.surf_alignment);
978
979 if (!r600_alloc_resource(rscreen, resource)) {
980 FREE(rtex);
981 return NULL;
982 }
983 } else {
984 resource->buf = buf;
985 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
986 resource->bo_size = buf->size;
987 resource->bo_alignment = buf->alignment;
988 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
989 if (resource->domains & RADEON_DOMAIN_VRAM)
990 resource->vram_usage = buf->size;
991 else if (resource->domains & RADEON_DOMAIN_GTT)
992 resource->gart_usage = buf->size;
993 }
994
995 if (rtex->cmask.size) {
996 /* Initialize the cmask to 0xCC (= compressed state). */
997 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
998 rtex->cmask.offset, rtex->cmask.size,
999 0xCCCCCCCC);
1000 }
1001 if (rtex->htile_offset) {
1002 uint32_t clear_value = 0;
1003
1004 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
1005 rtex->htile_offset,
1006 rtex->surface.htile_size,
1007 clear_value);
1008 }
1009
1010 /* Initialize the CMASK base register value. */
1011 rtex->cmask.base_address_reg =
1012 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1013
1014 if (rscreen->debug_flags & DBG_VM) {
1015 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1016 rtex->resource.gpu_address,
1017 rtex->resource.gpu_address + rtex->resource.buf->size,
1018 base->width0, base->height0, util_num_layers(base, 0), base->last_level+1,
1019 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
1020 }
1021
1022 if (rscreen->debug_flags & DBG_TEX) {
1023 puts("Texture:");
1024 struct u_log_context log;
1025 u_log_context_init(&log);
1026 r600_print_texture_info(rscreen, rtex, &log);
1027 u_log_new_page_print(&log, stdout);
1028 fflush(stdout);
1029 u_log_context_destroy(&log);
1030 }
1031
1032 return rtex;
1033 }
1034
1035 static enum radeon_surf_mode
1036 r600_choose_tiling(struct r600_common_screen *rscreen,
1037 const struct pipe_resource *templ)
1038 {
1039 const struct util_format_description *desc = util_format_description(templ->format);
1040 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
1041 bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
1042 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
1043
1044 /* MSAA resources must be 2D tiled. */
1045 if (templ->nr_samples > 1)
1046 return RADEON_SURF_MODE_2D;
1047
1048 /* Transfer resources should be linear. */
1049 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
1050 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1051
1052 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1053 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
1054 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
1055 (templ->target == PIPE_TEXTURE_2D ||
1056 templ->target == PIPE_TEXTURE_3D))
1057 force_tiling = true;
1058
1059 /* Handle common candidates for the linear mode.
1060 * Compressed textures and DB surfaces must always be tiled.
1061 */
1062 if (!force_tiling &&
1063 !is_depth_stencil &&
1064 !util_format_is_compressed(templ->format)) {
1065 if (rscreen->debug_flags & DBG_NO_TILING)
1066 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1067
1068 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1069 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
1070 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1071
1072 if (templ->bind & PIPE_BIND_LINEAR)
1073 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1074
1075 /* 1D textures should be linear - fixes image operations on 1d */
1076 if (templ->target == PIPE_TEXTURE_1D ||
1077 templ->target == PIPE_TEXTURE_1D_ARRAY)
1078 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1079
1080 /* Textures likely to be mapped often. */
1081 if (templ->usage == PIPE_USAGE_STAGING ||
1082 templ->usage == PIPE_USAGE_STREAM)
1083 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1084 }
1085
1086 /* Make small textures 1D tiled. */
1087 if (templ->width0 <= 16 || templ->height0 <= 16 ||
1088 (rscreen->debug_flags & DBG_NO_2D_TILING))
1089 return RADEON_SURF_MODE_1D;
1090
1091 /* The allocator will switch to 1D if needed. */
1092 return RADEON_SURF_MODE_2D;
1093 }
1094
1095 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
1096 const struct pipe_resource *templ)
1097 {
1098 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1099 struct radeon_surf surface = {0};
1100 bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1101 int r;
1102
1103 r = r600_init_surface(rscreen, &surface, templ,
1104 r600_choose_tiling(rscreen, templ), 0, 0,
1105 false, false, is_flushed_depth);
1106 if (r) {
1107 return NULL;
1108 }
1109
1110 return (struct pipe_resource *)
1111 r600_texture_create_object(screen, templ, NULL, &surface);
1112 }
1113
1114 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1115 const struct pipe_resource *templ,
1116 struct winsys_handle *whandle,
1117 unsigned usage)
1118 {
1119 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1120 struct pb_buffer *buf = NULL;
1121 unsigned stride = 0, offset = 0;
1122 enum radeon_surf_mode array_mode;
1123 struct radeon_surf surface = {};
1124 int r;
1125 struct radeon_bo_metadata metadata = {};
1126 struct r600_texture *rtex;
1127 bool is_scanout;
1128
1129 /* Support only 2D textures without mipmaps */
1130 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1131 templ->depth0 != 1 || templ->last_level != 0)
1132 return NULL;
1133
1134 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1135 rscreen->info.max_alignment,
1136 &stride, &offset);
1137 if (!buf)
1138 return NULL;
1139
1140 rscreen->ws->buffer_get_metadata(buf, &metadata);
1141 r600_surface_import_metadata(rscreen, &surface, &metadata,
1142 &array_mode, &is_scanout);
1143
1144 r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
1145 offset, true, is_scanout, false);
1146 if (r) {
1147 return NULL;
1148 }
1149
1150 rtex = r600_texture_create_object(screen, templ, buf, &surface);
1151 if (!rtex)
1152 return NULL;
1153
1154 rtex->resource.b.is_shared = true;
1155 rtex->resource.external_usage = usage;
1156
1157 if (rscreen->apply_opaque_metadata)
1158 rscreen->apply_opaque_metadata(rscreen, rtex, &metadata);
1159
1160 assert(rtex->surface.tile_swizzle == 0);
1161 return &rtex->resource.b.b;
1162 }
1163
1164 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1165 struct pipe_resource *texture,
1166 struct r600_texture **staging)
1167 {
1168 struct r600_texture *rtex = (struct r600_texture*)texture;
1169 struct pipe_resource resource;
1170 struct r600_texture **flushed_depth_texture = staging ?
1171 staging : &rtex->flushed_depth_texture;
1172 enum pipe_format pipe_format = texture->format;
1173
1174 if (!staging) {
1175 if (rtex->flushed_depth_texture)
1176 return true; /* it's ready */
1177
1178 if (!rtex->can_sample_z && rtex->can_sample_s) {
1179 switch (pipe_format) {
1180 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1181 /* Save memory by not allocating the S plane. */
1182 pipe_format = PIPE_FORMAT_Z32_FLOAT;
1183 break;
1184 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1185 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1186 /* Save memory bandwidth by not copying the
1187 * stencil part during flush.
1188 *
1189 * This potentially increases memory bandwidth
1190 * if an application uses both Z and S texturing
1191 * simultaneously (a flushed Z24S8 texture
1192 * would be stored compactly), but how often
1193 * does that really happen?
1194 */
1195 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
1196 break;
1197 default:;
1198 }
1199 } else if (!rtex->can_sample_s && rtex->can_sample_z) {
1200 assert(util_format_has_stencil(util_format_description(pipe_format)));
1201
1202 /* DB->CB copies to an 8bpp surface don't work. */
1203 pipe_format = PIPE_FORMAT_X24S8_UINT;
1204 }
1205 }
1206
1207 memset(&resource, 0, sizeof(resource));
1208 resource.target = texture->target;
1209 resource.format = pipe_format;
1210 resource.width0 = texture->width0;
1211 resource.height0 = texture->height0;
1212 resource.depth0 = texture->depth0;
1213 resource.array_size = texture->array_size;
1214 resource.last_level = texture->last_level;
1215 resource.nr_samples = texture->nr_samples;
1216 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1217 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1218 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1219
1220 if (staging)
1221 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1222
1223 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1224 if (*flushed_depth_texture == NULL) {
1225 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1226 return false;
1227 }
1228
1229 (*flushed_depth_texture)->non_disp_tiling = false;
1230 return true;
1231 }
1232
1233 /**
1234 * Initialize the pipe_resource descriptor to be of the same size as the box,
1235 * which is supposed to hold a subregion of the texture "orig" at the given
1236 * mipmap level.
1237 */
1238 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1239 struct pipe_resource *orig,
1240 const struct pipe_box *box,
1241 unsigned level, unsigned flags)
1242 {
1243 memset(res, 0, sizeof(*res));
1244 res->format = orig->format;
1245 res->width0 = box->width;
1246 res->height0 = box->height;
1247 res->depth0 = 1;
1248 res->array_size = 1;
1249 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1250 res->flags = flags;
1251
1252 /* We must set the correct texture target and dimensions for a 3D box. */
1253 if (box->depth > 1 && util_max_layer(orig, level) > 0) {
1254 res->target = PIPE_TEXTURE_2D_ARRAY;
1255 res->array_size = box->depth;
1256 } else {
1257 res->target = PIPE_TEXTURE_2D;
1258 }
1259 }
1260
1261 static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen,
1262 struct r600_texture *rtex,
1263 unsigned transfer_usage,
1264 const struct pipe_box *box)
1265 {
1266 /* r600g doesn't react to dirty_tex_descriptor_counter */
1267 return rscreen->chip_class >= GFX6 &&
1268 !rtex->resource.b.is_shared &&
1269 !(transfer_usage & PIPE_TRANSFER_READ) &&
1270 rtex->resource.b.b.last_level == 0 &&
1271 util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
1272 box->x, box->y, box->z,
1273 box->width, box->height,
1274 box->depth);
1275 }
1276
1277 static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
1278 struct r600_texture *rtex)
1279 {
1280 struct r600_common_screen *rscreen = rctx->screen;
1281
1282 /* There is no point in discarding depth and tiled buffers. */
1283 assert(!rtex->is_depth);
1284 assert(rtex->surface.is_linear);
1285
1286 /* Reallocate the buffer in the same pipe_resource. */
1287 r600_alloc_resource(rscreen, &rtex->resource);
1288
1289 /* Initialize the CMASK base address (needed even without CMASK). */
1290 rtex->cmask.base_address_reg =
1291 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1292
1293 p_atomic_inc(&rscreen->dirty_tex_counter);
1294
1295 rctx->num_alloc_tex_transfer_bytes += rtex->size;
1296 }
1297
1298 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1299 struct pipe_resource *texture,
1300 unsigned level,
1301 unsigned usage,
1302 const struct pipe_box *box,
1303 struct pipe_transfer **ptransfer)
1304 {
1305 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1306 struct r600_texture *rtex = (struct r600_texture*)texture;
1307 struct r600_transfer *trans;
1308 struct r600_resource *buf;
1309 unsigned offset = 0;
1310 char *map;
1311 bool use_staging_texture = false;
1312
1313 assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
1314 assert(box->width && box->height && box->depth);
1315
1316 /* Depth textures use staging unconditionally. */
1317 if (!rtex->is_depth) {
1318 /* Degrade the tile mode if we get too many transfers on APUs.
1319 * On dGPUs, the staging texture is always faster.
1320 * Only count uploads that are at least 4x4 pixels large.
1321 */
1322 if (!rctx->screen->info.has_dedicated_vram &&
1323 level == 0 &&
1324 box->width >= 4 && box->height >= 4 &&
1325 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
1326 bool can_invalidate =
1327 r600_can_invalidate_texture(rctx->screen, rtex,
1328 usage, box);
1329
1330 r600_reallocate_texture_inplace(rctx, rtex,
1331 PIPE_BIND_LINEAR,
1332 can_invalidate);
1333 }
1334
1335 /* Tiled textures need to be converted into a linear texture for CPU
1336 * access. The staging texture is always linear and is placed in GART.
1337 *
1338 * Reading from VRAM or GTT WC is slow, always use the staging
1339 * texture in this case.
1340 *
1341 * Use the staging texture for uploads if the underlying BO
1342 * is busy.
1343 */
1344 if (!rtex->surface.is_linear)
1345 use_staging_texture = true;
1346 else if (usage & PIPE_TRANSFER_READ)
1347 use_staging_texture =
1348 rtex->resource.domains & RADEON_DOMAIN_VRAM ||
1349 rtex->resource.flags & RADEON_FLAG_GTT_WC;
1350 /* Write & linear only: */
1351 else if (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf,
1352 RADEON_USAGE_READWRITE) ||
1353 !rctx->ws->buffer_wait(rtex->resource.buf, 0,
1354 RADEON_USAGE_READWRITE)) {
1355 /* It's busy. */
1356 if (r600_can_invalidate_texture(rctx->screen, rtex,
1357 usage, box))
1358 r600_texture_invalidate_storage(rctx, rtex);
1359 else
1360 use_staging_texture = true;
1361 }
1362 }
1363
1364 trans = CALLOC_STRUCT(r600_transfer);
1365 if (!trans)
1366 return NULL;
1367 pipe_resource_reference(&trans->b.b.resource, texture);
1368 trans->b.b.level = level;
1369 trans->b.b.usage = usage;
1370 trans->b.b.box = *box;
1371
1372 if (rtex->is_depth) {
1373 struct r600_texture *staging_depth;
1374
1375 if (rtex->resource.b.b.nr_samples > 1) {
1376 /* MSAA depth buffers need to be converted to single sample buffers.
1377 *
1378 * Mapping MSAA depth buffers can occur if ReadPixels is called
1379 * with a multisample GLX visual.
1380 *
1381 * First downsample the depth buffer to a temporary texture,
1382 * then decompress the temporary one to staging.
1383 *
1384 * Only the region being mapped is transfered.
1385 */
1386 struct pipe_resource resource;
1387
1388 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1389
1390 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1391 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1392 FREE(trans);
1393 return NULL;
1394 }
1395
1396 if (usage & PIPE_TRANSFER_READ) {
1397 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1398 if (!temp) {
1399 R600_ERR("failed to create a temporary depth texture\n");
1400 FREE(trans);
1401 return NULL;
1402 }
1403
1404 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1405 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1406 0, 0, 0, box->depth, 0, 0);
1407 pipe_resource_reference(&temp, NULL);
1408 }
1409
1410 /* Just get the strides. */
1411 r600_texture_get_offset(rctx->screen, staging_depth, level, NULL,
1412 &trans->b.b.stride,
1413 &trans->b.b.layer_stride);
1414 } else {
1415 /* XXX: only readback the rectangle which is being mapped? */
1416 /* XXX: when discard is true, no need to read back from depth texture */
1417 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1418 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1419 FREE(trans);
1420 return NULL;
1421 }
1422
1423 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1424 level, level,
1425 box->z, box->z + box->depth - 1,
1426 0, 0);
1427
1428 offset = r600_texture_get_offset(rctx->screen, staging_depth,
1429 level, box,
1430 &trans->b.b.stride,
1431 &trans->b.b.layer_stride);
1432 }
1433
1434 trans->staging = (struct r600_resource*)staging_depth;
1435 buf = trans->staging;
1436 } else if (use_staging_texture) {
1437 struct pipe_resource resource;
1438 struct r600_texture *staging;
1439
1440 r600_init_temp_resource_from_box(&resource, texture, box, level,
1441 R600_RESOURCE_FLAG_TRANSFER);
1442 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1443 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1444
1445 /* Create the temporary texture. */
1446 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1447 if (!staging) {
1448 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1449 FREE(trans);
1450 return NULL;
1451 }
1452 trans->staging = &staging->resource;
1453
1454 /* Just get the strides. */
1455 r600_texture_get_offset(rctx->screen, staging, 0, NULL,
1456 &trans->b.b.stride,
1457 &trans->b.b.layer_stride);
1458
1459 if (usage & PIPE_TRANSFER_READ)
1460 r600_copy_to_staging_texture(ctx, trans);
1461 else
1462 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1463
1464 buf = trans->staging;
1465 } else {
1466 /* the resource is mapped directly */
1467 offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
1468 &trans->b.b.stride,
1469 &trans->b.b.layer_stride);
1470 buf = &rtex->resource;
1471 }
1472
1473 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1474 r600_resource_reference(&trans->staging, NULL);
1475 FREE(trans);
1476 return NULL;
1477 }
1478
1479 *ptransfer = &trans->b.b;
1480 return map + offset;
1481 }
1482
1483 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1484 struct pipe_transfer* transfer)
1485 {
1486 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1487 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1488 struct pipe_resource *texture = transfer->resource;
1489 struct r600_texture *rtex = (struct r600_texture*)texture;
1490
1491 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1492 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1493 ctx->resource_copy_region(ctx, texture, transfer->level,
1494 transfer->box.x, transfer->box.y, transfer->box.z,
1495 &rtransfer->staging->b.b, transfer->level,
1496 &transfer->box);
1497 } else {
1498 r600_copy_from_staging_texture(ctx, rtransfer);
1499 }
1500 }
1501
1502 if (rtransfer->staging) {
1503 rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
1504 r600_resource_reference(&rtransfer->staging, NULL);
1505 }
1506
1507 /* Heuristic for {upload, draw, upload, draw, ..}:
1508 *
1509 * Flush the gfx IB if we've allocated too much texture storage.
1510 *
1511 * The idea is that we don't want to build IBs that use too much
1512 * memory and put pressure on the kernel memory manager and we also
1513 * want to make temporary and invalidated buffers go idle ASAP to
1514 * decrease the total memory usage or make them reusable. The memory
1515 * usage will be slightly higher than given here because of the buffer
1516 * cache in the winsys.
1517 *
1518 * The result is that the kernel memory manager is never a bottleneck.
1519 */
1520 if (rctx->num_alloc_tex_transfer_bytes > rctx->screen->info.gart_size / 4) {
1521 rctx->gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
1522 rctx->num_alloc_tex_transfer_bytes = 0;
1523 }
1524
1525 pipe_resource_reference(&transfer->resource, NULL);
1526 FREE(transfer);
1527 }
1528
1529 static const struct u_resource_vtbl r600_texture_vtbl =
1530 {
1531 NULL, /* get_handle */
1532 r600_texture_destroy, /* resource_destroy */
1533 r600_texture_transfer_map, /* transfer_map */
1534 u_default_transfer_flush_region, /* transfer_flush_region */
1535 r600_texture_transfer_unmap, /* transfer_unmap */
1536 };
1537
1538 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1539 struct pipe_resource *texture,
1540 const struct pipe_surface *templ,
1541 unsigned width0, unsigned height0,
1542 unsigned width, unsigned height)
1543 {
1544 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1545
1546 if (!surface)
1547 return NULL;
1548
1549 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1550 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1551
1552 pipe_reference_init(&surface->base.reference, 1);
1553 pipe_resource_reference(&surface->base.texture, texture);
1554 surface->base.context = pipe;
1555 surface->base.format = templ->format;
1556 surface->base.width = width;
1557 surface->base.height = height;
1558 surface->base.u = templ->u;
1559
1560 surface->width0 = width0;
1561 surface->height0 = height0;
1562
1563 return &surface->base;
1564 }
1565
1566 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1567 struct pipe_resource *tex,
1568 const struct pipe_surface *templ)
1569 {
1570 unsigned level = templ->u.tex.level;
1571 unsigned width = u_minify(tex->width0, level);
1572 unsigned height = u_minify(tex->height0, level);
1573 unsigned width0 = tex->width0;
1574 unsigned height0 = tex->height0;
1575
1576 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1577 const struct util_format_description *tex_desc
1578 = util_format_description(tex->format);
1579 const struct util_format_description *templ_desc
1580 = util_format_description(templ->format);
1581
1582 assert(tex_desc->block.bits == templ_desc->block.bits);
1583
1584 /* Adjust size of surface if and only if the block width or
1585 * height is changed. */
1586 if (tex_desc->block.width != templ_desc->block.width ||
1587 tex_desc->block.height != templ_desc->block.height) {
1588 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1589 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1590
1591 width = nblks_x * templ_desc->block.width;
1592 height = nblks_y * templ_desc->block.height;
1593
1594 width0 = util_format_get_nblocksx(tex->format, width0);
1595 height0 = util_format_get_nblocksy(tex->format, height0);
1596 }
1597 }
1598
1599 return r600_create_surface_custom(pipe, tex, templ,
1600 width0, height0,
1601 width, height);
1602 }
1603
1604 static void r600_surface_destroy(struct pipe_context *pipe,
1605 struct pipe_surface *surface)
1606 {
1607 struct r600_surface *surf = (struct r600_surface*)surface;
1608 r600_resource_reference(&surf->cb_buffer_fmask, NULL);
1609 r600_resource_reference(&surf->cb_buffer_cmask, NULL);
1610 pipe_resource_reference(&surface->texture, NULL);
1611 FREE(surface);
1612 }
1613
1614 static void r600_clear_texture(struct pipe_context *pipe,
1615 struct pipe_resource *tex,
1616 unsigned level,
1617 const struct pipe_box *box,
1618 const void *data)
1619 {
1620 struct pipe_screen *screen = pipe->screen;
1621 struct r600_texture *rtex = (struct r600_texture*)tex;
1622 struct pipe_surface tmpl = {{0}};
1623 struct pipe_surface *sf;
1624 const struct util_format_description *desc =
1625 util_format_description(tex->format);
1626
1627 tmpl.format = tex->format;
1628 tmpl.u.tex.first_layer = box->z;
1629 tmpl.u.tex.last_layer = box->z + box->depth - 1;
1630 tmpl.u.tex.level = level;
1631 sf = pipe->create_surface(pipe, tex, &tmpl);
1632 if (!sf)
1633 return;
1634
1635 if (rtex->is_depth) {
1636 unsigned clear;
1637 float depth;
1638 uint8_t stencil = 0;
1639
1640 /* Depth is always present. */
1641 clear = PIPE_CLEAR_DEPTH;
1642 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
1643
1644 if (rtex->surface.has_stencil) {
1645 clear |= PIPE_CLEAR_STENCIL;
1646 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
1647 }
1648
1649 pipe->clear_depth_stencil(pipe, sf, clear, depth, stencil,
1650 box->x, box->y,
1651 box->width, box->height, false);
1652 } else {
1653 union pipe_color_union color;
1654
1655 /* pipe_color_union requires the full vec4 representation. */
1656 if (util_format_is_pure_uint(tex->format))
1657 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
1658 else if (util_format_is_pure_sint(tex->format))
1659 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
1660 else
1661 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
1662
1663 if (screen->is_format_supported(screen, tex->format,
1664 tex->target, 0, 0,
1665 PIPE_BIND_RENDER_TARGET)) {
1666 pipe->clear_render_target(pipe, sf, &color,
1667 box->x, box->y,
1668 box->width, box->height, false);
1669 } else {
1670 /* Software fallback - just for R9G9B9E5_FLOAT */
1671 util_clear_render_target(pipe, sf, &color,
1672 box->x, box->y,
1673 box->width, box->height);
1674 }
1675 }
1676 pipe_surface_reference(&sf, NULL);
1677 }
1678
1679 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap)
1680 {
1681 const struct util_format_description *desc = util_format_description(format);
1682
1683 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1684
1685 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1686 return V_0280A0_SWAP_STD;
1687
1688 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1689 return ~0U;
1690
1691 switch (desc->nr_channels) {
1692 case 1:
1693 if (HAS_SWIZZLE(0,X))
1694 return V_0280A0_SWAP_STD; /* X___ */
1695 else if (HAS_SWIZZLE(3,X))
1696 return V_0280A0_SWAP_ALT_REV; /* ___X */
1697 break;
1698 case 2:
1699 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1700 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1701 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1702 return V_0280A0_SWAP_STD; /* XY__ */
1703 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1704 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1705 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1706 /* YX__ */
1707 return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV);
1708 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1709 return V_0280A0_SWAP_ALT; /* X__Y */
1710 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1711 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1712 break;
1713 case 3:
1714 if (HAS_SWIZZLE(0,X))
1715 return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD);
1716 else if (HAS_SWIZZLE(0,Z))
1717 return V_0280A0_SWAP_STD_REV; /* ZYX */
1718 break;
1719 case 4:
1720 /* check the middle channels, the 1st and 4th channel can be NONE */
1721 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
1722 return V_0280A0_SWAP_STD; /* XYZW */
1723 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
1724 return V_0280A0_SWAP_STD_REV; /* WZYX */
1725 } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
1726 return V_0280A0_SWAP_ALT; /* ZYXW */
1727 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
1728 /* YZWX */
1729 if (desc->is_array)
1730 return V_0280A0_SWAP_ALT_REV;
1731 else
1732 return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV);
1733 }
1734 break;
1735 }
1736 return ~0U;
1737 }
1738
1739 /* FAST COLOR CLEAR */
1740
1741 static void evergreen_set_clear_color(struct r600_texture *rtex,
1742 enum pipe_format surface_format,
1743 const union pipe_color_union *color)
1744 {
1745 union util_color uc;
1746
1747 memset(&uc, 0, sizeof(uc));
1748
1749 if (rtex->surface.bpe == 16) {
1750 /* DCC fast clear only:
1751 * CLEAR_WORD0 = R = G = B
1752 * CLEAR_WORD1 = A
1753 */
1754 assert(color->ui[0] == color->ui[1] &&
1755 color->ui[0] == color->ui[2]);
1756 uc.ui[0] = color->ui[0];
1757 uc.ui[1] = color->ui[3];
1758 } else if (util_format_is_pure_uint(surface_format)) {
1759 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1760 } else if (util_format_is_pure_sint(surface_format)) {
1761 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1762 } else {
1763 util_pack_color(color->f, surface_format, &uc);
1764 }
1765
1766 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1767 }
1768
1769 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1770 struct pipe_framebuffer_state *fb,
1771 struct r600_atom *fb_state,
1772 unsigned *buffers, ubyte *dirty_cbufs,
1773 const union pipe_color_union *color)
1774 {
1775 int i;
1776
1777 /* This function is broken in BE, so just disable this path for now */
1778 #ifdef PIPE_ARCH_BIG_ENDIAN
1779 return;
1780 #endif
1781
1782 if (rctx->render_cond)
1783 return;
1784
1785 for (i = 0; i < fb->nr_cbufs; i++) {
1786 struct r600_texture *tex;
1787 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1788
1789 if (!fb->cbufs[i])
1790 continue;
1791
1792 /* if this colorbuffer is not being cleared */
1793 if (!(*buffers & clear_bit))
1794 continue;
1795
1796 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1797
1798 /* the clear is allowed if all layers are bound */
1799 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1800 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1801 continue;
1802 }
1803
1804 /* cannot clear mipmapped textures */
1805 if (fb->cbufs[i]->texture->last_level != 0) {
1806 continue;
1807 }
1808
1809 /* only supported on tiled surfaces */
1810 if (tex->surface.is_linear) {
1811 continue;
1812 }
1813
1814 /* shared textures can't use fast clear without an explicit flush,
1815 * because there is no way to communicate the clear color among
1816 * all clients
1817 */
1818 if (tex->resource.b.is_shared &&
1819 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1820 continue;
1821
1822 /* Use a slow clear for small surfaces where the cost of
1823 * the eliminate pass can be higher than the benefit of fast
1824 * clear. AMDGPU-pro does this, but the numbers may differ.
1825 *
1826 * This helps on both dGPUs and APUs, even small ones.
1827 */
1828 if (tex->resource.b.b.nr_samples <= 1 &&
1829 tex->resource.b.b.width0 * tex->resource.b.b.height0 <= 300 * 300)
1830 continue;
1831
1832 {
1833 /* 128-bit formats are unusupported */
1834 if (tex->surface.bpe > 8) {
1835 continue;
1836 }
1837
1838 /* ensure CMASK is enabled */
1839 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1840 if (tex->cmask.size == 0) {
1841 continue;
1842 }
1843
1844 /* Do the fast clear. */
1845 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1846 tex->cmask.offset, tex->cmask.size, 0,
1847 R600_COHERENCY_CB_META);
1848
1849 bool need_compressed_update = !tex->dirty_level_mask;
1850
1851 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1852
1853 if (need_compressed_update)
1854 p_atomic_inc(&rctx->screen->compressed_colortex_counter);
1855 }
1856
1857 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1858
1859 if (dirty_cbufs)
1860 *dirty_cbufs |= 1 << i;
1861 rctx->set_atom_dirty(rctx, fb_state, true);
1862 *buffers &= ~clear_bit;
1863 }
1864 }
1865
1866 static struct pipe_memory_object *
1867 r600_memobj_from_handle(struct pipe_screen *screen,
1868 struct winsys_handle *whandle,
1869 bool dedicated)
1870 {
1871 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1872 struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
1873 struct pb_buffer *buf = NULL;
1874 uint32_t stride, offset;
1875
1876 if (!memobj)
1877 return NULL;
1878
1879 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1880 rscreen->info.max_alignment,
1881 &stride, &offset);
1882 if (!buf) {
1883 free(memobj);
1884 return NULL;
1885 }
1886
1887 memobj->b.dedicated = dedicated;
1888 memobj->buf = buf;
1889 memobj->stride = stride;
1890 memobj->offset = offset;
1891
1892 return (struct pipe_memory_object *)memobj;
1893
1894 }
1895
1896 static void
1897 r600_memobj_destroy(struct pipe_screen *screen,
1898 struct pipe_memory_object *_memobj)
1899 {
1900 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1901
1902 pb_reference(&memobj->buf, NULL);
1903 free(memobj);
1904 }
1905
1906 static struct pipe_resource *
1907 r600_texture_from_memobj(struct pipe_screen *screen,
1908 const struct pipe_resource *templ,
1909 struct pipe_memory_object *_memobj,
1910 uint64_t offset)
1911 {
1912 int r;
1913 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1914 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1915 struct r600_texture *rtex;
1916 struct radeon_surf surface = {};
1917 struct radeon_bo_metadata metadata = {};
1918 enum radeon_surf_mode array_mode;
1919 bool is_scanout;
1920 struct pb_buffer *buf = NULL;
1921
1922 if (memobj->b.dedicated) {
1923 rscreen->ws->buffer_get_metadata(memobj->buf, &metadata);
1924 r600_surface_import_metadata(rscreen, &surface, &metadata,
1925 &array_mode, &is_scanout);
1926 } else {
1927 /**
1928 * The bo metadata is unset for un-dedicated images. So we fall
1929 * back to linear. See answer to question 5 of the
1930 * VK_KHX_external_memory spec for some details.
1931 *
1932 * It is possible that this case isn't going to work if the
1933 * surface pitch isn't correctly aligned by default.
1934 *
1935 * In order to support it correctly we require multi-image
1936 * metadata to be syncrhonized between radv and radeonsi. The
1937 * semantics of associating multiple image metadata to a memory
1938 * object on the vulkan export side are not concretely defined
1939 * either.
1940 *
1941 * All the use cases we are aware of at the moment for memory
1942 * objects use dedicated allocations. So lets keep the initial
1943 * implementation simple.
1944 *
1945 * A possible alternative is to attempt to reconstruct the
1946 * tiling information when the TexParameter TEXTURE_TILING_EXT
1947 * is set.
1948 */
1949 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1950 is_scanout = false;
1951
1952 }
1953
1954 r = r600_init_surface(rscreen, &surface, templ,
1955 array_mode, memobj->stride,
1956 offset, true, is_scanout,
1957 false);
1958 if (r)
1959 return NULL;
1960
1961 rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface);
1962 if (!rtex)
1963 return NULL;
1964
1965 /* r600_texture_create_object doesn't increment refcount of
1966 * memobj->buf, so increment it here.
1967 */
1968 pb_reference(&buf, memobj->buf);
1969
1970 rtex->resource.b.is_shared = true;
1971 rtex->resource.external_usage = PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE;
1972
1973 if (rscreen->apply_opaque_metadata)
1974 rscreen->apply_opaque_metadata(rscreen, rtex, &metadata);
1975
1976 return &rtex->resource.b.b;
1977 }
1978
1979 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1980 {
1981 rscreen->b.resource_from_handle = r600_texture_from_handle;
1982 rscreen->b.resource_get_handle = r600_texture_get_handle;
1983 rscreen->b.resource_get_info = r600_texture_get_info;
1984 rscreen->b.resource_from_memobj = r600_texture_from_memobj;
1985 rscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
1986 rscreen->b.memobj_destroy = r600_memobj_destroy;
1987 }
1988
1989 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1990 {
1991 rctx->b.create_surface = r600_create_surface;
1992 rctx->b.surface_destroy = r600_surface_destroy;
1993 rctx->b.clear_texture = r600_clear_texture;
1994 }