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r600g: work around ddx over alignment
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34
35 /* Copy from a full GPU texture to a transfer's staging one. */
36 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
37 {
38 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
39 struct pipe_resource *dst = &rtransfer->staging->b.b;
40 struct pipe_resource *src = transfer->resource;
41
42 if (src->nr_samples <= 1) {
43 ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
44 src, transfer->level, &transfer->box);
45 } else {
46 /* Resolve the resource. */
47 struct pipe_blit_info blit;
48
49 memset(&blit, 0, sizeof(blit));
50 blit.src.resource = src;
51 blit.src.format = src->format;
52 blit.src.level = transfer->level;
53 blit.src.box = transfer->box;
54 blit.dst.resource = dst;
55 blit.dst.format = dst->format;
56 blit.dst.box.width = transfer->box.width;
57 blit.dst.box.height = transfer->box.height;
58 blit.dst.box.depth = transfer->box.depth;
59 blit.mask = PIPE_MASK_RGBA;
60 blit.filter = PIPE_TEX_FILTER_NEAREST;
61
62 ctx->blit(ctx, &blit);
63 }
64 }
65
66 /* Copy from a transfer's staging texture to a full GPU one. */
67 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
68 {
69 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
70 struct pipe_resource *texture = transfer->resource;
71 struct pipe_box sbox;
72
73 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
74
75 ctx->resource_copy_region(ctx, texture, transfer->level,
76 transfer->box.x, transfer->box.y, transfer->box.z,
77 &rtransfer->staging->b.b,
78 0, &sbox);
79 }
80
81 unsigned r600_texture_get_offset(struct r600_texture *rtex,
82 unsigned level, unsigned layer)
83 {
84 return rtex->surface.level[level].offset +
85 layer * rtex->surface.level[level].slice_size;
86 }
87
88 static int r600_init_surface(struct r600_screen *rscreen,
89 struct radeon_surface *surface,
90 const struct pipe_resource *ptex,
91 unsigned array_mode,
92 bool is_flushed_depth,
93 bool from_ddx)
94 {
95 const struct util_format_description *desc =
96 util_format_description(ptex->format);
97 bool is_depth, is_stencil;
98
99 is_depth = util_format_has_depth(desc);
100 is_stencil = util_format_has_stencil(desc);
101
102 surface->npix_x = ptex->width0;
103 surface->npix_y = ptex->height0;
104 surface->npix_z = ptex->depth0;
105 surface->blk_w = util_format_get_blockwidth(ptex->format);
106 surface->blk_h = util_format_get_blockheight(ptex->format);
107 surface->blk_d = 1;
108 surface->array_size = 1;
109 surface->last_level = ptex->last_level;
110
111 if (from_ddx) {
112 surface->npix_y = align(surface->npix_y, 8);
113 }
114
115 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
116 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
117 surface->bpe = 4; /* stencil is allocated separately on evergreen */
118 } else {
119 surface->bpe = util_format_get_blocksize(ptex->format);
120 /* align byte per element on dword */
121 if (surface->bpe == 3) {
122 surface->bpe = 4;
123 }
124 }
125
126 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
127 surface->flags = 0;
128
129 switch (array_mode) {
130 case V_038000_ARRAY_1D_TILED_THIN1:
131 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
132 break;
133 case V_038000_ARRAY_2D_TILED_THIN1:
134 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
135 break;
136 case V_038000_ARRAY_LINEAR_ALIGNED:
137 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
138 break;
139 case V_038000_ARRAY_LINEAR_GENERAL:
140 default:
141 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
142 break;
143 }
144 switch (ptex->target) {
145 case PIPE_TEXTURE_1D:
146 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
147 break;
148 case PIPE_TEXTURE_RECT:
149 case PIPE_TEXTURE_2D:
150 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
151 break;
152 case PIPE_TEXTURE_3D:
153 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
154 break;
155 case PIPE_TEXTURE_1D_ARRAY:
156 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
157 surface->array_size = ptex->array_size;
158 break;
159 case PIPE_TEXTURE_2D_ARRAY:
160 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d layout for now */
161 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
162 surface->array_size = ptex->array_size;
163 break;
164 case PIPE_TEXTURE_CUBE:
165 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
166 break;
167 case PIPE_BUFFER:
168 default:
169 return -EINVAL;
170 }
171 if (ptex->bind & PIPE_BIND_SCANOUT) {
172 surface->flags |= RADEON_SURF_SCANOUT;
173 }
174
175 if (!is_flushed_depth && is_depth) {
176 surface->flags |= RADEON_SURF_ZBUFFER;
177
178 if (is_stencil) {
179 surface->flags |= RADEON_SURF_SBUFFER |
180 RADEON_SURF_HAS_SBUFFER_MIPTREE;
181 }
182 }
183 return 0;
184 }
185
186 static int r600_setup_surface(struct pipe_screen *screen,
187 struct r600_texture *rtex,
188 unsigned pitch_in_bytes_override)
189 {
190 struct pipe_resource *ptex = &rtex->resource.b.b;
191 struct r600_screen *rscreen = (struct r600_screen*)screen;
192 unsigned i;
193 int r;
194
195 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
196 if (r) {
197 return r;
198 }
199 rtex->size = rtex->surface.bo_size;
200 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
201 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
202 * for those
203 */
204 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
205 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
206 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
207 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
208 rtex->surface.stencil_offset =
209 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
210 }
211 }
212 for (i = 0; i <= ptex->last_level; i++) {
213 switch (rtex->surface.level[i].mode) {
214 case RADEON_SURF_MODE_LINEAR_ALIGNED:
215 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
216 break;
217 case RADEON_SURF_MODE_1D:
218 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
219 break;
220 case RADEON_SURF_MODE_2D:
221 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
222 break;
223 default:
224 case RADEON_SURF_MODE_LINEAR:
225 rtex->array_mode[i] = 0;
226 break;
227 }
228 }
229 return 0;
230 }
231
232 static boolean r600_texture_get_handle(struct pipe_screen* screen,
233 struct pipe_resource *ptex,
234 struct winsys_handle *whandle)
235 {
236 struct r600_texture *rtex = (struct r600_texture*)ptex;
237 struct r600_resource *resource = &rtex->resource;
238 struct radeon_surface *surface = &rtex->surface;
239 struct r600_screen *rscreen = (struct r600_screen*)screen;
240
241 rscreen->ws->buffer_set_tiling(resource->buf,
242 NULL,
243 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
244 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
245 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
246 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
247 surface->bankw, surface->bankh,
248 surface->tile_split,
249 surface->stencil_tile_split,
250 surface->mtilea,
251 rtex->surface.level[0].pitch_bytes);
252
253 return rscreen->ws->buffer_get_handle(resource->buf,
254 rtex->surface.level[0].pitch_bytes, whandle);
255 }
256
257 static void r600_texture_destroy(struct pipe_screen *screen,
258 struct pipe_resource *ptex)
259 {
260 struct r600_texture *rtex = (struct r600_texture*)ptex;
261 struct r600_resource *resource = &rtex->resource;
262
263 if (rtex->flushed_depth_texture)
264 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
265
266 pb_reference(&resource->buf, NULL);
267 FREE(rtex);
268 }
269
270 static const struct u_resource_vtbl r600_texture_vtbl;
271
272 /* The number of samples can be specified independently of the texture. */
273 void r600_texture_get_fmask_info(struct r600_screen *rscreen,
274 struct r600_texture *rtex,
275 unsigned nr_samples,
276 struct r600_fmask_info *out)
277 {
278 /* FMASK is allocated pretty much like an ordinary texture.
279 * Here we use bpe in the units of bits, not bytes. */
280 struct radeon_surface fmask = rtex->surface;
281
282 switch (nr_samples) {
283 case 2:
284 /* This should be 8,1, but we should set nsamples > 1
285 * for the allocator to treat it as a multisample surface.
286 * Let's set 4,2 then. */
287 case 4:
288 fmask.bpe = 4;
289 fmask.nsamples = 2;
290 break;
291 case 8:
292 fmask.bpe = 8;
293 fmask.nsamples = 4;
294 break;
295 case 16:
296 fmask.bpe = 16;
297 fmask.nsamples = 4;
298 break;
299 default:
300 R600_ERR("Invalid sample count for FMASK allocation.\n");
301 return;
302 }
303
304 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
305 if (rscreen->chip_class <= R700) {
306 fmask.bpe *= 2;
307 }
308
309 if (rscreen->chip_class >= EVERGREEN) {
310 fmask.bankh = nr_samples <= 4 ? 4 : 1;
311 }
312
313 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
314 R600_ERR("Got error in surface_init while allocating FMASK.\n");
315 return;
316 }
317 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
318
319 out->bank_height = fmask.bankh;
320 out->alignment = MAX2(256, fmask.bo_alignment);
321 out->size = (fmask.bo_size + 7) / 8;
322 }
323
324 static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
325 struct r600_texture *rtex)
326 {
327 struct r600_fmask_info fmask;
328
329 r600_texture_get_fmask_info(rscreen, rtex,
330 rtex->resource.b.b.nr_samples, &fmask);
331
332 /* Reserve space for FMASK while converting bits back to bytes. */
333 rtex->fmask_bank_height = fmask.bank_height;
334 rtex->fmask_offset = align(rtex->size, fmask.alignment);
335 rtex->fmask_size = fmask.size;
336 rtex->size = rtex->fmask_offset + rtex->fmask_size;
337 #if 0
338 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
339 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
340 #endif
341 }
342
343 void r600_texture_get_cmask_info(struct r600_screen *rscreen,
344 struct r600_texture *rtex,
345 struct r600_cmask_info *out)
346 {
347 unsigned cmask_tile_width = 8;
348 unsigned cmask_tile_height = 8;
349 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
350 unsigned element_bits = 4;
351 unsigned cmask_cache_bits = 1024;
352 unsigned num_pipes = rscreen->tiling_info.num_channels;
353 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
354
355 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
356 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
357 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
358 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
359 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
360
361 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
362 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
363
364 unsigned base_align = num_pipes * pipe_interleave_bytes;
365 unsigned slice_bytes =
366 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
367
368 assert(macro_tile_width % 128 == 0);
369 assert(macro_tile_height % 128 == 0);
370
371 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
372 out->alignment = MAX2(256, base_align);
373 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
374 }
375
376 static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
377 struct r600_texture *rtex)
378 {
379 struct r600_cmask_info cmask;
380
381 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
382
383 rtex->cmask_slice_tile_max = cmask.slice_tile_max;
384 rtex->cmask_offset = align(rtex->size, cmask.alignment);
385 rtex->cmask_size = cmask.size;
386 rtex->size = rtex->cmask_offset + rtex->cmask_size;
387 #if 0
388 printf("CMASK: macro tile width = %u, macro tile height = %u, "
389 "pitch elements = %u, height = %u, slice tile max = %u\n",
390 macro_tile_width, macro_tile_height, pitch_elements, height,
391 rtex->cmask_slice_tile_max);
392 #endif
393 }
394
395 DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "R600_PRINT_TEXDEPTH", FALSE);
396
397 static struct r600_texture *
398 r600_texture_create_object(struct pipe_screen *screen,
399 const struct pipe_resource *base,
400 unsigned pitch_in_bytes_override,
401 struct pb_buffer *buf,
402 boolean alloc_bo,
403 struct radeon_surface *surface)
404 {
405 struct r600_texture *rtex;
406 struct r600_resource *resource;
407 struct r600_screen *rscreen = (struct r600_screen*)screen;
408 int r;
409
410 rtex = CALLOC_STRUCT(r600_texture);
411 if (rtex == NULL)
412 return NULL;
413
414 resource = &rtex->resource;
415 resource->b.b = *base;
416 resource->b.vtbl = &r600_texture_vtbl;
417 pipe_reference_init(&resource->b.b.reference, 1);
418 resource->b.b.screen = screen;
419 rtex->pitch_override = pitch_in_bytes_override;
420
421 /* don't include stencil-only formats which we don't support for rendering */
422 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
423
424 rtex->surface = *surface;
425 r = r600_setup_surface(screen, rtex,
426 pitch_in_bytes_override);
427 if (r) {
428 FREE(rtex);
429 return NULL;
430 }
431
432 if (base->nr_samples > 1 && !rtex->is_depth && alloc_bo) {
433 r600_texture_allocate_cmask(rscreen, rtex);
434 r600_texture_allocate_fmask(rscreen, rtex);
435 }
436
437 if (!rtex->is_depth && base->nr_samples > 1 &&
438 (!rtex->fmask_size || !rtex->cmask_size)) {
439 FREE(rtex);
440 return NULL;
441 }
442
443 /* Tiled depth textures utilize the non-displayable tile order. */
444 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
445
446 /* Now create the backing buffer. */
447 if (!buf && alloc_bo) {
448 unsigned base_align = rtex->surface.bo_alignment;
449 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
450
451 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
452 FREE(rtex);
453 return NULL;
454 }
455 } else if (buf) {
456 /* This is usually the window framebuffer. We want it in VRAM, always. */
457 resource->buf = buf;
458 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
459 resource->domains = RADEON_DOMAIN_VRAM;
460 }
461
462 if (rtex->cmask_size) {
463 /* Initialize the cmask to 0xCC (= compressed state). */
464 char *ptr = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE);
465 memset(ptr + rtex->cmask_offset, 0xCC, rtex->cmask_size);
466 rscreen->ws->buffer_unmap(resource->cs_buf);
467 }
468
469 if (debug_get_option_print_texdepth() && rtex->is_depth && rtex->non_disp_tiling) {
470 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
471 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
472 "bpe=%u, nsamples=%u, flags=%u\n",
473 rtex->surface.npix_x, rtex->surface.npix_y,
474 rtex->surface.npix_z, rtex->surface.blk_w,
475 rtex->surface.blk_h, rtex->surface.blk_d,
476 rtex->surface.array_size, rtex->surface.last_level,
477 rtex->surface.bpe, rtex->surface.nsamples,
478 rtex->surface.flags);
479 if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
480 for (int i = 0; i <= rtex->surface.last_level; i++) {
481 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
482 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
483 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
484 i, (unsigned long long)rtex->surface.level[i].offset,
485 (unsigned long long)rtex->surface.level[i].slice_size,
486 rtex->surface.level[i].npix_x,
487 rtex->surface.level[i].npix_y,
488 rtex->surface.level[i].npix_z,
489 rtex->surface.level[i].nblk_x,
490 rtex->surface.level[i].nblk_y,
491 rtex->surface.level[i].nblk_z,
492 rtex->surface.level[i].pitch_bytes,
493 rtex->surface.level[i].mode);
494 }
495 }
496 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
497 for (int i = 0; i <= rtex->surface.last_level; i++) {
498 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
499 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
500 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
501 i, (unsigned long long)rtex->surface.stencil_level[i].offset,
502 (unsigned long long)rtex->surface.stencil_level[i].slice_size,
503 rtex->surface.stencil_level[i].npix_x,
504 rtex->surface.stencil_level[i].npix_y,
505 rtex->surface.stencil_level[i].npix_z,
506 rtex->surface.stencil_level[i].nblk_x,
507 rtex->surface.stencil_level[i].nblk_y,
508 rtex->surface.stencil_level[i].nblk_z,
509 rtex->surface.stencil_level[i].pitch_bytes,
510 rtex->surface.stencil_level[i].mode);
511 }
512 }
513 }
514 return rtex;
515 }
516
517 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
518 const struct pipe_resource *templ)
519 {
520 struct r600_screen *rscreen = (struct r600_screen*)screen;
521 struct radeon_surface surface;
522 const struct util_format_description *desc = util_format_description(templ->format);
523 unsigned array_mode;
524 int r;
525
526 /* Default tiling mode for staging textures. */
527 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
528
529 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
530 * because 422 formats are used for videos, which prefer linear buffers
531 * for fast uploads anyway. */
532 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
533 desc->layout != UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
534 if (!(templ->bind & PIPE_BIND_SCANOUT) &&
535 templ->usage != PIPE_USAGE_STAGING &&
536 templ->usage != PIPE_USAGE_STREAM &&
537 templ->target != PIPE_TEXTURE_1D &&
538 templ->target != PIPE_TEXTURE_1D_ARRAY &&
539 templ->height0 > 3) {
540 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
541 } else if (util_format_is_compressed(templ->format)) {
542 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
543 }
544 }
545
546 r = r600_init_surface(rscreen, &surface, templ, array_mode,
547 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH,
548 false);
549 if (r) {
550 return NULL;
551 }
552 r = rscreen->ws->surface_best(rscreen->ws, &surface);
553 if (r) {
554 return NULL;
555 }
556 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
557 0, NULL, TRUE, &surface);
558 }
559
560 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
561 struct pipe_resource *texture,
562 const struct pipe_surface *templ,
563 unsigned width, unsigned height)
564 {
565 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
566
567 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
568 if (surface == NULL)
569 return NULL;
570 pipe_reference_init(&surface->base.reference, 1);
571 pipe_resource_reference(&surface->base.texture, texture);
572 surface->base.context = pipe;
573 surface->base.format = templ->format;
574 surface->base.width = width;
575 surface->base.height = height;
576 surface->base.u = templ->u;
577 return &surface->base;
578 }
579
580 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
581 struct pipe_resource *texture,
582 const struct pipe_surface *templ)
583 {
584 struct r600_texture *rtex = (struct r600_texture*)texture;
585 unsigned level = templ->u.tex.level;
586
587 return r600_create_surface_custom(pipe, texture, templ,
588 rtex->surface.level[level].npix_x,
589 rtex->surface.level[level].npix_y);
590 }
591
592 static void r600_surface_destroy(struct pipe_context *pipe,
593 struct pipe_surface *surface)
594 {
595 struct r600_surface *surf = (struct r600_surface*)surface;
596 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
597 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
598 pipe_resource_reference(&surface->texture, NULL);
599 FREE(surface);
600 }
601
602 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
603 const struct pipe_resource *templ,
604 struct winsys_handle *whandle)
605 {
606 struct r600_screen *rscreen = (struct r600_screen*)screen;
607 struct pb_buffer *buf = NULL;
608 unsigned stride = 0;
609 unsigned array_mode = 0;
610 enum radeon_bo_layout micro, macro;
611 struct radeon_surface surface;
612 int r;
613
614 /* Support only 2D textures without mipmaps */
615 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
616 templ->depth0 != 1 || templ->last_level != 0)
617 return NULL;
618
619 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
620 if (!buf)
621 return NULL;
622
623 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
624 &surface.bankw, &surface.bankh,
625 &surface.tile_split,
626 &surface.stencil_tile_split,
627 &surface.mtilea);
628
629 if (macro == RADEON_LAYOUT_TILED)
630 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
631 else if (micro == RADEON_LAYOUT_TILED)
632 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
633 else
634 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
635
636 r = r600_init_surface(rscreen, &surface, templ, array_mode, false, true);
637 if (r) {
638 return NULL;
639 }
640 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
641 stride, buf, FALSE, &surface);
642 }
643
644 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
645 struct pipe_resource *texture,
646 struct r600_texture **staging)
647 {
648 struct r600_texture *rtex = (struct r600_texture*)texture;
649 struct pipe_resource resource;
650 struct r600_texture **flushed_depth_texture = staging ?
651 staging : &rtex->flushed_depth_texture;
652
653 if (!staging && rtex->flushed_depth_texture)
654 return true; /* it's ready */
655
656 resource.target = texture->target;
657 resource.format = texture->format;
658 resource.width0 = texture->width0;
659 resource.height0 = texture->height0;
660 resource.depth0 = texture->depth0;
661 resource.array_size = texture->array_size;
662 resource.last_level = texture->last_level;
663 resource.nr_samples = texture->nr_samples;
664 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
665 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
666 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
667
668 if (staging)
669 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
670
671 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
672 if (*flushed_depth_texture == NULL) {
673 R600_ERR("failed to create temporary texture to hold flushed depth\n");
674 return false;
675 }
676
677 (*flushed_depth_texture)->is_flushing_texture = TRUE;
678 (*flushed_depth_texture)->non_disp_tiling = false;
679 return true;
680 }
681
682 static void *r600_texture_transfer_map(struct pipe_context *ctx,
683 struct pipe_resource *texture,
684 unsigned level,
685 unsigned usage,
686 const struct pipe_box *box,
687 struct pipe_transfer **ptransfer)
688 {
689 struct r600_context *rctx = (struct r600_context*)ctx;
690 struct r600_texture *rtex = (struct r600_texture*)texture;
691 struct pipe_resource resource;
692 struct r600_transfer *trans;
693 boolean use_staging_texture = FALSE;
694 enum pipe_format format = texture->format;
695 struct radeon_winsys_cs_handle *buf;
696 unsigned offset = 0;
697 char *map;
698
699 if ((texture->bind & PIPE_BIND_GLOBAL) && texture->target == PIPE_BUFFER) {
700 return r600_compute_global_transfer_map(ctx, texture, level, usage, box, ptransfer);
701 }
702
703 /* We cannot map a tiled texture directly because the data is
704 * in a different order, therefore we do detiling using a blit.
705 *
706 * Also, use a temporary in GTT memory for read transfers, as
707 * the CPU is much happier reading out of cached system memory
708 * than uncached VRAM.
709 */
710 if (R600_TEX_IS_TILED(rtex, level)) {
711 use_staging_texture = TRUE;
712 }
713
714 /* Use a staging texture for uploads if the underlying BO is busy. */
715 if (!(usage & PIPE_TRANSFER_READ) &&
716 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
717 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
718 use_staging_texture = TRUE;
719 }
720
721 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
722 use_staging_texture = FALSE;
723 }
724
725 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
726 return NULL;
727 }
728
729 trans = CALLOC_STRUCT(r600_transfer);
730 if (trans == NULL)
731 return NULL;
732 trans->transfer.resource = texture;
733 trans->transfer.level = level;
734 trans->transfer.usage = usage;
735 trans->transfer.box = *box;
736 if (rtex->is_depth) {
737 /* XXX: only readback the rectangle which is being mapped?
738 */
739 /* XXX: when discard is true, no need to read back from depth texture
740 */
741 struct r600_texture *staging_depth;
742
743 assert(rtex->resource.b.b.nr_samples <= 1);
744 if (rtex->resource.b.b.nr_samples > 1) {
745 R600_ERR("mapping MSAA zbuffer unimplemented\n");
746 FREE(trans);
747 return NULL;
748 }
749
750 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
751 R600_ERR("failed to create temporary texture to hold untiled copy\n");
752 FREE(trans);
753 return NULL;
754 }
755
756 r600_blit_decompress_depth(ctx, rtex, staging_depth,
757 level, level,
758 box->z, box->z + box->depth - 1,
759 0, 0);
760
761 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
762 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
763 trans->staging = (struct r600_resource*)staging_depth;
764 } else if (use_staging_texture) {
765 resource.target = PIPE_TEXTURE_2D;
766 resource.format = texture->format;
767 resource.width0 = box->width;
768 resource.height0 = box->height;
769 resource.depth0 = 1;
770 resource.array_size = 1;
771 resource.last_level = 0;
772 resource.nr_samples = 0;
773 resource.usage = PIPE_USAGE_STAGING;
774 resource.bind = 0;
775 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
776 /* For texture reading, the temporary (detiled) texture is used as
777 * a render target when blitting from a tiled texture. */
778 if (usage & PIPE_TRANSFER_READ) {
779 resource.bind |= PIPE_BIND_RENDER_TARGET;
780 }
781 /* For texture writing, the temporary texture is used as a sampler
782 * when blitting into a tiled texture. */
783 if (usage & PIPE_TRANSFER_WRITE) {
784 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
785 }
786 /* Create the temporary texture. */
787 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
788 if (trans->staging == NULL) {
789 R600_ERR("failed to create temporary texture to hold untiled copy\n");
790 FREE(trans);
791 return NULL;
792 }
793
794 trans->transfer.stride =
795 ((struct r600_texture *)trans->staging)->surface.level[0].pitch_bytes;
796 if (usage & PIPE_TRANSFER_READ) {
797 r600_copy_to_staging_texture(ctx, trans);
798 /* Always referenced in the blit. */
799 r600_flush(ctx, NULL, 0);
800 }
801 } else {
802 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
803 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
804 trans->offset = r600_texture_get_offset(rtex, level, box->z);
805 }
806
807 if (trans->staging) {
808 buf = ((struct r600_resource *)trans->staging)->cs_buf;
809 } else {
810 buf = ((struct r600_resource *)texture)->cs_buf;
811 }
812
813 if (rtex->is_depth || !trans->staging)
814 offset = trans->offset +
815 box->y / util_format_get_blockheight(format) * trans->transfer.stride +
816 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
817
818 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) {
819 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
820 FREE(trans);
821 return NULL;
822 }
823
824 *ptransfer = &trans->transfer;
825 return map + offset;
826 }
827
828 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
829 struct pipe_transfer* transfer)
830 {
831 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
832 struct r600_context *rctx = (struct r600_context*)ctx;
833 struct radeon_winsys_cs_handle *buf;
834 struct pipe_resource *texture = transfer->resource;
835 struct r600_texture *rtex = (struct r600_texture*)texture;
836
837 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
838 return r600_compute_global_transfer_unmap(ctx, transfer);
839 }
840
841 if (rtransfer->staging) {
842 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
843 } else {
844 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
845 }
846 rctx->ws->buffer_unmap(buf);
847
848 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
849 if (rtex->is_depth) {
850 ctx->resource_copy_region(ctx, texture, transfer->level,
851 transfer->box.x, transfer->box.y, transfer->box.z,
852 &rtransfer->staging->b.b, transfer->level,
853 &transfer->box);
854 } else {
855 r600_copy_from_staging_texture(ctx, rtransfer);
856 }
857 }
858
859 if (rtransfer->staging)
860 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
861
862 FREE(transfer);
863 }
864
865 void r600_init_surface_functions(struct r600_context *r600)
866 {
867 r600->context.create_surface = r600_create_surface;
868 r600->context.surface_destroy = r600_surface_destroy;
869 }
870
871 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
872 const unsigned char *swizzle_view)
873 {
874 unsigned i;
875 unsigned char swizzle[4];
876 unsigned result = 0;
877 const uint32_t swizzle_shift[4] = {
878 16, 19, 22, 25,
879 };
880 const uint32_t swizzle_bit[4] = {
881 0, 1, 2, 3,
882 };
883
884 if (swizzle_view) {
885 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
886 } else {
887 memcpy(swizzle, swizzle_format, 4);
888 }
889
890 /* Get swizzle. */
891 for (i = 0; i < 4; i++) {
892 switch (swizzle[i]) {
893 case UTIL_FORMAT_SWIZZLE_Y:
894 result |= swizzle_bit[1] << swizzle_shift[i];
895 break;
896 case UTIL_FORMAT_SWIZZLE_Z:
897 result |= swizzle_bit[2] << swizzle_shift[i];
898 break;
899 case UTIL_FORMAT_SWIZZLE_W:
900 result |= swizzle_bit[3] << swizzle_shift[i];
901 break;
902 case UTIL_FORMAT_SWIZZLE_0:
903 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
904 break;
905 case UTIL_FORMAT_SWIZZLE_1:
906 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
907 break;
908 default: /* UTIL_FORMAT_SWIZZLE_X */
909 result |= swizzle_bit[0] << swizzle_shift[i];
910 }
911 }
912 return result;
913 }
914
915 /* texture format translate */
916 uint32_t r600_translate_texformat(struct pipe_screen *screen,
917 enum pipe_format format,
918 const unsigned char *swizzle_view,
919 uint32_t *word4_p, uint32_t *yuv_format_p)
920 {
921 uint32_t result = 0, word4 = 0, yuv_format = 0;
922 const struct util_format_description *desc;
923 boolean uniform = TRUE;
924 static int r600_enable_s3tc = -1;
925 bool is_srgb_valid = FALSE;
926
927 int i;
928 const uint32_t sign_bit[4] = {
929 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
930 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
931 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
932 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
933 };
934 desc = util_format_description(format);
935
936 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
937
938 /* Colorspace (return non-RGB formats directly). */
939 switch (desc->colorspace) {
940 /* Depth stencil formats */
941 case UTIL_FORMAT_COLORSPACE_ZS:
942 switch (format) {
943 case PIPE_FORMAT_Z16_UNORM:
944 result = FMT_16;
945 goto out_word4;
946 case PIPE_FORMAT_X24S8_UINT:
947 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
948 case PIPE_FORMAT_Z24X8_UNORM:
949 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
950 result = FMT_8_24;
951 goto out_word4;
952 case PIPE_FORMAT_S8X24_UINT:
953 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
954 case PIPE_FORMAT_X8Z24_UNORM:
955 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
956 result = FMT_24_8;
957 goto out_word4;
958 case PIPE_FORMAT_S8_UINT:
959 result = FMT_8;
960 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
961 goto out_word4;
962 case PIPE_FORMAT_Z32_FLOAT:
963 result = FMT_32_FLOAT;
964 goto out_word4;
965 case PIPE_FORMAT_X32_S8X24_UINT:
966 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
967 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
968 result = FMT_X24_8_32_FLOAT;
969 goto out_word4;
970 default:
971 goto out_unknown;
972 }
973
974 case UTIL_FORMAT_COLORSPACE_YUV:
975 yuv_format |= (1 << 30);
976 switch (format) {
977 case PIPE_FORMAT_UYVY:
978 case PIPE_FORMAT_YUYV:
979 default:
980 break;
981 }
982 goto out_unknown; /* XXX */
983
984 case UTIL_FORMAT_COLORSPACE_SRGB:
985 word4 |= S_038010_FORCE_DEGAMMA(1);
986 break;
987
988 default:
989 break;
990 }
991
992 if (r600_enable_s3tc == -1) {
993 struct r600_screen *rscreen = (struct r600_screen *)screen;
994 if (rscreen->info.drm_minor >= 9)
995 r600_enable_s3tc = 1;
996 else
997 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
998 }
999
1000 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1001 if (!r600_enable_s3tc)
1002 goto out_unknown;
1003
1004 switch (format) {
1005 case PIPE_FORMAT_RGTC1_SNORM:
1006 case PIPE_FORMAT_LATC1_SNORM:
1007 word4 |= sign_bit[0];
1008 case PIPE_FORMAT_RGTC1_UNORM:
1009 case PIPE_FORMAT_LATC1_UNORM:
1010 result = FMT_BC4;
1011 goto out_word4;
1012 case PIPE_FORMAT_RGTC2_SNORM:
1013 case PIPE_FORMAT_LATC2_SNORM:
1014 word4 |= sign_bit[0] | sign_bit[1];
1015 case PIPE_FORMAT_RGTC2_UNORM:
1016 case PIPE_FORMAT_LATC2_UNORM:
1017 result = FMT_BC5;
1018 goto out_word4;
1019 default:
1020 goto out_unknown;
1021 }
1022 }
1023
1024 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1025
1026 if (!r600_enable_s3tc)
1027 goto out_unknown;
1028
1029 if (!util_format_s3tc_enabled) {
1030 goto out_unknown;
1031 }
1032
1033 switch (format) {
1034 case PIPE_FORMAT_DXT1_RGB:
1035 case PIPE_FORMAT_DXT1_RGBA:
1036 case PIPE_FORMAT_DXT1_SRGB:
1037 case PIPE_FORMAT_DXT1_SRGBA:
1038 result = FMT_BC1;
1039 is_srgb_valid = TRUE;
1040 goto out_word4;
1041 case PIPE_FORMAT_DXT3_RGBA:
1042 case PIPE_FORMAT_DXT3_SRGBA:
1043 result = FMT_BC2;
1044 is_srgb_valid = TRUE;
1045 goto out_word4;
1046 case PIPE_FORMAT_DXT5_RGBA:
1047 case PIPE_FORMAT_DXT5_SRGBA:
1048 result = FMT_BC3;
1049 is_srgb_valid = TRUE;
1050 goto out_word4;
1051 default:
1052 goto out_unknown;
1053 }
1054 }
1055
1056 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1057 switch (format) {
1058 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1059 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1060 result = FMT_GB_GR;
1061 goto out_word4;
1062 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1063 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1064 result = FMT_BG_RG;
1065 goto out_word4;
1066 default:
1067 goto out_unknown;
1068 }
1069 }
1070
1071 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1072 result = FMT_5_9_9_9_SHAREDEXP;
1073 goto out_word4;
1074 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1075 result = FMT_10_11_11_FLOAT;
1076 goto out_word4;
1077 }
1078
1079
1080 for (i = 0; i < desc->nr_channels; i++) {
1081 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1082 word4 |= sign_bit[i];
1083 }
1084 }
1085
1086 /* R8G8Bx_SNORM - XXX CxV8U8 */
1087
1088 /* See whether the components are of the same size. */
1089 for (i = 1; i < desc->nr_channels; i++) {
1090 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1091 }
1092
1093 /* Non-uniform formats. */
1094 if (!uniform) {
1095 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1096 desc->channel[0].pure_integer)
1097 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1098 switch(desc->nr_channels) {
1099 case 3:
1100 if (desc->channel[0].size == 5 &&
1101 desc->channel[1].size == 6 &&
1102 desc->channel[2].size == 5) {
1103 result = FMT_5_6_5;
1104 goto out_word4;
1105 }
1106 goto out_unknown;
1107 case 4:
1108 if (desc->channel[0].size == 5 &&
1109 desc->channel[1].size == 5 &&
1110 desc->channel[2].size == 5 &&
1111 desc->channel[3].size == 1) {
1112 result = FMT_1_5_5_5;
1113 goto out_word4;
1114 }
1115 if (desc->channel[0].size == 10 &&
1116 desc->channel[1].size == 10 &&
1117 desc->channel[2].size == 10 &&
1118 desc->channel[3].size == 2) {
1119 result = FMT_2_10_10_10;
1120 goto out_word4;
1121 }
1122 goto out_unknown;
1123 }
1124 goto out_unknown;
1125 }
1126
1127 /* Find the first non-VOID channel. */
1128 for (i = 0; i < 4; i++) {
1129 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1130 break;
1131 }
1132 }
1133
1134 if (i == 4)
1135 goto out_unknown;
1136
1137 /* uniform formats */
1138 switch (desc->channel[i].type) {
1139 case UTIL_FORMAT_TYPE_UNSIGNED:
1140 case UTIL_FORMAT_TYPE_SIGNED:
1141 #if 0
1142 if (!desc->channel[i].normalized &&
1143 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1144 goto out_unknown;
1145 }
1146 #endif
1147 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1148 desc->channel[i].pure_integer)
1149 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1150
1151 switch (desc->channel[i].size) {
1152 case 4:
1153 switch (desc->nr_channels) {
1154 case 2:
1155 result = FMT_4_4;
1156 goto out_word4;
1157 case 4:
1158 result = FMT_4_4_4_4;
1159 goto out_word4;
1160 }
1161 goto out_unknown;
1162 case 8:
1163 switch (desc->nr_channels) {
1164 case 1:
1165 result = FMT_8;
1166 goto out_word4;
1167 case 2:
1168 result = FMT_8_8;
1169 goto out_word4;
1170 case 4:
1171 result = FMT_8_8_8_8;
1172 is_srgb_valid = TRUE;
1173 goto out_word4;
1174 }
1175 goto out_unknown;
1176 case 16:
1177 switch (desc->nr_channels) {
1178 case 1:
1179 result = FMT_16;
1180 goto out_word4;
1181 case 2:
1182 result = FMT_16_16;
1183 goto out_word4;
1184 case 4:
1185 result = FMT_16_16_16_16;
1186 goto out_word4;
1187 }
1188 goto out_unknown;
1189 case 32:
1190 switch (desc->nr_channels) {
1191 case 1:
1192 result = FMT_32;
1193 goto out_word4;
1194 case 2:
1195 result = FMT_32_32;
1196 goto out_word4;
1197 case 4:
1198 result = FMT_32_32_32_32;
1199 goto out_word4;
1200 }
1201 }
1202 goto out_unknown;
1203
1204 case UTIL_FORMAT_TYPE_FLOAT:
1205 switch (desc->channel[i].size) {
1206 case 16:
1207 switch (desc->nr_channels) {
1208 case 1:
1209 result = FMT_16_FLOAT;
1210 goto out_word4;
1211 case 2:
1212 result = FMT_16_16_FLOAT;
1213 goto out_word4;
1214 case 4:
1215 result = FMT_16_16_16_16_FLOAT;
1216 goto out_word4;
1217 }
1218 goto out_unknown;
1219 case 32:
1220 switch (desc->nr_channels) {
1221 case 1:
1222 result = FMT_32_FLOAT;
1223 goto out_word4;
1224 case 2:
1225 result = FMT_32_32_FLOAT;
1226 goto out_word4;
1227 case 4:
1228 result = FMT_32_32_32_32_FLOAT;
1229 goto out_word4;
1230 }
1231 }
1232 goto out_unknown;
1233 }
1234
1235 out_word4:
1236
1237 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1238 return ~0;
1239 if (word4_p)
1240 *word4_p = word4;
1241 if (yuv_format_p)
1242 *yuv_format_p = yuv_format;
1243 return result;
1244 out_unknown:
1245 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1246 return ~0;
1247 }
1248
1249 static const struct u_resource_vtbl r600_texture_vtbl =
1250 {
1251 r600_texture_get_handle, /* get_handle */
1252 r600_texture_destroy, /* resource_destroy */
1253 r600_texture_transfer_map, /* transfer_map */
1254 NULL, /* transfer_flush_region */
1255 r600_texture_transfer_unmap, /* transfer_unmap */
1256 NULL /* transfer_inline_write */
1257 };