2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_formats.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
34 /* Copy from a full GPU texture to a transfer's staging one. */
35 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
37 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
38 struct pipe_resource
*texture
= transfer
->resource
;
40 ctx
->resource_copy_region(ctx
, &rtransfer
->staging
->b
.b
,
41 0, 0, 0, 0, texture
, transfer
->level
,
46 /* Copy from a transfer's staging texture to a full GPU one. */
47 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
49 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
50 struct pipe_resource
*texture
= transfer
->resource
;
53 u_box_origin_2d(transfer
->box
.width
, transfer
->box
.height
, &sbox
);
55 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
56 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
57 &rtransfer
->staging
->b
.b
,
61 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
62 unsigned level
, unsigned layer
)
64 unsigned offset
= rtex
->offset
[level
];
66 switch (rtex
->resource
.b
.b
.target
) {
68 case PIPE_TEXTURE_CUBE
:
70 return offset
+ layer
* rtex
->layer_size
[level
];
74 static unsigned r600_get_block_alignment(struct pipe_screen
*screen
,
75 enum pipe_format format
,
78 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
79 unsigned pixsize
= util_format_get_blocksize(format
);
83 case V_038000_ARRAY_1D_TILED_THIN1
:
85 ((rscreen
->tiling_info
.group_bytes
/ 8 / pixsize
)));
87 case V_038000_ARRAY_2D_TILED_THIN1
:
88 p_align
= MAX2(rscreen
->tiling_info
.num_banks
,
89 (((rscreen
->tiling_info
.group_bytes
/ 8 / pixsize
)) *
90 rscreen
->tiling_info
.num_banks
)) * 8;
92 case V_038000_ARRAY_LINEAR_ALIGNED
:
93 p_align
= MAX2(64, rscreen
->tiling_info
.group_bytes
/ pixsize
);
95 case V_038000_ARRAY_LINEAR_GENERAL
:
97 p_align
= rscreen
->tiling_info
.group_bytes
/ pixsize
;
103 static unsigned r600_get_height_alignment(struct pipe_screen
*screen
,
106 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
109 switch (array_mode
) {
110 case V_038000_ARRAY_2D_TILED_THIN1
:
111 h_align
= rscreen
->tiling_info
.num_channels
* 8;
113 case V_038000_ARRAY_1D_TILED_THIN1
:
114 case V_038000_ARRAY_LINEAR_ALIGNED
:
117 case V_038000_ARRAY_LINEAR_GENERAL
:
125 static unsigned r600_get_base_alignment(struct pipe_screen
*screen
,
126 enum pipe_format format
,
129 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
130 unsigned pixsize
= util_format_get_blocksize(format
);
131 int p_align
= r600_get_block_alignment(screen
, format
, array_mode
);
132 int h_align
= r600_get_height_alignment(screen
, array_mode
);
135 switch (array_mode
) {
136 case V_038000_ARRAY_2D_TILED_THIN1
:
137 b_align
= MAX2(rscreen
->tiling_info
.num_banks
* rscreen
->tiling_info
.num_channels
* 8 * 8 * pixsize
,
138 p_align
* pixsize
* h_align
);
140 case V_038000_ARRAY_1D_TILED_THIN1
:
141 case V_038000_ARRAY_LINEAR_ALIGNED
:
142 case V_038000_ARRAY_LINEAR_GENERAL
:
144 b_align
= rscreen
->tiling_info
.group_bytes
;
150 static unsigned mip_minify(unsigned size
, unsigned level
)
153 val
= u_minify(size
, level
);
155 val
= util_next_power_of_two(val
);
159 static unsigned r600_texture_get_nblocksx(struct pipe_screen
*screen
,
160 struct r600_resource_texture
*rtex
,
163 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
164 unsigned nblocksx
, block_align
, width
;
165 unsigned blocksize
= util_format_get_blocksize(rtex
->real_format
);
167 if (rtex
->pitch_override
)
168 return rtex
->pitch_override
/ blocksize
;
170 width
= mip_minify(ptex
->width0
, level
);
171 nblocksx
= util_format_get_nblocksx(rtex
->real_format
, width
);
173 block_align
= r600_get_block_alignment(screen
, rtex
->real_format
,
174 rtex
->array_mode
[level
]);
175 nblocksx
= align(nblocksx
, block_align
);
179 static unsigned r600_texture_get_nblocksy(struct pipe_screen
*screen
,
180 struct r600_resource_texture
*rtex
,
183 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
184 unsigned height
, tile_height
;
186 height
= mip_minify(ptex
->height0
, level
);
187 height
= util_format_get_nblocksy(rtex
->real_format
, height
);
188 tile_height
= r600_get_height_alignment(screen
,
189 rtex
->array_mode
[level
]);
191 /* XXX Hack around an alignment issue. Less tests fail with this.
193 * The thing is depth-stencil buffers should be tiled, i.e.
194 * the alignment should be >=8. If I make them tiled, stencil starts
195 * working because it no longer overlaps with the depth buffer
196 * in memory, but texturing like drawpix-stencil breaks. */
197 if (util_format_is_depth_or_stencil(rtex
->real_format
) && tile_height
< 8)
200 height
= align(height
, tile_height
);
204 static void r600_texture_set_array_mode(struct pipe_screen
*screen
,
205 struct r600_resource_texture
*rtex
,
206 unsigned level
, unsigned array_mode
)
208 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
210 switch (array_mode
) {
211 case V_0280A0_ARRAY_LINEAR_GENERAL
:
212 case V_0280A0_ARRAY_LINEAR_ALIGNED
:
213 case V_0280A0_ARRAY_1D_TILED_THIN1
:
215 rtex
->array_mode
[level
] = array_mode
;
217 case V_0280A0_ARRAY_2D_TILED_THIN1
:
219 unsigned w
, h
, tile_height
, tile_width
;
221 tile_height
= r600_get_height_alignment(screen
, array_mode
);
222 tile_width
= r600_get_block_alignment(screen
, rtex
->real_format
, array_mode
);
224 w
= mip_minify(ptex
->width0
, level
);
225 h
= mip_minify(ptex
->height0
, level
);
226 if (w
<= tile_width
|| h
<= tile_height
)
227 rtex
->array_mode
[level
] = V_0280A0_ARRAY_1D_TILED_THIN1
;
229 rtex
->array_mode
[level
] = array_mode
;
235 static int r600_init_surface(struct radeon_surface
*surface
,
236 const struct pipe_resource
*ptex
,
237 unsigned array_mode
, bool is_transfer
)
239 surface
->npix_x
= ptex
->width0
;
240 surface
->npix_y
= ptex
->height0
;
241 surface
->npix_z
= ptex
->depth0
;
242 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
243 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
245 surface
->array_size
= 1;
246 surface
->last_level
= ptex
->last_level
;
247 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
248 /* align byte per element on dword */
249 if (surface
->bpe
== 3) {
252 surface
->nsamples
= 1;
254 switch (array_mode
) {
255 case V_038000_ARRAY_1D_TILED_THIN1
:
256 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
258 case V_038000_ARRAY_2D_TILED_THIN1
:
259 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
261 case V_038000_ARRAY_LINEAR_ALIGNED
:
262 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
264 case V_038000_ARRAY_LINEAR_GENERAL
:
266 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR
, MODE
);
269 switch (ptex
->target
) {
270 case PIPE_TEXTURE_1D
:
271 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
273 case PIPE_TEXTURE_RECT
:
274 case PIPE_TEXTURE_2D
:
275 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
277 case PIPE_TEXTURE_3D
:
278 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
280 case PIPE_TEXTURE_1D_ARRAY
:
281 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
282 surface
->array_size
= ptex
->array_size
;
284 case PIPE_TEXTURE_2D_ARRAY
:
285 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
286 surface
->array_size
= ptex
->array_size
;
288 case PIPE_TEXTURE_CUBE
:
289 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
295 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
296 surface
->flags
|= RADEON_SURF_SCANOUT
;
298 if ((ptex
->bind
& PIPE_BIND_DEPTH_STENCIL
) &&
299 util_format_is_depth_and_stencil(ptex
->format
) && !is_transfer
) {
300 surface
->flags
|= RADEON_SURF_ZBUFFER
;
301 surface
->flags
|= RADEON_SURF_SBUFFER
;
307 static int r600_setup_surface(struct pipe_screen
*screen
,
308 struct r600_resource_texture
*rtex
,
310 unsigned pitch_in_bytes_override
)
312 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
313 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
317 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
321 rtex
->size
= rtex
->surface
.bo_size
;
322 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
323 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
326 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
327 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
328 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
329 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
330 rtex
->surface
.stencil_offset
= rtex
->surface
.level
[0].slice_size
;
333 for (i
= 0; i
<= ptex
->last_level
; i
++) {
334 rtex
->offset
[i
] = rtex
->surface
.level
[i
].offset
;
335 rtex
->layer_size
[i
] = rtex
->surface
.level
[i
].slice_size
;
336 rtex
->pitch_in_bytes
[i
] = rtex
->surface
.level
[i
].pitch_bytes
;
337 switch (rtex
->surface
.level
[i
].mode
) {
338 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
339 rtex
->array_mode
[i
] = V_038000_ARRAY_LINEAR_ALIGNED
;
341 case RADEON_SURF_MODE_1D
:
342 rtex
->array_mode
[i
] = V_038000_ARRAY_1D_TILED_THIN1
;
344 case RADEON_SURF_MODE_2D
:
345 rtex
->array_mode
[i
] = V_038000_ARRAY_2D_TILED_THIN1
;
348 case RADEON_SURF_MODE_LINEAR
:
349 rtex
->array_mode
[i
] = 0;
356 static void r600_setup_miptree(struct pipe_screen
*screen
,
357 struct r600_resource_texture
*rtex
,
360 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
361 enum chip_class chipc
= ((struct r600_screen
*)screen
)->chip_class
;
362 unsigned size
, layer_size
, i
, offset
;
363 unsigned nblocksx
, nblocksy
;
365 for (i
= 0, offset
= 0; i
<= ptex
->last_level
; i
++) {
366 unsigned blocksize
= util_format_get_blocksize(rtex
->real_format
);
367 unsigned base_align
= r600_get_base_alignment(screen
, rtex
->real_format
, array_mode
);
369 r600_texture_set_array_mode(screen
, rtex
, i
, array_mode
);
371 nblocksx
= r600_texture_get_nblocksx(screen
, rtex
, i
);
372 nblocksy
= r600_texture_get_nblocksy(screen
, rtex
, i
);
374 if (chipc
>= EVERGREEN
&& array_mode
== V_038000_ARRAY_LINEAR_GENERAL
)
375 layer_size
= align(nblocksx
, 64) * nblocksy
* blocksize
;
377 layer_size
= nblocksx
* nblocksy
* blocksize
;
379 if (ptex
->target
== PIPE_TEXTURE_CUBE
) {
381 size
= layer_size
* 8;
383 size
= layer_size
* 6;
385 else if (ptex
->target
== PIPE_TEXTURE_3D
)
386 size
= layer_size
* u_minify(ptex
->depth0
, i
);
388 size
= layer_size
* ptex
->array_size
;
390 /* align base image and start of miptree */
391 if ((i
== 0) || (i
== 1))
392 offset
= align(offset
, base_align
);
393 rtex
->offset
[i
] = offset
;
394 rtex
->layer_size
[i
] = layer_size
;
395 rtex
->pitch_in_blocks
[i
] = nblocksx
; /* CB talks in elements */
396 rtex
->pitch_in_bytes
[i
] = nblocksx
* blocksize
;
403 /* Figure out whether u_blitter will fallback to a transfer operation.
404 * If so, don't use a staging resource.
406 static boolean
permit_hardware_blit(struct pipe_screen
*screen
,
407 const struct pipe_resource
*res
)
411 if (util_format_is_depth_or_stencil(res
->format
))
412 bind
= PIPE_BIND_DEPTH_STENCIL
;
414 bind
= PIPE_BIND_RENDER_TARGET
;
416 /* hackaround for S3TC */
417 if (util_format_is_compressed(res
->format
))
420 if (!screen
->is_format_supported(screen
,
427 if (!screen
->is_format_supported(screen
,
431 PIPE_BIND_SAMPLER_VIEW
))
437 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
438 struct pipe_resource
*ptex
,
439 struct winsys_handle
*whandle
)
441 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
442 struct r600_resource
*resource
= &rtex
->resource
;
443 struct radeon_surface
*surface
= &rtex
->surface
;
444 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
446 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
448 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
449 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
450 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
451 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
452 surface
->bankw
, surface
->bankh
,
454 surface
->stencil_tile_split
,
456 rtex
->pitch_in_bytes
[0]);
458 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
459 rtex
->pitch_in_bytes
[0], whandle
);
462 static void r600_texture_destroy(struct pipe_screen
*screen
,
463 struct pipe_resource
*ptex
)
465 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)ptex
;
466 struct r600_resource
*resource
= &rtex
->resource
;
468 if (rtex
->flushed_depth_texture
)
469 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
472 pipe_resource_reference((struct pipe_resource
**)&rtex
->stencil
, NULL
);
474 pb_reference(&resource
->buf
, NULL
);
478 static const struct u_resource_vtbl r600_texture_vtbl
=
480 r600_texture_get_handle
, /* get_handle */
481 r600_texture_destroy
, /* resource_destroy */
482 r600_texture_get_transfer
, /* get_transfer */
483 r600_texture_transfer_destroy
, /* transfer_destroy */
484 r600_texture_transfer_map
, /* transfer_map */
485 NULL
, /* transfer_flush_region */
486 r600_texture_transfer_unmap
, /* transfer_unmap */
487 NULL
/* transfer_inline_write */
490 static struct r600_resource_texture
*
491 r600_texture_create_object(struct pipe_screen
*screen
,
492 const struct pipe_resource
*base
,
494 unsigned pitch_in_bytes_override
,
495 unsigned max_buffer_size
,
496 struct pb_buffer
*buf
,
498 struct radeon_surface
*surface
)
500 struct r600_resource_texture
*rtex
;
501 struct r600_resource
*resource
;
502 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
505 rtex
= CALLOC_STRUCT(r600_resource_texture
);
509 resource
= &rtex
->resource
;
510 resource
->b
.b
= *base
;
511 resource
->b
.vtbl
= &r600_texture_vtbl
;
512 pipe_reference_init(&resource
->b
.b
.reference
, 1);
513 resource
->b
.b
.screen
= screen
;
514 rtex
->pitch_override
= pitch_in_bytes_override
;
515 rtex
->real_format
= base
->format
;
517 /* We must split depth and stencil into two separate buffers on Evergreen. */
518 if ((base
->bind
& PIPE_BIND_DEPTH_STENCIL
) &&
519 ((struct r600_screen
*)screen
)->chip_class
>= EVERGREEN
&&
520 util_format_is_depth_and_stencil(base
->format
) &&
521 !rscreen
->use_surface_alloc
) {
522 struct pipe_resource stencil
;
523 unsigned stencil_pitch_override
= 0;
525 switch (base
->format
) {
526 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
527 rtex
->real_format
= PIPE_FORMAT_Z24X8_UNORM
;
529 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
530 rtex
->real_format
= PIPE_FORMAT_X8Z24_UNORM
;
532 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
533 rtex
->real_format
= PIPE_FORMAT_Z32_FLOAT
;
541 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
542 if (pitch_in_bytes_override
) {
543 assert(base
->format
== PIPE_FORMAT_Z24_UNORM_S8_UINT
||
544 base
->format
== PIPE_FORMAT_S8_UINT_Z24_UNORM
);
545 stencil_pitch_override
= pitch_in_bytes_override
/ 4;
548 /* Allocate the stencil buffer. */
550 stencil
.format
= PIPE_FORMAT_S8_UINT
;
551 rtex
->stencil
= r600_texture_create_object(screen
, &stencil
, array_mode
,
552 stencil_pitch_override
,
553 max_buffer_size
, NULL
, FALSE
, surface
);
554 if (!rtex
->stencil
) {
558 /* Proceed in creating the depth buffer. */
561 /* only mark depth textures the HW can hit as depth textures */
562 if (util_format_is_depth_or_stencil(rtex
->real_format
) &&
563 permit_hardware_blit(screen
, base
))
564 rtex
->is_depth
= true;
566 r600_setup_miptree(screen
, rtex
, array_mode
);
567 if (rscreen
->use_surface_alloc
) {
568 rtex
->surface
= *surface
;
569 r
= r600_setup_surface(screen
, rtex
, array_mode
,
570 pitch_in_bytes_override
);
577 /* If we initialized separate stencil for Evergreen. place it after depth. */
579 unsigned stencil_align
, stencil_offset
;
581 stencil_align
= r600_get_base_alignment(screen
, rtex
->stencil
->real_format
, array_mode
);
582 stencil_offset
= align(rtex
->size
, stencil_align
);
584 for (unsigned i
= 0; i
<= rtex
->stencil
->resource
.b
.b
.last_level
; i
++)
585 rtex
->stencil
->offset
[i
] += stencil_offset
;
587 rtex
->size
= stencil_offset
+ rtex
->stencil
->size
;
590 /* Now create the backing buffer. */
591 if (!buf
&& alloc_bo
) {
592 struct pipe_resource
*ptex
= &rtex
->resource
.b
.b
;
593 unsigned base_align
= r600_get_base_alignment(screen
, ptex
->format
, array_mode
);
595 if (rscreen
->use_surface_alloc
) {
596 base_align
= rtex
->surface
.bo_alignment
;
597 } else if (util_format_is_depth_or_stencil(rtex
->real_format
)) {
598 /* ugly work around depth buffer need stencil room at end of bo */
599 rtex
->size
+= ptex
->width0
* ptex
->height0
;
601 if (!r600_init_resource(rscreen
, resource
, rtex
->size
, base_align
, base
->bind
, base
->usage
)) {
602 pipe_resource_reference((struct pipe_resource
**)&rtex
->stencil
, NULL
);
608 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
609 resource
->domains
= RADEON_DOMAIN_GTT
| RADEON_DOMAIN_VRAM
;
613 pb_reference(&rtex
->stencil
->resource
.buf
, rtex
->resource
.buf
);
614 rtex
->stencil
->resource
.cs_buf
= rtex
->resource
.cs_buf
;
615 rtex
->stencil
->resource
.domains
= rtex
->resource
.domains
;
620 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
621 const struct pipe_resource
*templ
)
623 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
624 struct radeon_surface surface
;
625 unsigned array_mode
= 0;
628 if (!(templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)) {
629 if (rscreen
->use_surface_alloc
&&
630 !(templ
->bind
& PIPE_BIND_SCANOUT
) &&
631 templ
->usage
!= PIPE_USAGE_STAGING
&&
632 templ
->usage
!= PIPE_USAGE_STREAM
&&
633 permit_hardware_blit(screen
, templ
)) {
634 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
635 } else if (util_format_is_compressed(templ
->format
)) {
636 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
640 r
= r600_init_surface(&surface
, templ
, array_mode
,
641 templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
);
645 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
649 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
650 0, 0, NULL
, TRUE
, &surface
);
653 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
654 struct pipe_resource
*texture
,
655 const struct pipe_surface
*surf_tmpl
)
657 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
658 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
659 unsigned level
= surf_tmpl
->u
.tex
.level
;
661 assert(surf_tmpl
->u
.tex
.first_layer
== surf_tmpl
->u
.tex
.last_layer
);
664 pipe_reference_init(&surface
->base
.reference
, 1);
665 pipe_resource_reference(&surface
->base
.texture
, texture
);
666 surface
->base
.context
= pipe
;
667 surface
->base
.format
= surf_tmpl
->format
;
668 surface
->base
.width
= mip_minify(texture
->width0
, level
);
669 surface
->base
.height
= mip_minify(texture
->height0
, level
);
670 surface
->base
.usage
= surf_tmpl
->usage
;
671 surface
->base
.texture
= texture
;
672 surface
->base
.u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
673 surface
->base
.u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
674 surface
->base
.u
.tex
.level
= level
;
676 surface
->aligned_height
= r600_texture_get_nblocksy(pipe
->screen
,
678 return &surface
->base
;
681 static void r600_surface_destroy(struct pipe_context
*pipe
,
682 struct pipe_surface
*surface
)
684 pipe_resource_reference(&surface
->texture
, NULL
);
688 struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
689 const struct pipe_resource
*templ
,
690 struct winsys_handle
*whandle
)
692 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
693 struct pb_buffer
*buf
= NULL
;
695 unsigned array_mode
= 0;
696 enum radeon_bo_layout micro
, macro
;
697 struct radeon_surface surface
;
700 /* Support only 2D textures without mipmaps */
701 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
702 templ
->depth0
!= 1 || templ
->last_level
!= 0)
705 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
709 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
710 &surface
.bankw
, &surface
.bankh
,
712 &surface
.stencil_tile_split
,
715 if (macro
== RADEON_LAYOUT_TILED
)
716 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
717 else if (micro
== RADEON_LAYOUT_TILED
)
718 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
722 r
= r600_init_surface(&surface
, templ
, array_mode
, 0);
726 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, array_mode
,
727 stride
, 0, buf
, FALSE
, &surface
);
730 void r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
731 struct pipe_resource
*texture
,
732 struct r600_resource_texture
**staging
)
734 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
735 struct pipe_resource resource
;
736 struct r600_resource_texture
**flushed_depth_texture
= staging
?
737 staging
: &rtex
->flushed_depth_texture
;
739 if (!staging
&& rtex
->flushed_depth_texture
)
740 return; /* it's ready */
742 resource
.target
= texture
->target
;
743 resource
.format
= texture
->format
;
744 resource
.width0
= texture
->width0
;
745 resource
.height0
= texture
->height0
;
746 resource
.depth0
= texture
->depth0
;
747 resource
.array_size
= texture
->array_size
;
748 resource
.last_level
= texture
->last_level
;
749 resource
.nr_samples
= texture
->nr_samples
;
750 resource
.usage
= staging
? PIPE_USAGE_DYNAMIC
: PIPE_USAGE_DEFAULT
;
751 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
752 resource
.flags
= texture
->flags
;
755 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
757 *flushed_depth_texture
= (struct r600_resource_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
758 if (*flushed_depth_texture
== NULL
) {
759 R600_ERR("failed to create temporary texture to hold flushed depth\n");
763 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
767 void r600_texture_depth_flush(struct pipe_context
*ctx
,
768 struct pipe_resource
*texture
,
769 struct r600_resource_texture
**staging
,
770 unsigned first_level
, unsigned last_level
,
771 unsigned first_layer
, unsigned last_layer
)
773 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
775 r600_init_flushed_depth_texture(ctx
, texture
, staging
);
781 r600_blit_uncompress_depth(ctx
, rtex
, *staging
,
782 first_level
, last_level
,
783 first_layer
, last_layer
);
785 if (!rtex
->flushed_depth_texture
)
788 r600_blit_uncompress_depth(ctx
, rtex
, NULL
,
789 first_level
, last_level
,
790 first_layer
, last_layer
);
794 /* Needs adjustment for pixelformat:
796 static INLINE
unsigned u_box_volume( const struct pipe_box
*box
)
798 return box
->width
* box
->depth
* box
->height
;
801 struct pipe_transfer
* r600_texture_get_transfer(struct pipe_context
*ctx
,
802 struct pipe_resource
*texture
,
805 const struct pipe_box
*box
)
807 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
808 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
809 struct pipe_resource resource
;
810 struct r600_transfer
*trans
;
811 boolean use_staging_texture
= FALSE
;
813 /* We cannot map a tiled texture directly because the data is
814 * in a different order, therefore we do detiling using a blit.
816 * Also, use a temporary in GTT memory for read transfers, as
817 * the CPU is much happier reading out of cached system memory
818 * than uncached VRAM.
820 if (R600_TEX_IS_TILED(rtex
, level
)) {
821 use_staging_texture
= TRUE
;
824 if ((usage
& PIPE_TRANSFER_READ
) && u_box_volume(box
) > 1024)
825 use_staging_texture
= TRUE
;
827 /* Use a staging texture for uploads if the underlying BO is busy. */
828 if (!(usage
& PIPE_TRANSFER_READ
) &&
829 (rctx
->ws
->cs_is_buffer_referenced(rctx
->cs
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
830 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
))) {
831 use_staging_texture
= TRUE
;
834 if (!permit_hardware_blit(ctx
->screen
, texture
) ||
835 (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
)) {
836 use_staging_texture
= FALSE
;
839 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
843 trans
= CALLOC_STRUCT(r600_transfer
);
846 pipe_resource_reference(&trans
->transfer
.resource
, texture
);
847 trans
->transfer
.level
= level
;
848 trans
->transfer
.usage
= usage
;
849 trans
->transfer
.box
= *box
;
850 if (rtex
->is_depth
) {
851 /* XXX: only readback the rectangle which is being mapped?
853 /* XXX: when discard is true, no need to read back from depth texture
855 struct r600_resource_texture
*staging_depth
;
857 r600_texture_depth_flush(ctx
, texture
, &staging_depth
,
859 box
->z
, box
->z
+ box
->depth
- 1);
860 if (!staging_depth
) {
861 R600_ERR("failed to create temporary texture to hold untiled copy\n");
862 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
866 trans
->transfer
.stride
= staging_depth
->pitch_in_bytes
[level
];
867 trans
->offset
= r600_texture_get_offset(staging_depth
, level
, box
->z
);
868 trans
->staging
= (struct r600_resource
*)staging_depth
;
869 return &trans
->transfer
;
870 } else if (use_staging_texture
) {
871 resource
.target
= PIPE_TEXTURE_2D
;
872 resource
.format
= texture
->format
;
873 resource
.width0
= box
->width
;
874 resource
.height0
= box
->height
;
876 resource
.array_size
= 1;
877 resource
.last_level
= 0;
878 resource
.nr_samples
= 0;
879 resource
.usage
= PIPE_USAGE_STAGING
;
881 resource
.flags
= R600_RESOURCE_FLAG_TRANSFER
;
882 /* For texture reading, the temporary (detiled) texture is used as
883 * a render target when blitting from a tiled texture. */
884 if (usage
& PIPE_TRANSFER_READ
) {
885 resource
.bind
|= PIPE_BIND_RENDER_TARGET
;
887 /* For texture writing, the temporary texture is used as a sampler
888 * when blitting into a tiled texture. */
889 if (usage
& PIPE_TRANSFER_WRITE
) {
890 resource
.bind
|= PIPE_BIND_SAMPLER_VIEW
;
892 /* Create the temporary texture. */
893 trans
->staging
= (struct r600_resource
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
894 if (trans
->staging
== NULL
) {
895 R600_ERR("failed to create temporary texture to hold untiled copy\n");
896 pipe_resource_reference(&trans
->transfer
.resource
, NULL
);
901 trans
->transfer
.stride
=
902 ((struct r600_resource_texture
*)trans
->staging
)->pitch_in_bytes
[0];
903 if (usage
& PIPE_TRANSFER_READ
) {
904 r600_copy_to_staging_texture(ctx
, trans
);
905 /* Always referenced in the blit. */
906 r600_flush(ctx
, NULL
, 0);
908 return &trans
->transfer
;
910 trans
->transfer
.stride
= rtex
->pitch_in_bytes
[level
];
911 trans
->transfer
.layer_stride
= rtex
->layer_size
[level
];
912 trans
->offset
= r600_texture_get_offset(rtex
, level
, box
->z
);
913 return &trans
->transfer
;
916 void r600_texture_transfer_destroy(struct pipe_context
*ctx
,
917 struct pipe_transfer
*transfer
)
919 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
920 struct pipe_resource
*texture
= transfer
->resource
;
921 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)texture
;
923 if (rtex
->is_depth
) {
924 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
925 struct pipe_box sbox
;
927 u_box_origin_2d(texture
->width0
, texture
->height0
, &sbox
);
929 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
930 0, 0, transfer
->box
.z
,
931 &rtransfer
->staging
->b
.b
, transfer
->level
,
934 } else if (rtransfer
->staging
) {
935 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
936 r600_copy_from_staging_texture(ctx
, rtransfer
);
940 if (rtransfer
->staging
)
941 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
943 pipe_resource_reference(&transfer
->resource
, NULL
);
947 void* r600_texture_transfer_map(struct pipe_context
*ctx
,
948 struct pipe_transfer
* transfer
)
950 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
951 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
952 struct radeon_winsys_cs_handle
*buf
;
953 struct r600_resource_texture
*rtex
=
954 (struct r600_resource_texture
*)transfer
->resource
;
955 enum pipe_format format
= transfer
->resource
->format
;
959 if ((transfer
->resource
->bind
& PIPE_BIND_GLOBAL
) && transfer
->resource
->target
== PIPE_BUFFER
) {
960 return r600_compute_global_transfer_map(ctx
, transfer
);
963 if (rtransfer
->staging
) {
964 buf
= ((struct r600_resource
*)rtransfer
->staging
)->cs_buf
;
966 buf
= ((struct r600_resource
*)transfer
->resource
)->cs_buf
;
969 if (rtex
->is_depth
|| !rtransfer
->staging
)
970 offset
= rtransfer
->offset
+
971 transfer
->box
.y
/ util_format_get_blockheight(format
) * transfer
->stride
+
972 transfer
->box
.x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
974 if (!(map
= rctx
->ws
->buffer_map(buf
, rctx
->cs
, transfer
->usage
))) {
981 void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
982 struct pipe_transfer
* transfer
)
984 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
985 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
986 struct radeon_winsys_cs_handle
*buf
;
988 if ((transfer
->resource
->bind
& PIPE_BIND_GLOBAL
) && transfer
->resource
->target
== PIPE_BUFFER
) {
989 return r600_compute_global_transfer_unmap(ctx
, transfer
);
992 if (rtransfer
->staging
) {
993 buf
= ((struct r600_resource
*)rtransfer
->staging
)->cs_buf
;
995 buf
= ((struct r600_resource
*)transfer
->resource
)->cs_buf
;
997 rctx
->ws
->buffer_unmap(buf
);
1000 void r600_init_surface_functions(struct r600_context
*r600
)
1002 r600
->context
.create_surface
= r600_create_surface
;
1003 r600
->context
.surface_destroy
= r600_surface_destroy
;
1006 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
1007 const unsigned char *swizzle_view
)
1010 unsigned char swizzle
[4];
1011 unsigned result
= 0;
1012 const uint32_t swizzle_shift
[4] = {
1015 const uint32_t swizzle_bit
[4] = {
1020 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
1022 memcpy(swizzle
, swizzle_format
, 4);
1026 for (i
= 0; i
< 4; i
++) {
1027 switch (swizzle
[i
]) {
1028 case UTIL_FORMAT_SWIZZLE_Y
:
1029 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
1031 case UTIL_FORMAT_SWIZZLE_Z
:
1032 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
1034 case UTIL_FORMAT_SWIZZLE_W
:
1035 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
1037 case UTIL_FORMAT_SWIZZLE_0
:
1038 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
1040 case UTIL_FORMAT_SWIZZLE_1
:
1041 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
1043 default: /* UTIL_FORMAT_SWIZZLE_X */
1044 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
1050 /* texture format translate */
1051 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
1052 enum pipe_format format
,
1053 const unsigned char *swizzle_view
,
1054 uint32_t *word4_p
, uint32_t *yuv_format_p
)
1056 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
1057 const struct util_format_description
*desc
;
1058 boolean uniform
= TRUE
;
1059 static int r600_enable_s3tc
= -1;
1060 bool is_srgb_valid
= FALSE
;
1063 const uint32_t sign_bit
[4] = {
1064 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
1065 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
1066 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
1067 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
1069 desc
= util_format_description(format
);
1071 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
);
1073 /* Colorspace (return non-RGB formats directly). */
1074 switch (desc
->colorspace
) {
1075 /* Depth stencil formats */
1076 case UTIL_FORMAT_COLORSPACE_ZS
:
1078 case PIPE_FORMAT_Z16_UNORM
:
1081 case PIPE_FORMAT_X24S8_UINT
:
1082 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1083 case PIPE_FORMAT_Z24X8_UNORM
:
1084 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1087 case PIPE_FORMAT_S8X24_UINT
:
1088 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1089 case PIPE_FORMAT_X8Z24_UNORM
:
1090 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1093 case PIPE_FORMAT_S8_UINT
:
1095 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1097 case PIPE_FORMAT_Z32_FLOAT
:
1098 result
= FMT_32_FLOAT
;
1100 case PIPE_FORMAT_X32_S8X24_UINT
:
1101 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1102 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1103 result
= FMT_X24_8_32_FLOAT
;
1109 case UTIL_FORMAT_COLORSPACE_YUV
:
1110 yuv_format
|= (1 << 30);
1112 case PIPE_FORMAT_UYVY
:
1113 case PIPE_FORMAT_YUYV
:
1117 goto out_unknown
; /* XXX */
1119 case UTIL_FORMAT_COLORSPACE_SRGB
:
1120 word4
|= S_038010_FORCE_DEGAMMA(1);
1127 if (r600_enable_s3tc
== -1) {
1128 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1129 if (rscreen
->info
.drm_minor
>= 9)
1130 r600_enable_s3tc
= 1;
1132 r600_enable_s3tc
= debug_get_bool_option("R600_ENABLE_S3TC", FALSE
);
1135 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1136 if (!r600_enable_s3tc
)
1140 case PIPE_FORMAT_RGTC1_SNORM
:
1141 case PIPE_FORMAT_LATC1_SNORM
:
1142 word4
|= sign_bit
[0];
1143 case PIPE_FORMAT_RGTC1_UNORM
:
1144 case PIPE_FORMAT_LATC1_UNORM
:
1147 case PIPE_FORMAT_RGTC2_SNORM
:
1148 case PIPE_FORMAT_LATC2_SNORM
:
1149 word4
|= sign_bit
[0] | sign_bit
[1];
1150 case PIPE_FORMAT_RGTC2_UNORM
:
1151 case PIPE_FORMAT_LATC2_UNORM
:
1159 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1161 if (!r600_enable_s3tc
)
1164 if (!util_format_s3tc_enabled
) {
1169 case PIPE_FORMAT_DXT1_RGB
:
1170 case PIPE_FORMAT_DXT1_RGBA
:
1171 case PIPE_FORMAT_DXT1_SRGB
:
1172 case PIPE_FORMAT_DXT1_SRGBA
:
1174 is_srgb_valid
= TRUE
;
1176 case PIPE_FORMAT_DXT3_RGBA
:
1177 case PIPE_FORMAT_DXT3_SRGBA
:
1179 is_srgb_valid
= TRUE
;
1181 case PIPE_FORMAT_DXT5_RGBA
:
1182 case PIPE_FORMAT_DXT5_SRGBA
:
1184 is_srgb_valid
= TRUE
;
1191 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1193 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1194 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1197 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1198 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1206 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1207 result
= FMT_5_9_9_9_SHAREDEXP
;
1209 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1210 result
= FMT_10_11_11_FLOAT
;
1215 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1216 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1217 word4
|= sign_bit
[i
];
1221 /* R8G8Bx_SNORM - XXX CxV8U8 */
1223 /* See whether the components are of the same size. */
1224 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1225 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1228 /* Non-uniform formats. */
1230 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1231 desc
->channel
[0].pure_integer
)
1232 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1233 switch(desc
->nr_channels
) {
1235 if (desc
->channel
[0].size
== 5 &&
1236 desc
->channel
[1].size
== 6 &&
1237 desc
->channel
[2].size
== 5) {
1243 if (desc
->channel
[0].size
== 5 &&
1244 desc
->channel
[1].size
== 5 &&
1245 desc
->channel
[2].size
== 5 &&
1246 desc
->channel
[3].size
== 1) {
1247 result
= FMT_1_5_5_5
;
1250 if (desc
->channel
[0].size
== 10 &&
1251 desc
->channel
[1].size
== 10 &&
1252 desc
->channel
[2].size
== 10 &&
1253 desc
->channel
[3].size
== 2) {
1254 result
= FMT_2_10_10_10
;
1262 /* Find the first non-VOID channel. */
1263 for (i
= 0; i
< 4; i
++) {
1264 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1272 /* uniform formats */
1273 switch (desc
->channel
[i
].type
) {
1274 case UTIL_FORMAT_TYPE_UNSIGNED
:
1275 case UTIL_FORMAT_TYPE_SIGNED
:
1277 if (!desc
->channel
[i
].normalized
&&
1278 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
1282 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1283 desc
->channel
[i
].pure_integer
)
1284 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1286 switch (desc
->channel
[i
].size
) {
1288 switch (desc
->nr_channels
) {
1293 result
= FMT_4_4_4_4
;
1298 switch (desc
->nr_channels
) {
1306 result
= FMT_8_8_8_8
;
1307 is_srgb_valid
= TRUE
;
1312 switch (desc
->nr_channels
) {
1320 result
= FMT_16_16_16_16
;
1325 switch (desc
->nr_channels
) {
1333 result
= FMT_32_32_32_32
;
1339 case UTIL_FORMAT_TYPE_FLOAT
:
1340 switch (desc
->channel
[i
].size
) {
1342 switch (desc
->nr_channels
) {
1344 result
= FMT_16_FLOAT
;
1347 result
= FMT_16_16_FLOAT
;
1350 result
= FMT_16_16_16_16_FLOAT
;
1355 switch (desc
->nr_channels
) {
1357 result
= FMT_32_FLOAT
;
1360 result
= FMT_32_32_FLOAT
;
1363 result
= FMT_32_32_32_32_FLOAT
;
1372 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
1377 *yuv_format_p
= yuv_format
;
1380 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */