src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_format_s3tc.h>
  31 #include <util/u_math.h>
  32 #include <util/u_inlines.h>
  33 #include <util/u_memory.h>
  34 #include "state_tracker/drm_driver.h"
  35 #include "pipebuffer/pb_buffer.h"
  36 #include "r600_pipe.h"
  37 #include "r600_resource.h"
  38 #include "r600_state_inlines.h"
  39 #include "r600d.h"
  40 #include "r600_formats.h"
  41
  42 /* Copy from a full GPU texture to a transfer's staging one. */
  43 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  44 {
  45         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  46         struct pipe_resource *texture = transfer->resource;
  47
  48         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  49                                 0, 0, 0, 0, texture, transfer->level,
  50                                 &transfer->box);
  51 }
  52
  53
  54 /* Copy from a transfer's staging texture to a full GPU one. */
  55 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  56 {
  57         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  58         struct pipe_resource *texture = transfer->resource;
  59         struct pipe_box sbox;
  60
  61         sbox.x = sbox.y = sbox.z = 0;
  62         sbox.width = transfer->box.width;
  63         sbox.height = transfer->box.height;
  64         /* XXX that might be wrong */
  65         sbox.depth = 1;
  66         ctx->resource_copy_region(ctx, texture, transfer->level,
  67                                   transfer->box.x, transfer->box.y, transfer->box.z,
  68                                   rtransfer->staging_texture,
  69                                   0, &sbox);
  70
  71         ctx->flush(ctx, 0, NULL);
  72 }
  73
  74 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  75                                         unsigned level, unsigned layer)
  76 {
  77         unsigned offset = rtex->offset[level];
  78
  79         switch (rtex->resource.b.b.b.target) {
  80         case PIPE_TEXTURE_3D:
  81         case PIPE_TEXTURE_CUBE:
  82         default:
  83                 return offset + layer * rtex->layer_size[level];
  84         }
  85 }
  86
  87 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
  88                                          enum pipe_format format,
  89                                          unsigned array_mode)
  90 {
  91         struct r600_screen* rscreen = (struct r600_screen *)screen;
  92         unsigned pixsize = util_format_get_blocksize(format);
  93         int p_align;
  94
  95         switch(array_mode) {
  96         case V_038000_ARRAY_1D_TILED_THIN1:
  97                 p_align = MAX2(8,
  98                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
  99                 break;
 100         case V_038000_ARRAY_2D_TILED_THIN1:
 101                 p_align = MAX2(rscreen->tiling_info->num_banks,
 102                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 103                                 rscreen->tiling_info->num_banks)) * 8;
 104                 break;
 105         case V_038000_ARRAY_LINEAR_ALIGNED:
 106                 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
 107                 break;
 108         case V_038000_ARRAY_LINEAR_GENERAL:
 109         default:
 110                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 111                 break;
 112         }
 113         return p_align;
 114 }
 115
 116 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 117                                           unsigned array_mode)
 118 {
 119         struct r600_screen* rscreen = (struct r600_screen *)screen;
 120         int h_align;
 121
 122         switch (array_mode) {
 123         case V_038000_ARRAY_2D_TILED_THIN1:
 124                 h_align = rscreen->tiling_info->num_channels * 8;
 125                 break;
 126         case V_038000_ARRAY_1D_TILED_THIN1:
 127         case V_038000_ARRAY_LINEAR_ALIGNED:
 128                 h_align = 8;
 129                 break;
 130         case V_038000_ARRAY_LINEAR_GENERAL:
 131         default:
 132                 h_align = 1;
 133                 break;
 134         }
 135         return h_align;
 136 }
 137
 138 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 139                                         enum pipe_format format,
 140                                         unsigned array_mode)
 141 {
 142         struct r600_screen* rscreen = (struct r600_screen *)screen;
 143         unsigned pixsize = util_format_get_blocksize(format);
 144         int p_align = r600_get_block_alignment(screen, format, array_mode);
 145         int h_align = r600_get_height_alignment(screen, array_mode);
 146         int b_align;
 147
 148         switch (array_mode) {
 149         case V_038000_ARRAY_2D_TILED_THIN1:
 150                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 151                                p_align * pixsize * h_align);
 152                 break;
 153         case V_038000_ARRAY_1D_TILED_THIN1:
 154         case V_038000_ARRAY_LINEAR_ALIGNED:
 155         case V_038000_ARRAY_LINEAR_GENERAL:
 156         default:
 157                 b_align = rscreen->tiling_info->group_bytes;
 158                 break;
 159         }
 160         return b_align;
 161 }
 162
 163 static unsigned mip_minify(unsigned size, unsigned level)
 164 {
 165         unsigned val;
 166         val = u_minify(size, level);
 167         if (level > 0)
 168                 val = util_next_power_of_two(val);
 169         return val;
 170 }
 171
 172 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
 173                                           struct r600_resource_texture *rtex,
 174                                           unsigned level)
 175 {
 176         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 177         unsigned nblocksx, block_align, width;
 178         unsigned blocksize = util_format_get_blocksize(ptex->format);
 179
 180         if (rtex->pitch_override)
 181                 return rtex->pitch_override / blocksize;
 182
 183         width = mip_minify(ptex->width0, level);
 184         nblocksx = util_format_get_nblocksx(ptex->format, width);
 185
 186         block_align = r600_get_block_alignment(screen, ptex->format,
 187                                               rtex->array_mode[level]);
 188         nblocksx = align(nblocksx, block_align);
 189         return nblocksx;
 190 }
 191
 192 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 193                                           struct r600_resource_texture *rtex,
 194                                           unsigned level)
 195 {
 196         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 197         unsigned height, tile_height;
 198
 199         height = mip_minify(ptex->height0, level);
 200         height = util_format_get_nblocksy(ptex->format, height);
 201         tile_height = r600_get_height_alignment(screen,
 202                                                 rtex->array_mode[level]);
 203         height = align(height, tile_height);
 204         return height;
 205 }
 206
 207 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 208                                         struct r600_resource_texture *rtex,
 209                                         unsigned level, unsigned array_mode)
 210 {
 211         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 212
 213         switch (array_mode) {
 214         case V_0280A0_ARRAY_LINEAR_GENERAL:
 215         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 216         case V_0280A0_ARRAY_1D_TILED_THIN1:
 217         default:
 218                 rtex->array_mode[level] = array_mode;
 219                 break;
 220         case V_0280A0_ARRAY_2D_TILED_THIN1:
 221         {
 222                 unsigned w, h, tile_height, tile_width;
 223
 224                 tile_height = r600_get_height_alignment(screen, array_mode);
 225                 tile_width = r600_get_block_alignment(screen, ptex->format, array_mode);
 226
 227                 w = mip_minify(ptex->width0, level);
 228                 h = mip_minify(ptex->height0, level);
 229                 if (w <= tile_width || h <= tile_height)
 230                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 231                 else
 232                         rtex->array_mode[level] = array_mode;
 233         }
 234         break;
 235         }
 236 }
 237
 238 static void r600_setup_miptree(struct pipe_screen *screen,
 239                                struct r600_resource_texture *rtex,
 240                                unsigned array_mode)
 241 {
 242         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 243         struct radeon *radeon = (struct radeon *)screen->winsys;
 244         enum chip_class chipc = r600_get_family_class(radeon);
 245         unsigned size, layer_size, i, offset;
 246         unsigned nblocksx, nblocksy;
 247
 248         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 249                 unsigned blocksize = util_format_get_blocksize(ptex->format);
 250
 251                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 252
 253                 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
 254                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 255
 256                 layer_size = nblocksx * nblocksy * blocksize;
 257                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 258                         if (chipc >= R700)
 259                                 size = layer_size * 8;
 260                         else
 261                                 size = layer_size * 6;
 262                 }
 263                 else if (ptex->target == PIPE_TEXTURE_3D)
 264                         size = layer_size * u_minify(ptex->depth0, i);
 265                 else
 266                         size = layer_size * ptex->array_size;
 267
 268                 /* align base image and start of miptree */
 269                 if ((i == 0) || (i == 1))
 270                         offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
 271                 rtex->offset[i] = offset;
 272                 rtex->layer_size[i] = layer_size;
 273                 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
 274                 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
 275
 276                 offset += size;
 277         }
 278         rtex->size = offset;
 279 }
 280
 281 /* Figure out whether u_blitter will fallback to a transfer operation.
 282  * If so, don't use a staging resource.
 283  */
 284 static boolean permit_hardware_blit(struct pipe_screen *screen,
 285                                         const struct pipe_resource *res)
 286 {
 287         unsigned bind;
 288
 289         if (util_format_is_depth_or_stencil(res->format))
 290                 bind = PIPE_BIND_DEPTH_STENCIL;
 291         else
 292                 bind = PIPE_BIND_RENDER_TARGET;
 293
 294         /* hackaround for S3TC */
 295         if (util_format_is_compressed(res->format))
 296                 return TRUE;
 297
 298         if (!screen->is_format_supported(screen,
 299                                 res->format,
 300                                 res->target,
 301                                 res->nr_samples,
 302                                 bind))
 303                 return FALSE;
 304
 305         if (!screen->is_format_supported(screen,
 306                                 res->format,
 307                                 res->target,
 308                                 res->nr_samples,
 309                                 PIPE_BIND_SAMPLER_VIEW))
 310                 return FALSE;
 311
 312         return TRUE;
 313 }
 314
 315 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 316                                         struct pipe_resource *ptex,
 317                                         struct winsys_handle *whandle)
 318 {
 319         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 320         struct r600_resource *resource = &rtex->resource;
 321         struct radeon *radeon = (struct radeon *)screen->winsys;
 322
 323         return r600_bo_get_winsys_handle(radeon, resource->bo,
 324                         rtex->pitch_in_bytes[0], whandle);
 325 }
 326
 327 static void r600_texture_destroy(struct pipe_screen *screen,
 328                                  struct pipe_resource *ptex)
 329 {
 330         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 331         struct r600_resource *resource = &rtex->resource;
 332         struct radeon *radeon = (struct radeon *)screen->winsys;
 333
 334         if (rtex->flushed_depth_texture)
 335                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 336
 337         if (resource->bo) {
 338                 r600_bo_reference(radeon, &resource->bo, NULL);
 339         }
 340         FREE(rtex);
 341 }
 342
 343 static const struct u_resource_vtbl r600_texture_vtbl =
 344 {
 345         r600_texture_get_handle,        /* get_handle */
 346         r600_texture_destroy,           /* resource_destroy */
 347         r600_texture_get_transfer,      /* get_transfer */
 348         r600_texture_transfer_destroy,  /* transfer_destroy */
 349         r600_texture_transfer_map,      /* transfer_map */
 350         u_default_transfer_flush_region,/* transfer_flush_region */
 351         r600_texture_transfer_unmap,    /* transfer_unmap */
 352         u_default_transfer_inline_write /* transfer_inline_write */
 353 };
 354
 355 static struct r600_resource_texture *
 356 r600_texture_create_object(struct pipe_screen *screen,
 357                            const struct pipe_resource *base,
 358                            unsigned array_mode,
 359                            unsigned pitch_in_bytes_override,
 360                            unsigned max_buffer_size,
 361                            struct r600_bo *bo)
 362 {
 363         struct r600_resource_texture *rtex;
 364         struct r600_resource *resource;
 365         struct radeon *radeon = (struct radeon *)screen->winsys;
 366
 367         rtex = CALLOC_STRUCT(r600_resource_texture);
 368         if (rtex == NULL)
 369                 return NULL;
 370
 371         resource = &rtex->resource;
 372         resource->b.b.b = *base;
 373         resource->b.b.vtbl = &r600_texture_vtbl;
 374         pipe_reference_init(&resource->b.b.b.reference, 1);
 375         resource->b.b.b.screen = screen;
 376         resource->bo = bo;
 377         rtex->pitch_override = pitch_in_bytes_override;
 378         /* only mark depth textures the HW can hit as depth textures */
 379         if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
 380                 rtex->depth = 1;
 381
 382         r600_setup_miptree(screen, rtex, array_mode);
 383
 384         resource->size = rtex->size;
 385
 386         if (!resource->bo) {
 387                 struct pipe_resource *ptex = &rtex->resource.b.b.b;
 388                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 389
 390                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 391                 if (!resource->bo) {
 392                         FREE(rtex);
 393                         return NULL;
 394                 }
 395         }
 396         return rtex;
 397 }
 398
 399 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 400                                                 const struct pipe_resource *templ)
 401 {
 402         unsigned array_mode = 0;
 403         static int force_tiling = -1;
 404
 405         /* Would like some magic "get_bool_option_once" routine.
 406          */
 407         if (force_tiling == -1) {
 408                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 409                 /* reenable when 2D tiling is fixed better */
 410                 /*if (r600_get_minor_version(rscreen->radeon) >= 9)
 411                         force_tiling = debug_get_bool_option("R600_TILING", TRUE);*/
 412                 force_tiling = debug_get_bool_option("R600_TILING", FALSE);
 413         }
 414
 415         if (force_tiling && permit_hardware_blit(screen, templ)) {
 416                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 417                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 418                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 419                 }
 420         }
 421
 422         if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 423             util_format_is_compressed(templ->format))
 424                 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
 425
 426         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 427                                                                   0, 0, NULL);
 428
 429 }
 430
 431 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 432                                                 struct pipe_resource *texture,
 433                                                 const struct pipe_surface *surf_tmpl)
 434 {
 435         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 436         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 437         unsigned level = surf_tmpl->u.tex.level;
 438
 439         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 440         if (surface == NULL)
 441                 return NULL;
 442         /* XXX no offset */
 443 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 444         pipe_reference_init(&surface->base.reference, 1);
 445         pipe_resource_reference(&surface->base.texture, texture);
 446         surface->base.context = pipe;
 447         surface->base.format = surf_tmpl->format;
 448         surface->base.width = mip_minify(texture->width0, level);
 449         surface->base.height = mip_minify(texture->height0, level);
 450         surface->base.usage = surf_tmpl->usage;
 451         surface->base.texture = texture;
 452         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 453         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 454         surface->base.u.tex.level = level;
 455
 456         surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
 457                                                             rtex, level);
 458         return &surface->base;
 459 }
 460
 461 static void r600_surface_destroy(struct pipe_context *pipe,
 462                                  struct pipe_surface *surface)
 463 {
 464         pipe_resource_reference(&surface->texture, NULL);
 465         FREE(surface);
 466 }
 467
 468
 469 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 470                                                const struct pipe_resource *templ,
 471                                                struct winsys_handle *whandle)
 472 {
 473         struct radeon *rw = (struct radeon*)screen->winsys;
 474         struct r600_bo *bo = NULL;
 475         unsigned array_mode = 0;
 476
 477         /* Support only 2D textures without mipmaps */
 478         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 479               templ->depth0 != 1 || templ->last_level != 0)
 480                 return NULL;
 481
 482         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 483         if (bo == NULL) {
 484                 return NULL;
 485         }
 486
 487         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 488                                                                   whandle->stride,
 489                                                                   0,
 490                                                                   bo);
 491 }
 492
 493 int r600_texture_depth_flush(struct pipe_context *ctx,
 494                              struct pipe_resource *texture, boolean just_create)
 495 {
 496         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 497         struct pipe_resource resource;
 498
 499         if (rtex->flushed_depth_texture)
 500                 goto out;
 501
 502         resource.target = PIPE_TEXTURE_2D;
 503         resource.format = texture->format;
 504         resource.width0 = texture->width0;
 505         resource.height0 = texture->height0;
 506         resource.depth0 = 1;
 507         resource.array_size = 1;
 508         resource.last_level = texture->last_level;
 509         resource.nr_samples = 0;
 510         resource.usage = PIPE_USAGE_DYNAMIC;
 511         resource.bind = 0;
 512         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 513
 514         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 515
 516         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 517         if (rtex->flushed_depth_texture == NULL) {
 518                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 519                 return -ENOMEM;
 520         }
 521
 522         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 523 out:
 524         if (just_create)
 525                 return 0;
 526
 527         /* XXX: only do this if the depth texture has actually changed:
 528          */
 529         r600_blit_uncompress_depth(ctx, rtex);
 530         return 0;
 531 }
 532
 533 /* Needs adjustment for pixelformat:
 534  */
 535 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 536 {
 537         return box->width * box->depth * box->height;
 538 };
 539
 540 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 541                                                 struct pipe_resource *texture,
 542                                                 unsigned level,
 543                                                 unsigned usage,
 544                                                 const struct pipe_box *box)
 545 {
 546         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 547         struct pipe_resource resource;
 548         struct r600_transfer *trans;
 549         int r;
 550         boolean use_staging_texture = FALSE;
 551
 552         /* We cannot map a tiled texture directly because the data is
 553          * in a different order, therefore we do detiling using a blit.
 554          *
 555          * Also, use a temporary in GTT memory for read transfers, as
 556          * the CPU is much happier reading out of cached system memory
 557          * than uncached VRAM.
 558          */
 559         if (R600_TEX_IS_TILED(rtex, level))
 560                 use_staging_texture = TRUE;
 561
 562         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 563                 use_staging_texture = TRUE;
 564
 565         /* XXX: Use a staging texture for uploads if the underlying BO
 566          * is busy.  No interface for checking that currently? so do
 567          * it eagerly whenever the transfer doesn't require a readback
 568          * and might block.
 569          */
 570         if ((usage & PIPE_TRANSFER_WRITE) &&
 571                         !(usage & (PIPE_TRANSFER_READ |
 572                                         PIPE_TRANSFER_DONTBLOCK |
 573                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 574                 use_staging_texture = TRUE;
 575
 576         if (!permit_hardware_blit(ctx->screen, texture) ||
 577                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 578                 use_staging_texture = FALSE;
 579
 580         trans = CALLOC_STRUCT(r600_transfer);
 581         if (trans == NULL)
 582                 return NULL;
 583         pipe_resource_reference(&trans->transfer.resource, texture);
 584         trans->transfer.level = level;
 585         trans->transfer.usage = usage;
 586         trans->transfer.box = *box;
 587         if (rtex->depth) {
 588                 /* XXX: only readback the rectangle which is being mapped?
 589                 */
 590                 /* XXX: when discard is true, no need to read back from depth texture
 591                 */
 592                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 593                 if (r < 0) {
 594                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 595                         pipe_resource_reference(&trans->transfer.resource, NULL);
 596                         FREE(trans);
 597                         return NULL;
 598                 }
 599                 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
 600                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 601                 return &trans->transfer;
 602         } else if (use_staging_texture) {
 603                 resource.target = PIPE_TEXTURE_2D;
 604                 resource.format = texture->format;
 605                 resource.width0 = box->width;
 606                 resource.height0 = box->height;
 607                 resource.depth0 = 1;
 608                 resource.array_size = 1;
 609                 resource.last_level = 0;
 610                 resource.nr_samples = 0;
 611                 resource.usage = PIPE_USAGE_STAGING;
 612                 resource.bind = 0;
 613                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 614                 /* For texture reading, the temporary (detiled) texture is used as
 615                  * a render target when blitting from a tiled texture. */
 616                 if (usage & PIPE_TRANSFER_READ) {
 617                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 618                 }
 619                 /* For texture writing, the temporary texture is used as a sampler
 620                  * when blitting into a tiled texture. */
 621                 if (usage & PIPE_TRANSFER_WRITE) {
 622                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 623                 }
 624                 /* Create the temporary texture. */
 625                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 626                 if (trans->staging_texture == NULL) {
 627                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 628                         pipe_resource_reference(&trans->transfer.resource, NULL);
 629                         FREE(trans);
 630                         return NULL;
 631                 }
 632
 633                 trans->transfer.stride =
 634                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 635                 if (usage & PIPE_TRANSFER_READ) {
 636                         r600_copy_to_staging_texture(ctx, trans);
 637                         /* Always referenced in the blit. */
 638                         ctx->flush(ctx, 0, NULL);
 639                 }
 640                 return &trans->transfer;
 641         }
 642         trans->transfer.stride = rtex->pitch_in_bytes[level];
 643         trans->transfer.layer_stride = rtex->layer_size[level];
 644         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 645         return &trans->transfer;
 646 }
 647
 648 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 649                                    struct pipe_transfer *transfer)
 650 {
 651         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 652         struct pipe_resource *texture = transfer->resource;
 653         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 654
 655         if (rtransfer->staging_texture) {
 656                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 657                         r600_copy_from_staging_texture(ctx, rtransfer);
 658                 }
 659                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 660         }
 661
 662         if (rtex->depth && !rtex->is_flushing_texture) {
 663                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 664                         r600_blit_push_depth(ctx, rtex);
 665         }
 666
 667         pipe_resource_reference(&transfer->resource, NULL);
 668         FREE(transfer);
 669 }
 670
 671 void* r600_texture_transfer_map(struct pipe_context *ctx,
 672                                 struct pipe_transfer* transfer)
 673 {
 674         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 675         struct r600_bo *bo;
 676         enum pipe_format format = transfer->resource->format;
 677         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 678         unsigned offset = 0;
 679         unsigned usage = 0;
 680         char *map;
 681
 682         if (rtransfer->staging_texture) {
 683                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 684         } else {
 685                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 686
 687                 if (rtex->flushed_depth_texture)
 688                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 689                 else
 690                         bo = ((struct r600_resource *)transfer->resource)->bo;
 691
 692                 offset = rtransfer->offset +
 693                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 694                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 695         }
 696
 697         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 698                 usage |= PB_USAGE_CPU_WRITE;
 699
 700                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 701                 }
 702
 703                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 704                 }
 705         }
 706
 707         if (transfer->usage & PIPE_TRANSFER_READ) {
 708                 usage |= PB_USAGE_CPU_READ;
 709         }
 710
 711         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 712                 usage |= PB_USAGE_DONTBLOCK;
 713         }
 714
 715         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 716                 usage |= PB_USAGE_UNSYNCHRONIZED;
 717         }
 718
 719         map = r600_bo_map(radeon, bo, usage, ctx);
 720         if (!map) {
 721                 return NULL;
 722         }
 723
 724         return map + offset;
 725 }
 726
 727 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 728                                  struct pipe_transfer* transfer)
 729 {
 730         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 731         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 732         struct r600_bo *bo;
 733
 734         if (rtransfer->staging_texture) {
 735                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 736         } else {
 737                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 738
 739                 if (rtex->flushed_depth_texture) {
 740                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 741                 } else {
 742                         bo = ((struct r600_resource *)transfer->resource)->bo;
 743                 }
 744         }
 745         r600_bo_unmap(radeon, bo);
 746 }
 747
 748 void r600_init_surface_functions(struct r600_pipe_context *r600)
 749 {
 750         r600->context.create_surface = r600_create_surface;
 751         r600->context.surface_destroy = r600_surface_destroy;
 752 }
 753
 754 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 755                 const unsigned char *swizzle_view)
 756 {
 757         unsigned i;
 758         unsigned char swizzle[4];
 759         unsigned result = 0;
 760         const uint32_t swizzle_shift[4] = {
 761                 16, 19, 22, 25,
 762         };
 763         const uint32_t swizzle_bit[4] = {
 764                 0, 1, 2, 3,
 765         };
 766
 767         if (swizzle_view) {
 768                 /* Combine two sets of swizzles. */
 769                 for (i = 0; i < 4; i++) {
 770                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 771                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 772                 }
 773         } else {
 774                 memcpy(swizzle, swizzle_format, 4);
 775         }
 776
 777         /* Get swizzle. */
 778         for (i = 0; i < 4; i++) {
 779                 switch (swizzle[i]) {
 780                 case UTIL_FORMAT_SWIZZLE_Y:
 781                         result |= swizzle_bit[1] << swizzle_shift[i];
 782                         break;
 783                 case UTIL_FORMAT_SWIZZLE_Z:
 784                         result |= swizzle_bit[2] << swizzle_shift[i];
 785                         break;
 786                 case UTIL_FORMAT_SWIZZLE_W:
 787                         result |= swizzle_bit[3] << swizzle_shift[i];
 788                         break;
 789                 case UTIL_FORMAT_SWIZZLE_0:
 790                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 791                         break;
 792                 case UTIL_FORMAT_SWIZZLE_1:
 793                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 794                         break;
 795                 default: /* UTIL_FORMAT_SWIZZLE_X */
 796                         result |= swizzle_bit[0] << swizzle_shift[i];
 797                 }
 798         }
 799         return result;
 800 }
 801
 802 /* texture format translate */
 803 uint32_t r600_translate_texformat(struct pipe_screen *screen,
 804                                   enum pipe_format format,
 805                                   const unsigned char *swizzle_view,
 806                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 807 {
 808         uint32_t result = 0, word4 = 0, yuv_format = 0;
 809         const struct util_format_description *desc;
 810         boolean uniform = TRUE;
 811         static int r600_enable_s3tc = -1;
 812
 813         int i;
 814         const uint32_t sign_bit[4] = {
 815                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 816                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 817                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 818                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 819         };
 820         desc = util_format_description(format);
 821
 822         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 823
 824         /* Colorspace (return non-RGB formats directly). */
 825         switch (desc->colorspace) {
 826                 /* Depth stencil formats */
 827         case UTIL_FORMAT_COLORSPACE_ZS:
 828                 switch (format) {
 829                 case PIPE_FORMAT_Z16_UNORM:
 830                         result = FMT_16;
 831                         goto out_word4;
 832                 case PIPE_FORMAT_X24S8_USCALED:
 833                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 834                 case PIPE_FORMAT_Z24X8_UNORM:
 835                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 836                         result = FMT_8_24;
 837                         goto out_word4;
 838                 case PIPE_FORMAT_S8X24_USCALED:
 839                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 840                 case PIPE_FORMAT_X8Z24_UNORM:
 841                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 842                         result = FMT_24_8;
 843                         goto out_word4;
 844                 case PIPE_FORMAT_S8_USCALED:
 845                         result = FMT_8;
 846                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 847                         goto out_word4;
 848                 default:
 849                         goto out_unknown;
 850                 }
 851
 852         case UTIL_FORMAT_COLORSPACE_YUV:
 853                 yuv_format |= (1 << 30);
 854                 switch (format) {
 855                 case PIPE_FORMAT_UYVY:
 856                 case PIPE_FORMAT_YUYV:
 857                 default:
 858                         break;
 859                 }
 860                 goto out_unknown; /* TODO */
 861
 862         case UTIL_FORMAT_COLORSPACE_SRGB:
 863                 word4 |= S_038010_FORCE_DEGAMMA(1);
 864                 break;
 865
 866         default:
 867                 break;
 868         }
 869
 870         if (r600_enable_s3tc == -1) {
 871                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 872                 if (r600_get_minor_version(rscreen->radeon) >= 9)
 873                         r600_enable_s3tc = 1;
 874                 else
 875                         r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 876         }
 877
 878         if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 879                 if (!r600_enable_s3tc)
 880                         goto out_unknown;
 881
 882                 switch (format) {
 883                 case PIPE_FORMAT_RGTC1_SNORM:
 884                         word4 |= sign_bit[0];
 885                 case PIPE_FORMAT_RGTC1_UNORM:
 886                         result = FMT_BC4;
 887                         goto out_word4;
 888                 case PIPE_FORMAT_RGTC2_SNORM:
 889                         word4 |= sign_bit[0] | sign_bit[1];
 890                 case PIPE_FORMAT_RGTC2_UNORM:
 891                         result = FMT_BC5;
 892                         goto out_word4;
 893                 default:
 894                         goto out_unknown;
 895                 }
 896         }
 897
 898         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 899
 900                 if (!r600_enable_s3tc)
 901                         goto out_unknown;
 902
 903                 if (!util_format_s3tc_enabled) {
 904                         goto out_unknown;
 905                 }
 906
 907                 switch (format) {
 908                 case PIPE_FORMAT_DXT1_RGB:
 909                 case PIPE_FORMAT_DXT1_RGBA:
 910                 case PIPE_FORMAT_DXT1_SRGB:
 911                 case PIPE_FORMAT_DXT1_SRGBA:
 912                         result = FMT_BC1;
 913                         goto out_word4;
 914                 case PIPE_FORMAT_DXT3_RGBA:
 915                 case PIPE_FORMAT_DXT3_SRGBA:
 916                         result = FMT_BC2;
 917                         goto out_word4;
 918                 case PIPE_FORMAT_DXT5_RGBA:
 919                 case PIPE_FORMAT_DXT5_SRGBA:
 920                         result = FMT_BC3;
 921                         goto out_word4;
 922                 default:
 923                         goto out_unknown;
 924                 }
 925         }
 926
 927
 928         for (i = 0; i < desc->nr_channels; i++) {
 929                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 930                         word4 |= sign_bit[i];
 931                 }
 932         }
 933
 934         /* R8G8Bx_SNORM - TODO CxV8U8 */
 935
 936         /* See whether the components are of the same size. */
 937         for (i = 1; i < desc->nr_channels; i++) {
 938                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 939         }
 940
 941         /* Non-uniform formats. */
 942         if (!uniform) {
 943                 switch(desc->nr_channels) {
 944                 case 3:
 945                         if (desc->channel[0].size == 5 &&
 946                             desc->channel[1].size == 6 &&
 947                             desc->channel[2].size == 5) {
 948                                 result = FMT_5_6_5;
 949                                 goto out_word4;
 950                         }
 951                         goto out_unknown;
 952                 case 4:
 953                         if (desc->channel[0].size == 5 &&
 954                             desc->channel[1].size == 5 &&
 955                             desc->channel[2].size == 5 &&
 956                             desc->channel[3].size == 1) {
 957                                 result = FMT_1_5_5_5;
 958                                 goto out_word4;
 959                         }
 960                         if (desc->channel[0].size == 10 &&
 961                             desc->channel[1].size == 10 &&
 962                             desc->channel[2].size == 10 &&
 963                             desc->channel[3].size == 2) {
 964                                 result = FMT_2_10_10_10;
 965                                 goto out_word4;
 966                         }
 967                         goto out_unknown;
 968                 }
 969                 goto out_unknown;
 970         }
 971
 972         /* Find the first non-VOID channel. */
 973         for (i = 0; i < 4; i++) {
 974                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 975                         break;
 976                 }
 977         }
 978
 979         if (i == 4)
 980                 goto out_unknown;
 981
 982         /* uniform formats */
 983         switch (desc->channel[i].type) {
 984         case UTIL_FORMAT_TYPE_UNSIGNED:
 985         case UTIL_FORMAT_TYPE_SIGNED:
 986                 if (!desc->channel[i].normalized &&
 987                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 988                         goto out_unknown;
 989                 }
 990
 991                 switch (desc->channel[i].size) {
 992                 case 4:
 993                         switch (desc->nr_channels) {
 994                         case 2:
 995                                 result = FMT_4_4;
 996                                 goto out_word4;
 997                         case 4:
 998                                 result = FMT_4_4_4_4;
 999                                 goto out_word4;
1000                         }
1001                         goto out_unknown;
1002                 case 8:
1003                         switch (desc->nr_channels) {
1004                         case 1:
1005                                 result = FMT_8;
1006                                 goto out_word4;
1007                         case 2:
1008                                 result = FMT_8_8;
1009                                 goto out_word4;
1010                         case 4:
1011                                 result = FMT_8_8_8_8;
1012                                 goto out_word4;
1013                         }
1014                         goto out_unknown;
1015                 case 16:
1016                         switch (desc->nr_channels) {
1017                         case 1:
1018                                 result = FMT_16;
1019                                 goto out_word4;
1020                         case 2:
1021                                 result = FMT_16_16;
1022                                 goto out_word4;
1023                         case 4:
1024                                 result = FMT_16_16_16_16;
1025                                 goto out_word4;
1026                         }
1027                         goto out_unknown;
1028                 case 32:
1029                         switch (desc->nr_channels) {
1030                         case 1:
1031                                 result = FMT_32;
1032                                 goto out_word4;
1033                         case 2:
1034                                 result = FMT_32_32;
1035                                 goto out_word4;
1036                         case 4:
1037                                 result = FMT_32_32_32_32;
1038                                 goto out_word4;
1039                         }
1040                 }
1041                 goto out_unknown;
1042
1043         case UTIL_FORMAT_TYPE_FLOAT:
1044                 switch (desc->channel[i].size) {
1045                 case 16:
1046                         switch (desc->nr_channels) {
1047                         case 1:
1048                                 result = FMT_16_FLOAT;
1049                                 goto out_word4;
1050                         case 2:
1051                                 result = FMT_16_16_FLOAT;
1052                                 goto out_word4;
1053                         case 4:
1054                                 result = FMT_16_16_16_16_FLOAT;
1055                                 goto out_word4;
1056                         }
1057                         goto out_unknown;
1058                 case 32:
1059                         switch (desc->nr_channels) {
1060                         case 1:
1061                                 result = FMT_32_FLOAT;
1062                                 goto out_word4;
1063                         case 2:
1064                                 result = FMT_32_32_FLOAT;
1065                                 goto out_word4;
1066                         case 4:
1067                                 result = FMT_32_32_32_32_FLOAT;
1068                                 goto out_word4;
1069                         }
1070                 }
1071
1072         }
1073 out_word4:
1074         if (word4_p)
1075                 *word4_p = word4;
1076         if (yuv_format_p)
1077                 *yuv_format_p = yuv_format;
1078         return result;
1079 out_unknown:
1080 //      R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1081         return ~0;
1082 }