2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_pack_color.h"
34 #include "util/u_surface.h"
35 #include "util/os_time.h"
39 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
40 struct r600_texture
*rtex
);
41 static enum radeon_surf_mode
42 r600_choose_tiling(struct r600_common_screen
*rscreen
,
43 const struct pipe_resource
*templ
);
46 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
47 struct r600_texture
*rdst
,
48 unsigned dst_level
, unsigned dstx
,
49 unsigned dsty
, unsigned dstz
,
50 struct r600_texture
*rsrc
,
52 const struct pipe_box
*src_box
)
57 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
62 rdst
->resource
.b
.b
.nr_samples
> 1)
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
69 if (rsrc
->is_depth
|| rdst
->is_depth
)
73 * src: Both texture and SDMA paths need decompression. Use SDMA.
74 * dst: If overwriting the whole texture, discard CMASK and use
75 * SDMA. Otherwise, use the 3D path.
77 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
78 /* The CMASK clear is only enabled for the first level. */
79 assert(dst_level
== 0);
80 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
81 dstx
, dsty
, dstz
, src_box
->width
,
82 src_box
->height
, src_box
->depth
))
85 r600_texture_discard_cmask(rctx
->screen
, rdst
);
88 /* All requirements are met. Prepare textures for SDMA. */
89 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
90 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
92 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
93 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
98 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
99 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
100 struct pipe_resource
*dst
,
102 unsigned dstx
, unsigned dsty
, unsigned dstz
,
103 struct pipe_resource
*src
,
105 const struct pipe_box
*src_box
)
107 struct pipe_blit_info blit
;
109 memset(&blit
, 0, sizeof(blit
));
110 blit
.src
.resource
= src
;
111 blit
.src
.format
= src
->format
;
112 blit
.src
.level
= src_level
;
113 blit
.src
.box
= *src_box
;
114 blit
.dst
.resource
= dst
;
115 blit
.dst
.format
= dst
->format
;
116 blit
.dst
.level
= dst_level
;
117 blit
.dst
.box
.x
= dstx
;
118 blit
.dst
.box
.y
= dsty
;
119 blit
.dst
.box
.z
= dstz
;
120 blit
.dst
.box
.width
= src_box
->width
;
121 blit
.dst
.box
.height
= src_box
->height
;
122 blit
.dst
.box
.depth
= src_box
->depth
;
123 blit
.mask
= util_format_get_mask(src
->format
) &
124 util_format_get_mask(dst
->format
);
125 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
128 pipe
->blit(pipe
, &blit
);
132 /* Copy from a full GPU texture to a transfer's staging one. */
133 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
135 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
136 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
137 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
138 struct pipe_resource
*src
= transfer
->resource
;
140 if (src
->nr_samples
> 1) {
141 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
142 src
, transfer
->level
, &transfer
->box
);
146 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
150 /* Copy from a transfer's staging texture to a full GPU one. */
151 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
153 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
154 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
155 struct pipe_resource
*dst
= transfer
->resource
;
156 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
157 struct pipe_box sbox
;
159 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
161 if (dst
->nr_samples
> 1) {
162 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
163 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
168 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
169 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
173 static unsigned r600_texture_get_offset(struct r600_common_screen
*rscreen
,
174 struct r600_texture
*rtex
, unsigned level
,
175 const struct pipe_box
*box
,
177 unsigned *layer_stride
)
179 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
181 assert((uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
182 *layer_stride
= (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
185 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
187 /* Each texture is an array of mipmap levels. Each level is
188 * an array of slices. */
189 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
190 box
->z
* (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
191 (box
->y
/ rtex
->surface
.blk_h
*
192 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
193 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
196 static int r600_init_surface(struct r600_common_screen
*rscreen
,
197 struct radeon_surf
*surface
,
198 const struct pipe_resource
*ptex
,
199 enum radeon_surf_mode array_mode
,
200 unsigned pitch_in_bytes_override
,
204 bool is_flushed_depth
)
206 const struct util_format_description
*desc
=
207 util_format_description(ptex
->format
);
208 bool is_depth
, is_stencil
;
210 unsigned i
, bpe
, flags
= 0;
212 is_depth
= util_format_has_depth(desc
);
213 is_stencil
= util_format_has_stencil(desc
);
215 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
216 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
217 bpe
= 4; /* stencil is allocated separately on evergreen */
219 bpe
= util_format_get_blocksize(ptex
->format
);
220 assert(util_is_power_of_two(bpe
));
223 if (!is_flushed_depth
&& is_depth
) {
224 flags
|= RADEON_SURF_ZBUFFER
;
227 flags
|= RADEON_SURF_SBUFFER
;
230 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
231 /* This should catch bugs in gallium users setting incorrect flags. */
232 assert(ptex
->nr_samples
<= 1 &&
233 ptex
->array_size
== 1 &&
235 ptex
->last_level
== 0 &&
236 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
238 flags
|= RADEON_SURF_SCANOUT
;
241 if (ptex
->bind
& PIPE_BIND_SHARED
)
242 flags
|= RADEON_SURF_SHAREABLE
;
244 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
245 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
246 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
248 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
249 array_mode
, surface
);
254 if (pitch_in_bytes_override
&&
255 pitch_in_bytes_override
!= surface
->u
.legacy
.level
[0].nblk_x
* bpe
) {
256 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
259 surface
->u
.legacy
.level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
260 surface
->u
.legacy
.level
[0].slice_size_dw
=
261 ((uint64_t)pitch_in_bytes_override
* surface
->u
.legacy
.level
[0].nblk_y
) / 4;
265 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
266 surface
->u
.legacy
.level
[i
].offset
+= offset
;
272 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
273 struct r600_texture
*rtex
,
274 struct radeon_bo_metadata
*metadata
)
276 struct radeon_surf
*surface
= &rtex
->surface
;
278 memset(metadata
, 0, sizeof(*metadata
));
280 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
281 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
282 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
283 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
284 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
285 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
286 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
287 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
288 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
289 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
290 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
291 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
294 static void r600_surface_import_metadata(struct r600_common_screen
*rscreen
,
295 struct radeon_surf
*surf
,
296 struct radeon_bo_metadata
*metadata
,
297 enum radeon_surf_mode
*array_mode
,
300 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
301 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
302 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
303 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
304 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
305 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
307 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
308 *array_mode
= RADEON_SURF_MODE_2D
;
309 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
310 *array_mode
= RADEON_SURF_MODE_1D
;
312 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
314 *is_scanout
= metadata
->u
.legacy
.scanout
;
317 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
318 struct r600_texture
*rtex
)
320 struct r600_common_screen
*rscreen
= rctx
->screen
;
321 struct pipe_context
*ctx
= &rctx
->b
;
323 if (ctx
== rscreen
->aux_context
)
324 mtx_lock(&rscreen
->aux_context_lock
);
326 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
327 ctx
->flush(ctx
, NULL
, 0);
329 if (ctx
== rscreen
->aux_context
)
330 mtx_unlock(&rscreen
->aux_context_lock
);
333 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
334 struct r600_texture
*rtex
)
336 if (!rtex
->cmask
.size
)
339 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
342 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
343 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
344 rtex
->dirty_level_mask
= 0;
346 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
348 if (rtex
->cmask_buffer
!= &rtex
->resource
)
349 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
351 /* Notify all contexts about the change. */
352 p_atomic_inc(&rscreen
->dirty_tex_counter
);
353 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
356 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
357 struct r600_texture
*rtex
,
358 unsigned new_bind_flag
,
359 bool invalidate_storage
)
361 struct pipe_screen
*screen
= rctx
->b
.screen
;
362 struct r600_texture
*new_tex
;
363 struct pipe_resource templ
= rtex
->resource
.b
.b
;
366 templ
.bind
|= new_bind_flag
;
368 /* r600g doesn't react to dirty_tex_descriptor_counter */
369 if (rctx
->chip_class
< SI
)
372 if (rtex
->resource
.b
.is_shared
)
375 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
376 if (rtex
->surface
.is_linear
)
379 /* This fails with MSAA, depth, and compressed textures. */
380 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
381 RADEON_SURF_MODE_LINEAR_ALIGNED
)
385 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
389 /* Copy the pixels to the new texture. */
390 if (!invalidate_storage
) {
391 for (i
= 0; i
<= templ
.last_level
; i
++) {
395 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
396 util_max_layer(&templ
, i
) + 1, &box
);
398 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
399 &rtex
->resource
.b
.b
, i
, &box
);
403 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
404 r600_texture_discard_cmask(rctx
->screen
, rtex
);
407 /* Replace the structure fields of rtex. */
408 rtex
->resource
.b
.b
.bind
= templ
.bind
;
409 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
410 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
411 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
412 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
413 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
414 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
415 rtex
->resource
.domains
= new_tex
->resource
.domains
;
416 rtex
->resource
.flags
= new_tex
->resource
.flags
;
417 rtex
->size
= new_tex
->size
;
418 rtex
->db_render_format
= new_tex
->db_render_format
;
419 rtex
->db_compatible
= new_tex
->db_compatible
;
420 rtex
->can_sample_z
= new_tex
->can_sample_z
;
421 rtex
->can_sample_s
= new_tex
->can_sample_s
;
422 rtex
->surface
= new_tex
->surface
;
423 rtex
->fmask
= new_tex
->fmask
;
424 rtex
->cmask
= new_tex
->cmask
;
425 rtex
->cb_color_info
= new_tex
->cb_color_info
;
426 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
427 rtex
->htile_offset
= new_tex
->htile_offset
;
428 rtex
->depth_cleared
= new_tex
->depth_cleared
;
429 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
430 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
431 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
433 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
434 assert(!rtex
->htile_offset
);
435 assert(!rtex
->cmask
.size
);
436 assert(!rtex
->fmask
.size
);
437 assert(!rtex
->is_depth
);
440 r600_texture_reference(&new_tex
, NULL
);
442 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
445 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
446 struct pipe_context
*ctx
,
447 struct pipe_resource
*resource
,
448 struct winsys_handle
*whandle
,
451 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
452 struct r600_common_context
*rctx
;
453 struct r600_resource
*res
= (struct r600_resource
*)resource
;
454 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
455 struct radeon_bo_metadata metadata
;
456 bool update_metadata
= false;
457 unsigned stride
, offset
, slice_size
;
459 ctx
= threaded_context_unwrap_sync(ctx
);
460 rctx
= (struct r600_common_context
*)(ctx
? ctx
: rscreen
->aux_context
);
462 if (resource
->target
!= PIPE_BUFFER
) {
463 /* This is not supported now, but it might be required for OpenCL
464 * interop in the future.
466 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
469 /* Move a suballocated texture into a non-suballocated allocation. */
470 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
471 rtex
->surface
.tile_swizzle
) {
472 assert(!res
->b
.is_shared
);
473 r600_reallocate_texture_inplace(rctx
, rtex
,
474 PIPE_BIND_SHARED
, false);
475 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
476 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
477 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
478 assert(rtex
->surface
.tile_swizzle
== 0);
481 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
483 /* Eliminate fast clear (CMASK) */
484 r600_eliminate_fast_color_clear(rctx
, rtex
);
486 /* Disable CMASK if flush_resource isn't going
489 if (rtex
->cmask
.size
)
490 r600_texture_discard_cmask(rscreen
, rtex
);
494 if (!res
->b
.is_shared
|| update_metadata
) {
495 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
496 if (rscreen
->query_opaque_metadata
)
497 rscreen
->query_opaque_metadata(rscreen
, rtex
,
500 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
503 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
504 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
506 slice_size
= (uint64_t)rtex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
508 /* Move a suballocated buffer into a non-suballocated allocation. */
509 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
)) {
510 assert(!res
->b
.is_shared
);
512 /* Allocate a new buffer with PIPE_BIND_SHARED. */
513 struct pipe_resource templ
= res
->b
.b
;
514 templ
.bind
|= PIPE_BIND_SHARED
;
516 struct pipe_resource
*newb
=
517 screen
->resource_create(screen
, &templ
);
521 /* Copy the old buffer contents to the new one. */
523 u_box_1d(0, newb
->width0
, &box
);
524 rctx
->b
.resource_copy_region(&rctx
->b
, newb
, 0, 0, 0, 0,
526 /* Move the new buffer storage to the old pipe_resource. */
527 r600_replace_buffer_storage(&rctx
->b
, &res
->b
.b
, newb
);
528 pipe_resource_reference(&newb
, NULL
);
530 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
531 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
540 if (res
->b
.is_shared
) {
541 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
544 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
545 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
546 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
548 res
->b
.is_shared
= true;
549 res
->external_usage
= usage
;
552 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
553 slice_size
, whandle
);
556 static void r600_texture_destroy(struct pipe_screen
*screen
,
557 struct pipe_resource
*ptex
)
559 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
560 struct r600_resource
*resource
= &rtex
->resource
;
562 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
563 pipe_resource_reference((struct pipe_resource
**)&resource
->immed_buffer
, NULL
);
565 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
566 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
568 pb_reference(&resource
->buf
, NULL
);
572 static const struct u_resource_vtbl r600_texture_vtbl
;
574 /* The number of samples can be specified independently of the texture. */
575 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
576 struct r600_texture
*rtex
,
578 struct r600_fmask_info
*out
)
580 /* FMASK is allocated like an ordinary texture. */
581 struct pipe_resource templ
= rtex
->resource
.b
.b
;
582 struct radeon_surf fmask
= {};
585 memset(out
, 0, sizeof(*out
));
587 templ
.nr_samples
= 1;
588 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
590 /* Use the same parameters and tile mode. */
591 fmask
.u
.legacy
.bankw
= rtex
->surface
.u
.legacy
.bankw
;
592 fmask
.u
.legacy
.bankh
= rtex
->surface
.u
.legacy
.bankh
;
593 fmask
.u
.legacy
.mtilea
= rtex
->surface
.u
.legacy
.mtilea
;
594 fmask
.u
.legacy
.tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
597 fmask
.u
.legacy
.bankh
= 4;
599 switch (nr_samples
) {
608 R600_ERR("Invalid sample count for FMASK allocation.\n");
612 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
613 * This can be fixed by writing a separate FMASK allocator specifically
614 * for R600-R700 asics. */
615 if (rscreen
->chip_class
<= R700
) {
619 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
620 RADEON_SURF_MODE_2D
, &fmask
)) {
621 R600_ERR("Got error in surface_init while allocating FMASK.\n");
625 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
627 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
628 if (out
->slice_tile_max
)
629 out
->slice_tile_max
-= 1;
631 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
632 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
633 out
->bank_height
= fmask
.u
.legacy
.bankh
;
634 out
->tile_swizzle
= fmask
.tile_swizzle
;
635 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
636 out
->size
= fmask
.surf_size
;
639 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
640 struct r600_texture
*rtex
)
642 r600_texture_get_fmask_info(rscreen
, rtex
,
643 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
645 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
646 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
649 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
650 struct r600_texture
*rtex
,
651 struct r600_cmask_info
*out
)
653 unsigned cmask_tile_width
= 8;
654 unsigned cmask_tile_height
= 8;
655 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
656 unsigned element_bits
= 4;
657 unsigned cmask_cache_bits
= 1024;
658 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
659 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
661 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
662 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
663 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
664 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
665 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
667 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
668 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
670 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
671 unsigned slice_bytes
=
672 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
674 assert(macro_tile_width
% 128 == 0);
675 assert(macro_tile_height
% 128 == 0);
677 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
678 out
->alignment
= MAX2(256, base_align
);
679 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
680 align(slice_bytes
, base_align
);
683 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
684 struct r600_texture
*rtex
)
686 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
688 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
689 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
691 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
694 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
695 struct r600_texture
*rtex
)
697 if (rtex
->cmask_buffer
)
700 assert(rtex
->cmask
.size
== 0);
702 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
704 rtex
->cmask_buffer
= (struct r600_resource
*)
705 r600_aligned_buffer_create(&rscreen
->b
,
706 R600_RESOURCE_FLAG_UNMAPPABLE
,
709 rtex
->cmask
.alignment
);
710 if (rtex
->cmask_buffer
== NULL
) {
711 rtex
->cmask
.size
= 0;
715 /* update colorbuffer state bits */
716 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
718 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
720 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
723 void eg_resource_alloc_immed(struct r600_common_screen
*rscreen
,
724 struct r600_resource
*res
,
727 res
->immed_buffer
= (struct r600_resource
*)
728 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
729 PIPE_USAGE_DEFAULT
, immed_size
);
732 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
733 struct r600_texture
*rtex
)
735 unsigned cl_width
, cl_height
, width
, height
;
736 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
737 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
739 rtex
->surface
.htile_size
= 0;
741 if (rscreen
->chip_class
<= EVERGREEN
&&
742 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
745 /* HW bug on R6xx. */
746 if (rscreen
->chip_class
== R600
&&
747 (rtex
->resource
.b
.b
.width0
> 7680 ||
748 rtex
->resource
.b
.b
.height0
> 7680))
777 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
778 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
780 slice_elements
= (width
* height
) / (8 * 8);
781 slice_bytes
= slice_elements
* 4;
783 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
784 base_align
= num_pipes
* pipe_interleave_bytes
;
786 rtex
->surface
.htile_alignment
= base_align
;
787 rtex
->surface
.htile_size
=
788 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
789 align(slice_bytes
, base_align
);
792 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
793 struct r600_texture
*rtex
)
795 r600_texture_get_htile_size(rscreen
, rtex
);
797 if (!rtex
->surface
.htile_size
)
800 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
801 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
804 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
805 struct r600_texture
*rtex
, struct u_log_context
*log
)
809 /* Common parameters. */
810 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
811 "blk_h=%u, array_size=%u, last_level=%u, "
812 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
813 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
814 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
816 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
817 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
818 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
820 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
821 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
822 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
823 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
824 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
825 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
827 if (rtex
->fmask
.size
)
828 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
829 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
830 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
831 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
832 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
834 if (rtex
->cmask
.size
)
835 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
836 "slice_tile_max=%u\n",
837 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
838 rtex
->cmask
.slice_tile_max
);
840 if (rtex
->htile_offset
)
841 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u "
843 rtex
->htile_offset
, rtex
->surface
.htile_size
,
844 rtex
->surface
.htile_alignment
);
846 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
847 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
848 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
849 "mode=%u, tiling_index = %u\n",
850 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
851 (uint64_t)rtex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
852 u_minify(rtex
->resource
.b
.b
.width0
, i
),
853 u_minify(rtex
->resource
.b
.b
.height0
, i
),
854 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
855 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
856 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
857 rtex
->surface
.u
.legacy
.level
[i
].mode
,
858 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
860 if (rtex
->surface
.has_stencil
) {
861 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
862 rtex
->surface
.u
.legacy
.stencil_tile_split
);
863 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
864 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
865 "slice_size=%"PRIu64
", npix_x=%u, "
866 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
867 "mode=%u, tiling_index = %u\n",
868 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
869 (uint64_t)rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
870 u_minify(rtex
->resource
.b
.b
.width0
, i
),
871 u_minify(rtex
->resource
.b
.b
.height0
, i
),
872 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
873 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
874 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
875 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
876 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
881 /* Common processing for r600_texture_create and r600_texture_from_handle */
882 static struct r600_texture
*
883 r600_texture_create_object(struct pipe_screen
*screen
,
884 const struct pipe_resource
*base
,
885 struct pb_buffer
*buf
,
886 struct radeon_surf
*surface
)
888 struct r600_texture
*rtex
;
889 struct r600_resource
*resource
;
890 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
892 rtex
= CALLOC_STRUCT(r600_texture
);
896 resource
= &rtex
->resource
;
897 resource
->b
.b
= *base
;
898 resource
->b
.b
.next
= NULL
;
899 resource
->b
.vtbl
= &r600_texture_vtbl
;
900 pipe_reference_init(&resource
->b
.b
.reference
, 1);
901 resource
->b
.b
.screen
= screen
;
903 /* don't include stencil-only formats which we don't support for rendering */
904 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
906 rtex
->surface
= *surface
;
907 rtex
->size
= rtex
->surface
.surf_size
;
908 rtex
->db_render_format
= base
->format
;
910 /* Tiled depth textures utilize the non-displayable tile order.
911 * This must be done after r600_setup_surface.
912 * Applies to R600-Cayman. */
913 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
914 /* Applies to GCN. */
915 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
917 if (rtex
->is_depth
) {
918 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
919 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
920 rscreen
->chip_class
>= EVERGREEN
) {
921 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
922 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
924 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
925 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
926 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
927 rtex
->can_sample_z
= true;
930 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
931 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
932 rtex
->db_compatible
= true;
934 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
935 r600_texture_allocate_htile(rscreen
, rtex
);
938 if (base
->nr_samples
> 1) {
940 r600_texture_allocate_fmask(rscreen
, rtex
);
941 r600_texture_allocate_cmask(rscreen
, rtex
);
942 rtex
->cmask_buffer
= &rtex
->resource
;
944 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
951 /* Now create the backing buffer. */
953 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
954 rtex
->surface
.surf_alignment
);
956 /* Displayable surfaces are not suballocated. */
957 if (resource
->b
.b
.bind
& PIPE_BIND_SCANOUT
)
958 resource
->flags
|= RADEON_FLAG_NO_SUBALLOC
;
960 if (!r600_alloc_resource(rscreen
, resource
)) {
966 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
967 resource
->bo_size
= buf
->size
;
968 resource
->bo_alignment
= buf
->alignment
;
969 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
970 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
971 resource
->vram_usage
= buf
->size
;
972 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
973 resource
->gart_usage
= buf
->size
;
976 if (rtex
->cmask
.size
) {
977 /* Initialize the cmask to 0xCC (= compressed state). */
978 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
979 rtex
->cmask
.offset
, rtex
->cmask
.size
,
982 if (rtex
->htile_offset
) {
983 uint32_t clear_value
= 0;
985 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
987 rtex
->surface
.htile_size
,
991 /* Initialize the CMASK base register value. */
992 rtex
->cmask
.base_address_reg
=
993 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
995 if (rscreen
->debug_flags
& DBG_VM
) {
996 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
997 rtex
->resource
.gpu_address
,
998 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
999 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1000 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1003 if (rscreen
->debug_flags
& DBG_TEX
) {
1005 struct u_log_context log
;
1006 u_log_context_init(&log
);
1007 r600_print_texture_info(rscreen
, rtex
, &log
);
1008 u_log_new_page_print(&log
, stdout
);
1010 u_log_context_destroy(&log
);
1016 static enum radeon_surf_mode
1017 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1018 const struct pipe_resource
*templ
)
1020 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1021 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1022 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1023 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1025 /* MSAA resources must be 2D tiled. */
1026 if (templ
->nr_samples
> 1)
1027 return RADEON_SURF_MODE_2D
;
1029 /* Transfer resources should be linear. */
1030 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1031 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1033 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1034 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1035 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1036 (templ
->target
== PIPE_TEXTURE_2D
||
1037 templ
->target
== PIPE_TEXTURE_3D
))
1038 force_tiling
= true;
1040 /* Handle common candidates for the linear mode.
1041 * Compressed textures and DB surfaces must always be tiled.
1043 if (!force_tiling
&&
1044 !is_depth_stencil
&&
1045 !util_format_is_compressed(templ
->format
)) {
1046 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1047 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1049 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1050 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1051 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1053 if (templ
->bind
& PIPE_BIND_LINEAR
)
1054 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1056 /* Textures with a very small height are recommended to be linear. */
1057 if (templ
->target
== PIPE_TEXTURE_1D
||
1058 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1059 /* Only very thin and long 2D textures should benefit from
1060 * linear_aligned. */
1061 (templ
->width0
> 8 && templ
->height0
<= 2))
1062 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1064 /* Textures likely to be mapped often. */
1065 if (templ
->usage
== PIPE_USAGE_STAGING
||
1066 templ
->usage
== PIPE_USAGE_STREAM
)
1067 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1070 /* Make small textures 1D tiled. */
1071 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1072 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1073 return RADEON_SURF_MODE_1D
;
1075 /* The allocator will switch to 1D if needed. */
1076 return RADEON_SURF_MODE_2D
;
1079 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1080 const struct pipe_resource
*templ
)
1082 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1083 struct radeon_surf surface
= {0};
1084 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1087 r
= r600_init_surface(rscreen
, &surface
, templ
,
1088 r600_choose_tiling(rscreen
, templ
), 0, 0,
1089 false, false, is_flushed_depth
);
1094 return (struct pipe_resource
*)
1095 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1098 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1099 const struct pipe_resource
*templ
,
1100 struct winsys_handle
*whandle
,
1103 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1104 struct pb_buffer
*buf
= NULL
;
1105 unsigned stride
= 0, offset
= 0;
1106 enum radeon_surf_mode array_mode
;
1107 struct radeon_surf surface
= {};
1109 struct radeon_bo_metadata metadata
= {};
1110 struct r600_texture
*rtex
;
1113 /* Support only 2D textures without mipmaps */
1114 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1115 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1118 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1122 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1123 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
1124 &array_mode
, &is_scanout
);
1126 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1127 offset
, true, is_scanout
, false);
1132 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1136 rtex
->resource
.b
.is_shared
= true;
1137 rtex
->resource
.external_usage
= usage
;
1139 if (rscreen
->apply_opaque_metadata
)
1140 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1142 assert(rtex
->surface
.tile_swizzle
== 0);
1143 return &rtex
->resource
.b
.b
;
1146 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1147 struct pipe_resource
*texture
,
1148 struct r600_texture
**staging
)
1150 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1151 struct pipe_resource resource
;
1152 struct r600_texture
**flushed_depth_texture
= staging
?
1153 staging
: &rtex
->flushed_depth_texture
;
1154 enum pipe_format pipe_format
= texture
->format
;
1157 if (rtex
->flushed_depth_texture
)
1158 return true; /* it's ready */
1160 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1161 switch (pipe_format
) {
1162 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1163 /* Save memory by not allocating the S plane. */
1164 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1166 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1167 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1168 /* Save memory bandwidth by not copying the
1169 * stencil part during flush.
1171 * This potentially increases memory bandwidth
1172 * if an application uses both Z and S texturing
1173 * simultaneously (a flushed Z24S8 texture
1174 * would be stored compactly), but how often
1175 * does that really happen?
1177 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1181 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1182 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1184 /* DB->CB copies to an 8bpp surface don't work. */
1185 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1189 memset(&resource
, 0, sizeof(resource
));
1190 resource
.target
= texture
->target
;
1191 resource
.format
= pipe_format
;
1192 resource
.width0
= texture
->width0
;
1193 resource
.height0
= texture
->height0
;
1194 resource
.depth0
= texture
->depth0
;
1195 resource
.array_size
= texture
->array_size
;
1196 resource
.last_level
= texture
->last_level
;
1197 resource
.nr_samples
= texture
->nr_samples
;
1198 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1199 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1200 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1203 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1205 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1206 if (*flushed_depth_texture
== NULL
) {
1207 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1211 (*flushed_depth_texture
)->non_disp_tiling
= false;
1216 * Initialize the pipe_resource descriptor to be of the same size as the box,
1217 * which is supposed to hold a subregion of the texture "orig" at the given
1220 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1221 struct pipe_resource
*orig
,
1222 const struct pipe_box
*box
,
1223 unsigned level
, unsigned flags
)
1225 memset(res
, 0, sizeof(*res
));
1226 res
->format
= orig
->format
;
1227 res
->width0
= box
->width
;
1228 res
->height0
= box
->height
;
1230 res
->array_size
= 1;
1231 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1234 /* We must set the correct texture target and dimensions for a 3D box. */
1235 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1236 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1237 res
->array_size
= box
->depth
;
1239 res
->target
= PIPE_TEXTURE_2D
;
1243 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1244 struct r600_texture
*rtex
,
1245 unsigned transfer_usage
,
1246 const struct pipe_box
*box
)
1248 /* r600g doesn't react to dirty_tex_descriptor_counter */
1249 return rscreen
->chip_class
>= SI
&&
1250 !rtex
->resource
.b
.is_shared
&&
1251 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1252 rtex
->resource
.b
.b
.last_level
== 0 &&
1253 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1254 box
->x
, box
->y
, box
->z
,
1255 box
->width
, box
->height
,
1259 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1260 struct r600_texture
*rtex
)
1262 struct r600_common_screen
*rscreen
= rctx
->screen
;
1264 /* There is no point in discarding depth and tiled buffers. */
1265 assert(!rtex
->is_depth
);
1266 assert(rtex
->surface
.is_linear
);
1268 /* Reallocate the buffer in the same pipe_resource. */
1269 r600_alloc_resource(rscreen
, &rtex
->resource
);
1271 /* Initialize the CMASK base address (needed even without CMASK). */
1272 rtex
->cmask
.base_address_reg
=
1273 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1275 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1277 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1280 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1281 struct pipe_resource
*texture
,
1284 const struct pipe_box
*box
,
1285 struct pipe_transfer
**ptransfer
)
1287 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1288 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1289 struct r600_transfer
*trans
;
1290 struct r600_resource
*buf
;
1291 unsigned offset
= 0;
1293 bool use_staging_texture
= false;
1295 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1296 assert(box
->width
&& box
->height
&& box
->depth
);
1298 /* Depth textures use staging unconditionally. */
1299 if (!rtex
->is_depth
) {
1300 /* Degrade the tile mode if we get too many transfers on APUs.
1301 * On dGPUs, the staging texture is always faster.
1302 * Only count uploads that are at least 4x4 pixels large.
1304 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1306 box
->width
>= 4 && box
->height
>= 4 &&
1307 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1308 bool can_invalidate
=
1309 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1312 r600_reallocate_texture_inplace(rctx
, rtex
,
1317 /* Tiled textures need to be converted into a linear texture for CPU
1318 * access. The staging texture is always linear and is placed in GART.
1320 * Reading from VRAM or GTT WC is slow, always use the staging
1321 * texture in this case.
1323 * Use the staging texture for uploads if the underlying BO
1326 if (!rtex
->surface
.is_linear
)
1327 use_staging_texture
= true;
1328 else if (usage
& PIPE_TRANSFER_READ
)
1329 use_staging_texture
=
1330 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1331 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1332 /* Write & linear only: */
1333 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1334 RADEON_USAGE_READWRITE
) ||
1335 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1336 RADEON_USAGE_READWRITE
)) {
1338 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1340 r600_texture_invalidate_storage(rctx
, rtex
);
1342 use_staging_texture
= true;
1346 trans
= CALLOC_STRUCT(r600_transfer
);
1349 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1350 trans
->b
.b
.level
= level
;
1351 trans
->b
.b
.usage
= usage
;
1352 trans
->b
.b
.box
= *box
;
1354 if (rtex
->is_depth
) {
1355 struct r600_texture
*staging_depth
;
1357 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1358 /* MSAA depth buffers need to be converted to single sample buffers.
1360 * Mapping MSAA depth buffers can occur if ReadPixels is called
1361 * with a multisample GLX visual.
1363 * First downsample the depth buffer to a temporary texture,
1364 * then decompress the temporary one to staging.
1366 * Only the region being mapped is transfered.
1368 struct pipe_resource resource
;
1370 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1372 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1373 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1378 if (usage
& PIPE_TRANSFER_READ
) {
1379 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1381 R600_ERR("failed to create a temporary depth texture\n");
1386 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1387 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1388 0, 0, 0, box
->depth
, 0, 0);
1389 pipe_resource_reference(&temp
, NULL
);
1392 /* Just get the strides. */
1393 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1395 &trans
->b
.b
.layer_stride
);
1397 /* XXX: only readback the rectangle which is being mapped? */
1398 /* XXX: when discard is true, no need to read back from depth texture */
1399 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1400 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1405 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1407 box
->z
, box
->z
+ box
->depth
- 1,
1410 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1413 &trans
->b
.b
.layer_stride
);
1416 trans
->staging
= (struct r600_resource
*)staging_depth
;
1417 buf
= trans
->staging
;
1418 } else if (use_staging_texture
) {
1419 struct pipe_resource resource
;
1420 struct r600_texture
*staging
;
1422 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1423 R600_RESOURCE_FLAG_TRANSFER
);
1424 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1425 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1427 /* Create the temporary texture. */
1428 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1430 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1434 trans
->staging
= &staging
->resource
;
1436 /* Just get the strides. */
1437 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1439 &trans
->b
.b
.layer_stride
);
1441 if (usage
& PIPE_TRANSFER_READ
)
1442 r600_copy_to_staging_texture(ctx
, trans
);
1444 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1446 buf
= trans
->staging
;
1448 /* the resource is mapped directly */
1449 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1451 &trans
->b
.b
.layer_stride
);
1452 buf
= &rtex
->resource
;
1455 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1456 r600_resource_reference(&trans
->staging
, NULL
);
1461 *ptransfer
= &trans
->b
.b
;
1462 return map
+ offset
;
1465 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1466 struct pipe_transfer
* transfer
)
1468 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1469 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1470 struct pipe_resource
*texture
= transfer
->resource
;
1471 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1473 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1474 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1475 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1476 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1477 &rtransfer
->staging
->b
.b
, transfer
->level
,
1480 r600_copy_from_staging_texture(ctx
, rtransfer
);
1484 if (rtransfer
->staging
) {
1485 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1486 r600_resource_reference(&rtransfer
->staging
, NULL
);
1489 /* Heuristic for {upload, draw, upload, draw, ..}:
1491 * Flush the gfx IB if we've allocated too much texture storage.
1493 * The idea is that we don't want to build IBs that use too much
1494 * memory and put pressure on the kernel memory manager and we also
1495 * want to make temporary and invalidated buffers go idle ASAP to
1496 * decrease the total memory usage or make them reusable. The memory
1497 * usage will be slightly higher than given here because of the buffer
1498 * cache in the winsys.
1500 * The result is that the kernel memory manager is never a bottleneck.
1502 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1503 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1504 rctx
->num_alloc_tex_transfer_bytes
= 0;
1507 pipe_resource_reference(&transfer
->resource
, NULL
);
1511 static const struct u_resource_vtbl r600_texture_vtbl
=
1513 NULL
, /* get_handle */
1514 r600_texture_destroy
, /* resource_destroy */
1515 r600_texture_transfer_map
, /* transfer_map */
1516 u_default_transfer_flush_region
, /* transfer_flush_region */
1517 r600_texture_transfer_unmap
, /* transfer_unmap */
1520 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1521 struct pipe_resource
*texture
,
1522 const struct pipe_surface
*templ
,
1523 unsigned width0
, unsigned height0
,
1524 unsigned width
, unsigned height
)
1526 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1531 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1532 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1534 pipe_reference_init(&surface
->base
.reference
, 1);
1535 pipe_resource_reference(&surface
->base
.texture
, texture
);
1536 surface
->base
.context
= pipe
;
1537 surface
->base
.format
= templ
->format
;
1538 surface
->base
.width
= width
;
1539 surface
->base
.height
= height
;
1540 surface
->base
.u
= templ
->u
;
1542 surface
->width0
= width0
;
1543 surface
->height0
= height0
;
1545 return &surface
->base
;
1548 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1549 struct pipe_resource
*tex
,
1550 const struct pipe_surface
*templ
)
1552 unsigned level
= templ
->u
.tex
.level
;
1553 unsigned width
= u_minify(tex
->width0
, level
);
1554 unsigned height
= u_minify(tex
->height0
, level
);
1555 unsigned width0
= tex
->width0
;
1556 unsigned height0
= tex
->height0
;
1558 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1559 const struct util_format_description
*tex_desc
1560 = util_format_description(tex
->format
);
1561 const struct util_format_description
*templ_desc
1562 = util_format_description(templ
->format
);
1564 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1566 /* Adjust size of surface if and only if the block width or
1567 * height is changed. */
1568 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1569 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1570 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1571 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1573 width
= nblks_x
* templ_desc
->block
.width
;
1574 height
= nblks_y
* templ_desc
->block
.height
;
1576 width0
= util_format_get_nblocksx(tex
->format
, width0
);
1577 height0
= util_format_get_nblocksy(tex
->format
, height0
);
1581 return r600_create_surface_custom(pipe
, tex
, templ
,
1586 static void r600_surface_destroy(struct pipe_context
*pipe
,
1587 struct pipe_surface
*surface
)
1589 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1590 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1591 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1592 pipe_resource_reference(&surface
->texture
, NULL
);
1596 static void r600_clear_texture(struct pipe_context
*pipe
,
1597 struct pipe_resource
*tex
,
1599 const struct pipe_box
*box
,
1602 struct pipe_screen
*screen
= pipe
->screen
;
1603 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1604 struct pipe_surface tmpl
= {{0}};
1605 struct pipe_surface
*sf
;
1606 const struct util_format_description
*desc
=
1607 util_format_description(tex
->format
);
1609 tmpl
.format
= tex
->format
;
1610 tmpl
.u
.tex
.first_layer
= box
->z
;
1611 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1612 tmpl
.u
.tex
.level
= level
;
1613 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1617 if (rtex
->is_depth
) {
1620 uint8_t stencil
= 0;
1622 /* Depth is always present. */
1623 clear
= PIPE_CLEAR_DEPTH
;
1624 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1626 if (rtex
->surface
.has_stencil
) {
1627 clear
|= PIPE_CLEAR_STENCIL
;
1628 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1631 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1633 box
->width
, box
->height
, false);
1635 union pipe_color_union color
;
1637 /* pipe_color_union requires the full vec4 representation. */
1638 if (util_format_is_pure_uint(tex
->format
))
1639 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1640 else if (util_format_is_pure_sint(tex
->format
))
1641 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1643 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1645 if (screen
->is_format_supported(screen
, tex
->format
,
1647 PIPE_BIND_RENDER_TARGET
)) {
1648 pipe
->clear_render_target(pipe
, sf
, &color
,
1650 box
->width
, box
->height
, false);
1652 /* Software fallback - just for R9G9B9E5_FLOAT */
1653 util_clear_render_target(pipe
, sf
, &color
,
1655 box
->width
, box
->height
);
1658 pipe_surface_reference(&sf
, NULL
);
1661 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1663 const struct util_format_description
*desc
= util_format_description(format
);
1665 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1667 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1668 return V_0280A0_SWAP_STD
;
1670 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1673 switch (desc
->nr_channels
) {
1675 if (HAS_SWIZZLE(0,X
))
1676 return V_0280A0_SWAP_STD
; /* X___ */
1677 else if (HAS_SWIZZLE(3,X
))
1678 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1681 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1682 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1683 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1684 return V_0280A0_SWAP_STD
; /* XY__ */
1685 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1686 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1687 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1689 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1690 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1691 return V_0280A0_SWAP_ALT
; /* X__Y */
1692 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1693 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1696 if (HAS_SWIZZLE(0,X
))
1697 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1698 else if (HAS_SWIZZLE(0,Z
))
1699 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1702 /* check the middle channels, the 1st and 4th channel can be NONE */
1703 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1704 return V_0280A0_SWAP_STD
; /* XYZW */
1705 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1706 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1707 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1708 return V_0280A0_SWAP_ALT
; /* ZYXW */
1709 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1712 return V_0280A0_SWAP_ALT_REV
;
1714 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1721 /* FAST COLOR CLEAR */
1723 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
1724 enum pipe_format surface_format
,
1725 const union pipe_color_union
*color
)
1727 union util_color uc
;
1729 memset(&uc
, 0, sizeof(uc
));
1731 if (rtex
->surface
.bpe
== 16) {
1732 /* DCC fast clear only:
1733 * CLEAR_WORD0 = R = G = B
1736 assert(color
->ui
[0] == color
->ui
[1] &&
1737 color
->ui
[0] == color
->ui
[2]);
1738 uc
.ui
[0] = color
->ui
[0];
1739 uc
.ui
[1] = color
->ui
[3];
1740 } else if (util_format_is_pure_uint(surface_format
)) {
1741 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
1742 } else if (util_format_is_pure_sint(surface_format
)) {
1743 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
1745 util_pack_color(color
->f
, surface_format
, &uc
);
1748 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
1751 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
1752 struct pipe_framebuffer_state
*fb
,
1753 struct r600_atom
*fb_state
,
1754 unsigned *buffers
, ubyte
*dirty_cbufs
,
1755 const union pipe_color_union
*color
)
1759 /* This function is broken in BE, so just disable this path for now */
1760 #ifdef PIPE_ARCH_BIG_ENDIAN
1764 if (rctx
->render_cond
)
1767 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1768 struct r600_texture
*tex
;
1769 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
1774 /* if this colorbuffer is not being cleared */
1775 if (!(*buffers
& clear_bit
))
1778 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
1780 /* the clear is allowed if all layers are bound */
1781 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
1782 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
1786 /* cannot clear mipmapped textures */
1787 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
1791 /* only supported on tiled surfaces */
1792 if (tex
->surface
.is_linear
) {
1796 /* shared textures can't use fast clear without an explicit flush,
1797 * because there is no way to communicate the clear color among
1800 if (tex
->resource
.b
.is_shared
&&
1801 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
1805 /* 128-bit formats are unusupported */
1806 if (tex
->surface
.bpe
> 8) {
1810 /* ensure CMASK is enabled */
1811 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
1812 if (tex
->cmask
.size
== 0) {
1816 /* Do the fast clear. */
1817 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
1818 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
1819 R600_COHERENCY_CB_META
);
1821 bool need_compressed_update
= !tex
->dirty_level_mask
;
1823 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
1825 if (need_compressed_update
)
1826 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
1829 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
1832 *dirty_cbufs
|= 1 << i
;
1833 rctx
->set_atom_dirty(rctx
, fb_state
, true);
1834 *buffers
&= ~clear_bit
;
1838 static struct pipe_memory_object
*
1839 r600_memobj_from_handle(struct pipe_screen
*screen
,
1840 struct winsys_handle
*whandle
,
1843 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1844 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
1845 struct pb_buffer
*buf
= NULL
;
1846 uint32_t stride
, offset
;
1851 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
,
1858 memobj
->b
.dedicated
= dedicated
;
1860 memobj
->stride
= stride
;
1861 memobj
->offset
= offset
;
1863 return (struct pipe_memory_object
*)memobj
;
1868 r600_memobj_destroy(struct pipe_screen
*screen
,
1869 struct pipe_memory_object
*_memobj
)
1871 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
1873 pb_reference(&memobj
->buf
, NULL
);
1877 static struct pipe_resource
*
1878 r600_texture_from_memobj(struct pipe_screen
*screen
,
1879 const struct pipe_resource
*templ
,
1880 struct pipe_memory_object
*_memobj
,
1884 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1885 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
1886 struct r600_texture
*rtex
;
1887 struct radeon_surf surface
= {};
1888 struct radeon_bo_metadata metadata
= {};
1889 enum radeon_surf_mode array_mode
;
1891 struct pb_buffer
*buf
= NULL
;
1893 if (memobj
->b
.dedicated
) {
1894 rscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
1895 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
1896 &array_mode
, &is_scanout
);
1899 * The bo metadata is unset for un-dedicated images. So we fall
1900 * back to linear. See answer to question 5 of the
1901 * VK_KHX_external_memory spec for some details.
1903 * It is possible that this case isn't going to work if the
1904 * surface pitch isn't correctly aligned by default.
1906 * In order to support it correctly we require multi-image
1907 * metadata to be syncrhonized between radv and radeonsi. The
1908 * semantics of associating multiple image metadata to a memory
1909 * object on the vulkan export side are not concretely defined
1912 * All the use cases we are aware of at the moment for memory
1913 * objects use dedicated allocations. So lets keep the initial
1914 * implementation simple.
1916 * A possible alternative is to attempt to reconstruct the
1917 * tiling information when the TexParameter TEXTURE_TILING_EXT
1920 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1925 r
= r600_init_surface(rscreen
, &surface
, templ
,
1926 array_mode
, memobj
->stride
,
1927 offset
, true, is_scanout
,
1932 rtex
= r600_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
1936 /* r600_texture_create_object doesn't increment refcount of
1937 * memobj->buf, so increment it here.
1939 pb_reference(&buf
, memobj
->buf
);
1941 rtex
->resource
.b
.is_shared
= true;
1942 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
1944 if (rscreen
->apply_opaque_metadata
)
1945 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1947 return &rtex
->resource
.b
.b
;
1950 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
1952 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
1953 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
1954 rscreen
->b
.resource_from_memobj
= r600_texture_from_memobj
;
1955 rscreen
->b
.memobj_create_from_handle
= r600_memobj_from_handle
;
1956 rscreen
->b
.memobj_destroy
= r600_memobj_destroy
;
1959 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
1961 rctx
->b
.create_surface
= r600_create_surface
;
1962 rctx
->b
.surface_destroy
= r600_surface_destroy
;
1963 rctx
->b
.clear_texture
= r600_clear_texture
;