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r600g: add assertions to prevent creation of invalid surfaces
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include <errno.h>
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33
34
35 /* Copy from a full GPU texture to a transfer's staging one. */
36 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
37 {
38 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
39 struct pipe_resource *dst = &rtransfer->staging->b.b;
40 struct pipe_resource *src = transfer->resource;
41
42 if (src->nr_samples <= 1) {
43 ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
44 src, transfer->level, &transfer->box);
45 } else {
46 /* Resolve the resource. */
47 struct pipe_blit_info blit;
48
49 memset(&blit, 0, sizeof(blit));
50 blit.src.resource = src;
51 blit.src.format = src->format;
52 blit.src.level = transfer->level;
53 blit.src.box = transfer->box;
54 blit.dst.resource = dst;
55 blit.dst.format = dst->format;
56 blit.dst.box.width = transfer->box.width;
57 blit.dst.box.height = transfer->box.height;
58 blit.dst.box.depth = transfer->box.depth;
59 blit.mask = PIPE_MASK_RGBA;
60 blit.filter = PIPE_TEX_FILTER_NEAREST;
61
62 ctx->blit(ctx, &blit);
63 }
64 }
65
66 /* Copy from a transfer's staging texture to a full GPU one. */
67 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
68 {
69 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
70 struct pipe_resource *texture = transfer->resource;
71 struct pipe_box sbox;
72
73 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
74
75 ctx->resource_copy_region(ctx, texture, transfer->level,
76 transfer->box.x, transfer->box.y, transfer->box.z,
77 &rtransfer->staging->b.b,
78 0, &sbox);
79 }
80
81 unsigned r600_texture_get_offset(struct r600_texture *rtex,
82 unsigned level, unsigned layer)
83 {
84 return rtex->surface.level[level].offset +
85 layer * rtex->surface.level[level].slice_size;
86 }
87
88 static int r600_init_surface(struct r600_screen *rscreen,
89 struct radeon_surface *surface,
90 const struct pipe_resource *ptex,
91 unsigned array_mode,
92 bool is_flushed_depth)
93 {
94 const struct util_format_description *desc =
95 util_format_description(ptex->format);
96 bool is_depth, is_stencil;
97
98 is_depth = util_format_has_depth(desc);
99 is_stencil = util_format_has_stencil(desc);
100
101 surface->npix_x = ptex->width0;
102 surface->npix_y = ptex->height0;
103 surface->npix_z = ptex->depth0;
104 surface->blk_w = util_format_get_blockwidth(ptex->format);
105 surface->blk_h = util_format_get_blockheight(ptex->format);
106 surface->blk_d = 1;
107 surface->array_size = 1;
108 surface->last_level = ptex->last_level;
109
110 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
111 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
112 surface->bpe = 4; /* stencil is allocated separately on evergreen */
113 } else {
114 surface->bpe = util_format_get_blocksize(ptex->format);
115 /* align byte per element on dword */
116 if (surface->bpe == 3) {
117 surface->bpe = 4;
118 }
119 }
120
121 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
122 surface->flags = 0;
123
124 switch (array_mode) {
125 case V_038000_ARRAY_1D_TILED_THIN1:
126 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
127 break;
128 case V_038000_ARRAY_2D_TILED_THIN1:
129 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
130 break;
131 case V_038000_ARRAY_LINEAR_ALIGNED:
132 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
133 break;
134 case V_038000_ARRAY_LINEAR_GENERAL:
135 default:
136 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
137 break;
138 }
139 switch (ptex->target) {
140 case PIPE_TEXTURE_1D:
141 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
142 break;
143 case PIPE_TEXTURE_RECT:
144 case PIPE_TEXTURE_2D:
145 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
146 break;
147 case PIPE_TEXTURE_3D:
148 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
149 break;
150 case PIPE_TEXTURE_1D_ARRAY:
151 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
152 surface->array_size = ptex->array_size;
153 break;
154 case PIPE_TEXTURE_2D_ARRAY:
155 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d layout for now */
156 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
157 surface->array_size = ptex->array_size;
158 break;
159 case PIPE_TEXTURE_CUBE:
160 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
161 break;
162 case PIPE_BUFFER:
163 default:
164 return -EINVAL;
165 }
166 if (ptex->bind & PIPE_BIND_SCANOUT) {
167 surface->flags |= RADEON_SURF_SCANOUT;
168 }
169
170 if (!is_flushed_depth && is_depth) {
171 surface->flags |= RADEON_SURF_ZBUFFER;
172
173 if (is_stencil) {
174 surface->flags |= RADEON_SURF_SBUFFER |
175 RADEON_SURF_HAS_SBUFFER_MIPTREE;
176 }
177 }
178 return 0;
179 }
180
181 static int r600_setup_surface(struct pipe_screen *screen,
182 struct r600_texture *rtex,
183 unsigned pitch_in_bytes_override)
184 {
185 struct pipe_resource *ptex = &rtex->resource.b.b;
186 struct r600_screen *rscreen = (struct r600_screen*)screen;
187 unsigned i;
188 int r;
189
190 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
191 if (r) {
192 return r;
193 }
194 rtex->size = rtex->surface.bo_size;
195 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
196 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
197 * for those
198 */
199 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
200 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
201 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
202 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
203 rtex->surface.stencil_offset =
204 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
205 }
206 }
207 for (i = 0; i <= ptex->last_level; i++) {
208 switch (rtex->surface.level[i].mode) {
209 case RADEON_SURF_MODE_LINEAR_ALIGNED:
210 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
211 break;
212 case RADEON_SURF_MODE_1D:
213 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
214 break;
215 case RADEON_SURF_MODE_2D:
216 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
217 break;
218 default:
219 case RADEON_SURF_MODE_LINEAR:
220 rtex->array_mode[i] = 0;
221 break;
222 }
223 }
224 return 0;
225 }
226
227 static boolean r600_texture_get_handle(struct pipe_screen* screen,
228 struct pipe_resource *ptex,
229 struct winsys_handle *whandle)
230 {
231 struct r600_texture *rtex = (struct r600_texture*)ptex;
232 struct r600_resource *resource = &rtex->resource;
233 struct radeon_surface *surface = &rtex->surface;
234 struct r600_screen *rscreen = (struct r600_screen*)screen;
235
236 rscreen->ws->buffer_set_tiling(resource->buf,
237 NULL,
238 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
239 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
240 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
241 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
242 surface->bankw, surface->bankh,
243 surface->tile_split,
244 surface->stencil_tile_split,
245 surface->mtilea,
246 rtex->surface.level[0].pitch_bytes);
247
248 return rscreen->ws->buffer_get_handle(resource->buf,
249 rtex->surface.level[0].pitch_bytes, whandle);
250 }
251
252 static void r600_texture_destroy(struct pipe_screen *screen,
253 struct pipe_resource *ptex)
254 {
255 struct r600_texture *rtex = (struct r600_texture*)ptex;
256 struct r600_resource *resource = &rtex->resource;
257
258 if (rtex->flushed_depth_texture)
259 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
260
261 pb_reference(&resource->buf, NULL);
262 FREE(rtex);
263 }
264
265 static const struct u_resource_vtbl r600_texture_vtbl;
266
267 /* The number of samples can be specified independently of the texture. */
268 void r600_texture_get_fmask_info(struct r600_screen *rscreen,
269 struct r600_texture *rtex,
270 unsigned nr_samples,
271 struct r600_fmask_info *out)
272 {
273 /* FMASK is allocated pretty much like an ordinary texture.
274 * Here we use bpe in the units of bits, not bytes. */
275 struct radeon_surface fmask = rtex->surface;
276
277 switch (nr_samples) {
278 case 2:
279 /* This should be 8,1, but we should set nsamples > 1
280 * for the allocator to treat it as a multisample surface.
281 * Let's set 4,2 then. */
282 case 4:
283 fmask.bpe = 4;
284 fmask.nsamples = 2;
285 break;
286 case 8:
287 fmask.bpe = 8;
288 fmask.nsamples = 4;
289 break;
290 case 16:
291 fmask.bpe = 16;
292 fmask.nsamples = 4;
293 break;
294 default:
295 R600_ERR("Invalid sample count for FMASK allocation.\n");
296 return;
297 }
298
299 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
300 if (rscreen->chip_class <= R700) {
301 fmask.bpe *= 2;
302 }
303
304 if (rscreen->chip_class >= EVERGREEN) {
305 fmask.bankh = nr_samples <= 4 ? 4 : 1;
306 }
307
308 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
309 R600_ERR("Got error in surface_init while allocating FMASK.\n");
310 return;
311 }
312 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
313
314 out->bank_height = fmask.bankh;
315 out->alignment = MAX2(256, fmask.bo_alignment);
316 out->size = (fmask.bo_size + 7) / 8;
317 }
318
319 static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
320 struct r600_texture *rtex)
321 {
322 struct r600_fmask_info fmask;
323
324 r600_texture_get_fmask_info(rscreen, rtex,
325 rtex->resource.b.b.nr_samples, &fmask);
326
327 /* Reserve space for FMASK while converting bits back to bytes. */
328 rtex->fmask_bank_height = fmask.bank_height;
329 rtex->fmask_offset = align(rtex->size, fmask.alignment);
330 rtex->fmask_size = fmask.size;
331 rtex->size = rtex->fmask_offset + rtex->fmask_size;
332 #if 0
333 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
334 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
335 #endif
336 }
337
338 void r600_texture_get_cmask_info(struct r600_screen *rscreen,
339 struct r600_texture *rtex,
340 struct r600_cmask_info *out)
341 {
342 unsigned cmask_tile_width = 8;
343 unsigned cmask_tile_height = 8;
344 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
345 unsigned element_bits = 4;
346 unsigned cmask_cache_bits = 1024;
347 unsigned num_pipes = rscreen->tiling_info.num_channels;
348 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
349
350 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
351 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
352 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
353 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
354 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
355
356 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
357 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
358
359 unsigned base_align = num_pipes * pipe_interleave_bytes;
360 unsigned slice_bytes =
361 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
362
363 assert(macro_tile_width % 128 == 0);
364 assert(macro_tile_height % 128 == 0);
365
366 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
367 out->alignment = MAX2(256, base_align);
368 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
369 }
370
371 static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
372 struct r600_texture *rtex)
373 {
374 struct r600_cmask_info cmask;
375
376 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
377
378 rtex->cmask_slice_tile_max = cmask.slice_tile_max;
379 rtex->cmask_offset = align(rtex->size, cmask.alignment);
380 rtex->cmask_size = cmask.size;
381 rtex->size = rtex->cmask_offset + rtex->cmask_size;
382 #if 0
383 printf("CMASK: macro tile width = %u, macro tile height = %u, "
384 "pitch elements = %u, height = %u, slice tile max = %u\n",
385 macro_tile_width, macro_tile_height, pitch_elements, height,
386 rtex->cmask_slice_tile_max);
387 #endif
388 }
389
390 DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "R600_PRINT_TEXDEPTH", FALSE);
391
392 static struct r600_texture *
393 r600_texture_create_object(struct pipe_screen *screen,
394 const struct pipe_resource *base,
395 unsigned pitch_in_bytes_override,
396 struct pb_buffer *buf,
397 boolean alloc_bo,
398 struct radeon_surface *surface)
399 {
400 struct r600_texture *rtex;
401 struct r600_resource *resource;
402 struct r600_screen *rscreen = (struct r600_screen*)screen;
403 int r;
404
405 rtex = CALLOC_STRUCT(r600_texture);
406 if (rtex == NULL)
407 return NULL;
408
409 resource = &rtex->resource;
410 resource->b.b = *base;
411 resource->b.vtbl = &r600_texture_vtbl;
412 pipe_reference_init(&resource->b.b.reference, 1);
413 resource->b.b.screen = screen;
414 rtex->pitch_override = pitch_in_bytes_override;
415
416 /* don't include stencil-only formats which we don't support for rendering */
417 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
418
419 rtex->surface = *surface;
420 r = r600_setup_surface(screen, rtex,
421 pitch_in_bytes_override);
422 if (r) {
423 FREE(rtex);
424 return NULL;
425 }
426
427 if (base->nr_samples > 1 && !rtex->is_depth && alloc_bo) {
428 r600_texture_allocate_cmask(rscreen, rtex);
429 r600_texture_allocate_fmask(rscreen, rtex);
430 }
431
432 if (!rtex->is_depth && base->nr_samples > 1 &&
433 (!rtex->fmask_size || !rtex->cmask_size)) {
434 FREE(rtex);
435 return NULL;
436 }
437
438 /* Tiled depth textures utilize the non-displayable tile order. */
439 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
440
441 /* Now create the backing buffer. */
442 if (!buf && alloc_bo) {
443 unsigned base_align = rtex->surface.bo_alignment;
444 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
445
446 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
447 FREE(rtex);
448 return NULL;
449 }
450 } else if (buf) {
451 /* This is usually the window framebuffer. We want it in VRAM, always. */
452 resource->buf = buf;
453 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
454 resource->domains = RADEON_DOMAIN_VRAM;
455 }
456
457 if (rtex->cmask_size) {
458 /* Initialize the cmask to 0xCC (= compressed state). */
459 char *ptr = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE);
460 memset(ptr + rtex->cmask_offset, 0xCC, rtex->cmask_size);
461 rscreen->ws->buffer_unmap(resource->cs_buf);
462 }
463
464 if (debug_get_option_print_texdepth() && rtex->is_depth && rtex->non_disp_tiling) {
465 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
466 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
467 "bpe=%u, nsamples=%u, flags=%u\n",
468 rtex->surface.npix_x, rtex->surface.npix_y,
469 rtex->surface.npix_z, rtex->surface.blk_w,
470 rtex->surface.blk_h, rtex->surface.blk_d,
471 rtex->surface.array_size, rtex->surface.last_level,
472 rtex->surface.bpe, rtex->surface.nsamples,
473 rtex->surface.flags);
474 if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
475 for (int i = 0; i <= rtex->surface.last_level; i++) {
476 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
477 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
478 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
479 i, (unsigned long long)rtex->surface.level[i].offset,
480 (unsigned long long)rtex->surface.level[i].slice_size,
481 rtex->surface.level[i].npix_x,
482 rtex->surface.level[i].npix_y,
483 rtex->surface.level[i].npix_z,
484 rtex->surface.level[i].nblk_x,
485 rtex->surface.level[i].nblk_y,
486 rtex->surface.level[i].nblk_z,
487 rtex->surface.level[i].pitch_bytes,
488 rtex->surface.level[i].mode);
489 }
490 }
491 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
492 for (int i = 0; i <= rtex->surface.last_level; i++) {
493 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
494 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
495 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
496 i, (unsigned long long)rtex->surface.stencil_level[i].offset,
497 (unsigned long long)rtex->surface.stencil_level[i].slice_size,
498 rtex->surface.stencil_level[i].npix_x,
499 rtex->surface.stencil_level[i].npix_y,
500 rtex->surface.stencil_level[i].npix_z,
501 rtex->surface.stencil_level[i].nblk_x,
502 rtex->surface.stencil_level[i].nblk_y,
503 rtex->surface.stencil_level[i].nblk_z,
504 rtex->surface.stencil_level[i].pitch_bytes,
505 rtex->surface.stencil_level[i].mode);
506 }
507 }
508 }
509 return rtex;
510 }
511
512 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
513 const struct pipe_resource *templ)
514 {
515 struct r600_screen *rscreen = (struct r600_screen*)screen;
516 struct radeon_surface surface;
517 const struct util_format_description *desc = util_format_description(templ->format);
518 unsigned array_mode;
519 int r;
520
521 /* Default tiling mode for staging textures. */
522 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
523
524 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
525 * because 422 formats are used for videos, which prefer linear buffers
526 * for fast uploads anyway. */
527 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
528 desc->layout != UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
529 if (!(templ->bind & PIPE_BIND_SCANOUT) &&
530 templ->usage != PIPE_USAGE_STAGING &&
531 templ->usage != PIPE_USAGE_STREAM &&
532 templ->target != PIPE_TEXTURE_1D &&
533 templ->target != PIPE_TEXTURE_1D_ARRAY &&
534 templ->height0 > 3) {
535 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
536 } else if (util_format_is_compressed(templ->format)) {
537 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
538 }
539 }
540
541 r = r600_init_surface(rscreen, &surface, templ, array_mode,
542 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
543 if (r) {
544 return NULL;
545 }
546 r = rscreen->ws->surface_best(rscreen->ws, &surface);
547 if (r) {
548 return NULL;
549 }
550 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
551 0, NULL, TRUE, &surface);
552 }
553
554 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
555 struct pipe_resource *texture,
556 const struct pipe_surface *templ,
557 unsigned width, unsigned height)
558 {
559 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
560
561 assert(templ->u.tex.first_layer <= u_max_layer(texture, templ->u.tex.level));
562 assert(templ->u.tex.last_layer <= u_max_layer(texture, templ->u.tex.level));
563 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
564 if (surface == NULL)
565 return NULL;
566 pipe_reference_init(&surface->base.reference, 1);
567 pipe_resource_reference(&surface->base.texture, texture);
568 surface->base.context = pipe;
569 surface->base.format = templ->format;
570 surface->base.width = width;
571 surface->base.height = height;
572 surface->base.u = templ->u;
573 return &surface->base;
574 }
575
576 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
577 struct pipe_resource *texture,
578 const struct pipe_surface *templ)
579 {
580 struct r600_texture *rtex = (struct r600_texture*)texture;
581 unsigned level = templ->u.tex.level;
582
583 return r600_create_surface_custom(pipe, texture, templ,
584 rtex->surface.level[level].npix_x,
585 rtex->surface.level[level].npix_y);
586 }
587
588 static void r600_surface_destroy(struct pipe_context *pipe,
589 struct pipe_surface *surface)
590 {
591 struct r600_surface *surf = (struct r600_surface*)surface;
592 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
593 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
594 pipe_resource_reference(&surface->texture, NULL);
595 FREE(surface);
596 }
597
598 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
599 const struct pipe_resource *templ,
600 struct winsys_handle *whandle)
601 {
602 struct r600_screen *rscreen = (struct r600_screen*)screen;
603 struct pb_buffer *buf = NULL;
604 unsigned stride = 0;
605 unsigned array_mode = 0;
606 enum radeon_bo_layout micro, macro;
607 struct radeon_surface surface;
608 int r;
609
610 /* Support only 2D textures without mipmaps */
611 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
612 templ->depth0 != 1 || templ->last_level != 0)
613 return NULL;
614
615 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
616 if (!buf)
617 return NULL;
618
619 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
620 &surface.bankw, &surface.bankh,
621 &surface.tile_split,
622 &surface.stencil_tile_split,
623 &surface.mtilea);
624
625 if (macro == RADEON_LAYOUT_TILED)
626 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
627 else if (micro == RADEON_LAYOUT_TILED)
628 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
629 else
630 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
631
632 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
633 if (r) {
634 return NULL;
635 }
636 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
637 stride, buf, FALSE, &surface);
638 }
639
640 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
641 struct pipe_resource *texture,
642 struct r600_texture **staging)
643 {
644 struct r600_texture *rtex = (struct r600_texture*)texture;
645 struct pipe_resource resource;
646 struct r600_texture **flushed_depth_texture = staging ?
647 staging : &rtex->flushed_depth_texture;
648
649 if (!staging && rtex->flushed_depth_texture)
650 return true; /* it's ready */
651
652 resource.target = texture->target;
653 resource.format = texture->format;
654 resource.width0 = texture->width0;
655 resource.height0 = texture->height0;
656 resource.depth0 = texture->depth0;
657 resource.array_size = texture->array_size;
658 resource.last_level = texture->last_level;
659 resource.nr_samples = texture->nr_samples;
660 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
661 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
662 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
663
664 if (staging)
665 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
666
667 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
668 if (*flushed_depth_texture == NULL) {
669 R600_ERR("failed to create temporary texture to hold flushed depth\n");
670 return false;
671 }
672
673 (*flushed_depth_texture)->is_flushing_texture = TRUE;
674 (*flushed_depth_texture)->non_disp_tiling = false;
675 return true;
676 }
677
678 static void *r600_texture_transfer_map(struct pipe_context *ctx,
679 struct pipe_resource *texture,
680 unsigned level,
681 unsigned usage,
682 const struct pipe_box *box,
683 struct pipe_transfer **ptransfer)
684 {
685 struct r600_context *rctx = (struct r600_context*)ctx;
686 struct r600_texture *rtex = (struct r600_texture*)texture;
687 struct pipe_resource resource;
688 struct r600_transfer *trans;
689 boolean use_staging_texture = FALSE;
690 enum pipe_format format = texture->format;
691 struct radeon_winsys_cs_handle *buf;
692 unsigned offset = 0;
693 char *map;
694
695 if ((texture->bind & PIPE_BIND_GLOBAL) && texture->target == PIPE_BUFFER) {
696 return r600_compute_global_transfer_map(ctx, texture, level, usage, box, ptransfer);
697 }
698
699 /* We cannot map a tiled texture directly because the data is
700 * in a different order, therefore we do detiling using a blit.
701 *
702 * Also, use a temporary in GTT memory for read transfers, as
703 * the CPU is much happier reading out of cached system memory
704 * than uncached VRAM.
705 */
706 if (R600_TEX_IS_TILED(rtex, level)) {
707 use_staging_texture = TRUE;
708 }
709
710 /* Use a staging texture for uploads if the underlying BO is busy. */
711 if (!(usage & PIPE_TRANSFER_READ) &&
712 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
713 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
714 use_staging_texture = TRUE;
715 }
716
717 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
718 use_staging_texture = FALSE;
719 }
720
721 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
722 return NULL;
723 }
724
725 trans = CALLOC_STRUCT(r600_transfer);
726 if (trans == NULL)
727 return NULL;
728 trans->transfer.resource = texture;
729 trans->transfer.level = level;
730 trans->transfer.usage = usage;
731 trans->transfer.box = *box;
732 if (rtex->is_depth) {
733 /* XXX: only readback the rectangle which is being mapped?
734 */
735 /* XXX: when discard is true, no need to read back from depth texture
736 */
737 struct r600_texture *staging_depth;
738
739 assert(rtex->resource.b.b.nr_samples <= 1);
740 if (rtex->resource.b.b.nr_samples > 1) {
741 R600_ERR("mapping MSAA zbuffer unimplemented\n");
742 FREE(trans);
743 return NULL;
744 }
745
746 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
747 R600_ERR("failed to create temporary texture to hold untiled copy\n");
748 FREE(trans);
749 return NULL;
750 }
751
752 r600_blit_decompress_depth(ctx, rtex, staging_depth,
753 level, level,
754 box->z, box->z + box->depth - 1,
755 0, 0);
756
757 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
758 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
759 trans->staging = (struct r600_resource*)staging_depth;
760 } else if (use_staging_texture) {
761 resource.target = PIPE_TEXTURE_2D;
762 resource.format = texture->format;
763 resource.width0 = box->width;
764 resource.height0 = box->height;
765 resource.depth0 = 1;
766 resource.array_size = 1;
767 resource.last_level = 0;
768 resource.nr_samples = 0;
769 resource.usage = PIPE_USAGE_STAGING;
770 resource.bind = 0;
771 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
772 /* For texture reading, the temporary (detiled) texture is used as
773 * a render target when blitting from a tiled texture. */
774 if (usage & PIPE_TRANSFER_READ) {
775 resource.bind |= PIPE_BIND_RENDER_TARGET;
776 }
777 /* For texture writing, the temporary texture is used as a sampler
778 * when blitting into a tiled texture. */
779 if (usage & PIPE_TRANSFER_WRITE) {
780 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
781 }
782 /* Create the temporary texture. */
783 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
784 if (trans->staging == NULL) {
785 R600_ERR("failed to create temporary texture to hold untiled copy\n");
786 FREE(trans);
787 return NULL;
788 }
789
790 trans->transfer.stride =
791 ((struct r600_texture *)trans->staging)->surface.level[0].pitch_bytes;
792 if (usage & PIPE_TRANSFER_READ) {
793 r600_copy_to_staging_texture(ctx, trans);
794 /* Always referenced in the blit. */
795 r600_flush(ctx, NULL, 0);
796 }
797 } else {
798 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
799 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
800 trans->offset = r600_texture_get_offset(rtex, level, box->z);
801 }
802
803 if (trans->staging) {
804 buf = ((struct r600_resource *)trans->staging)->cs_buf;
805 } else {
806 buf = ((struct r600_resource *)texture)->cs_buf;
807 }
808
809 if (rtex->is_depth || !trans->staging)
810 offset = trans->offset +
811 box->y / util_format_get_blockheight(format) * trans->transfer.stride +
812 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
813
814 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) {
815 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
816 FREE(trans);
817 return NULL;
818 }
819
820 *ptransfer = &trans->transfer;
821 return map + offset;
822 }
823
824 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
825 struct pipe_transfer* transfer)
826 {
827 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
828 struct r600_context *rctx = (struct r600_context*)ctx;
829 struct radeon_winsys_cs_handle *buf;
830 struct pipe_resource *texture = transfer->resource;
831 struct r600_texture *rtex = (struct r600_texture*)texture;
832
833 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
834 return r600_compute_global_transfer_unmap(ctx, transfer);
835 }
836
837 if (rtransfer->staging) {
838 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
839 } else {
840 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
841 }
842 rctx->ws->buffer_unmap(buf);
843
844 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
845 if (rtex->is_depth) {
846 ctx->resource_copy_region(ctx, texture, transfer->level,
847 transfer->box.x, transfer->box.y, transfer->box.z,
848 &rtransfer->staging->b.b, transfer->level,
849 &transfer->box);
850 } else {
851 r600_copy_from_staging_texture(ctx, rtransfer);
852 }
853 }
854
855 if (rtransfer->staging)
856 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
857
858 FREE(transfer);
859 }
860
861 void r600_init_surface_functions(struct r600_context *r600)
862 {
863 r600->context.create_surface = r600_create_surface;
864 r600->context.surface_destroy = r600_surface_destroy;
865 }
866
867 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
868 const unsigned char *swizzle_view)
869 {
870 unsigned i;
871 unsigned char swizzle[4];
872 unsigned result = 0;
873 const uint32_t swizzle_shift[4] = {
874 16, 19, 22, 25,
875 };
876 const uint32_t swizzle_bit[4] = {
877 0, 1, 2, 3,
878 };
879
880 if (swizzle_view) {
881 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
882 } else {
883 memcpy(swizzle, swizzle_format, 4);
884 }
885
886 /* Get swizzle. */
887 for (i = 0; i < 4; i++) {
888 switch (swizzle[i]) {
889 case UTIL_FORMAT_SWIZZLE_Y:
890 result |= swizzle_bit[1] << swizzle_shift[i];
891 break;
892 case UTIL_FORMAT_SWIZZLE_Z:
893 result |= swizzle_bit[2] << swizzle_shift[i];
894 break;
895 case UTIL_FORMAT_SWIZZLE_W:
896 result |= swizzle_bit[3] << swizzle_shift[i];
897 break;
898 case UTIL_FORMAT_SWIZZLE_0:
899 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
900 break;
901 case UTIL_FORMAT_SWIZZLE_1:
902 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
903 break;
904 default: /* UTIL_FORMAT_SWIZZLE_X */
905 result |= swizzle_bit[0] << swizzle_shift[i];
906 }
907 }
908 return result;
909 }
910
911 /* texture format translate */
912 uint32_t r600_translate_texformat(struct pipe_screen *screen,
913 enum pipe_format format,
914 const unsigned char *swizzle_view,
915 uint32_t *word4_p, uint32_t *yuv_format_p)
916 {
917 uint32_t result = 0, word4 = 0, yuv_format = 0;
918 const struct util_format_description *desc;
919 boolean uniform = TRUE;
920 static int r600_enable_s3tc = -1;
921 bool is_srgb_valid = FALSE;
922
923 int i;
924 const uint32_t sign_bit[4] = {
925 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
926 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
927 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
928 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
929 };
930 desc = util_format_description(format);
931
932 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
933
934 /* Colorspace (return non-RGB formats directly). */
935 switch (desc->colorspace) {
936 /* Depth stencil formats */
937 case UTIL_FORMAT_COLORSPACE_ZS:
938 switch (format) {
939 case PIPE_FORMAT_Z16_UNORM:
940 result = FMT_16;
941 goto out_word4;
942 case PIPE_FORMAT_X24S8_UINT:
943 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
944 case PIPE_FORMAT_Z24X8_UNORM:
945 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
946 result = FMT_8_24;
947 goto out_word4;
948 case PIPE_FORMAT_S8X24_UINT:
949 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
950 case PIPE_FORMAT_X8Z24_UNORM:
951 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
952 result = FMT_24_8;
953 goto out_word4;
954 case PIPE_FORMAT_S8_UINT:
955 result = FMT_8;
956 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
957 goto out_word4;
958 case PIPE_FORMAT_Z32_FLOAT:
959 result = FMT_32_FLOAT;
960 goto out_word4;
961 case PIPE_FORMAT_X32_S8X24_UINT:
962 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
963 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
964 result = FMT_X24_8_32_FLOAT;
965 goto out_word4;
966 default:
967 goto out_unknown;
968 }
969
970 case UTIL_FORMAT_COLORSPACE_YUV:
971 yuv_format |= (1 << 30);
972 switch (format) {
973 case PIPE_FORMAT_UYVY:
974 case PIPE_FORMAT_YUYV:
975 default:
976 break;
977 }
978 goto out_unknown; /* XXX */
979
980 case UTIL_FORMAT_COLORSPACE_SRGB:
981 word4 |= S_038010_FORCE_DEGAMMA(1);
982 break;
983
984 default:
985 break;
986 }
987
988 if (r600_enable_s3tc == -1) {
989 struct r600_screen *rscreen = (struct r600_screen *)screen;
990 if (rscreen->info.drm_minor >= 9)
991 r600_enable_s3tc = 1;
992 else
993 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
994 }
995
996 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
997 if (!r600_enable_s3tc)
998 goto out_unknown;
999
1000 switch (format) {
1001 case PIPE_FORMAT_RGTC1_SNORM:
1002 case PIPE_FORMAT_LATC1_SNORM:
1003 word4 |= sign_bit[0];
1004 case PIPE_FORMAT_RGTC1_UNORM:
1005 case PIPE_FORMAT_LATC1_UNORM:
1006 result = FMT_BC4;
1007 goto out_word4;
1008 case PIPE_FORMAT_RGTC2_SNORM:
1009 case PIPE_FORMAT_LATC2_SNORM:
1010 word4 |= sign_bit[0] | sign_bit[1];
1011 case PIPE_FORMAT_RGTC2_UNORM:
1012 case PIPE_FORMAT_LATC2_UNORM:
1013 result = FMT_BC5;
1014 goto out_word4;
1015 default:
1016 goto out_unknown;
1017 }
1018 }
1019
1020 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1021
1022 if (!r600_enable_s3tc)
1023 goto out_unknown;
1024
1025 if (!util_format_s3tc_enabled) {
1026 goto out_unknown;
1027 }
1028
1029 switch (format) {
1030 case PIPE_FORMAT_DXT1_RGB:
1031 case PIPE_FORMAT_DXT1_RGBA:
1032 case PIPE_FORMAT_DXT1_SRGB:
1033 case PIPE_FORMAT_DXT1_SRGBA:
1034 result = FMT_BC1;
1035 is_srgb_valid = TRUE;
1036 goto out_word4;
1037 case PIPE_FORMAT_DXT3_RGBA:
1038 case PIPE_FORMAT_DXT3_SRGBA:
1039 result = FMT_BC2;
1040 is_srgb_valid = TRUE;
1041 goto out_word4;
1042 case PIPE_FORMAT_DXT5_RGBA:
1043 case PIPE_FORMAT_DXT5_SRGBA:
1044 result = FMT_BC3;
1045 is_srgb_valid = TRUE;
1046 goto out_word4;
1047 default:
1048 goto out_unknown;
1049 }
1050 }
1051
1052 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1053 switch (format) {
1054 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1055 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1056 result = FMT_GB_GR;
1057 goto out_word4;
1058 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1059 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1060 result = FMT_BG_RG;
1061 goto out_word4;
1062 default:
1063 goto out_unknown;
1064 }
1065 }
1066
1067 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1068 result = FMT_5_9_9_9_SHAREDEXP;
1069 goto out_word4;
1070 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1071 result = FMT_10_11_11_FLOAT;
1072 goto out_word4;
1073 }
1074
1075
1076 for (i = 0; i < desc->nr_channels; i++) {
1077 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1078 word4 |= sign_bit[i];
1079 }
1080 }
1081
1082 /* R8G8Bx_SNORM - XXX CxV8U8 */
1083
1084 /* See whether the components are of the same size. */
1085 for (i = 1; i < desc->nr_channels; i++) {
1086 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1087 }
1088
1089 /* Non-uniform formats. */
1090 if (!uniform) {
1091 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1092 desc->channel[0].pure_integer)
1093 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1094 switch(desc->nr_channels) {
1095 case 3:
1096 if (desc->channel[0].size == 5 &&
1097 desc->channel[1].size == 6 &&
1098 desc->channel[2].size == 5) {
1099 result = FMT_5_6_5;
1100 goto out_word4;
1101 }
1102 goto out_unknown;
1103 case 4:
1104 if (desc->channel[0].size == 5 &&
1105 desc->channel[1].size == 5 &&
1106 desc->channel[2].size == 5 &&
1107 desc->channel[3].size == 1) {
1108 result = FMT_1_5_5_5;
1109 goto out_word4;
1110 }
1111 if (desc->channel[0].size == 10 &&
1112 desc->channel[1].size == 10 &&
1113 desc->channel[2].size == 10 &&
1114 desc->channel[3].size == 2) {
1115 result = FMT_2_10_10_10;
1116 goto out_word4;
1117 }
1118 goto out_unknown;
1119 }
1120 goto out_unknown;
1121 }
1122
1123 /* Find the first non-VOID channel. */
1124 for (i = 0; i < 4; i++) {
1125 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1126 break;
1127 }
1128 }
1129
1130 if (i == 4)
1131 goto out_unknown;
1132
1133 /* uniform formats */
1134 switch (desc->channel[i].type) {
1135 case UTIL_FORMAT_TYPE_UNSIGNED:
1136 case UTIL_FORMAT_TYPE_SIGNED:
1137 #if 0
1138 if (!desc->channel[i].normalized &&
1139 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1140 goto out_unknown;
1141 }
1142 #endif
1143 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1144 desc->channel[i].pure_integer)
1145 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1146
1147 switch (desc->channel[i].size) {
1148 case 4:
1149 switch (desc->nr_channels) {
1150 case 2:
1151 result = FMT_4_4;
1152 goto out_word4;
1153 case 4:
1154 result = FMT_4_4_4_4;
1155 goto out_word4;
1156 }
1157 goto out_unknown;
1158 case 8:
1159 switch (desc->nr_channels) {
1160 case 1:
1161 result = FMT_8;
1162 goto out_word4;
1163 case 2:
1164 result = FMT_8_8;
1165 goto out_word4;
1166 case 4:
1167 result = FMT_8_8_8_8;
1168 is_srgb_valid = TRUE;
1169 goto out_word4;
1170 }
1171 goto out_unknown;
1172 case 16:
1173 switch (desc->nr_channels) {
1174 case 1:
1175 result = FMT_16;
1176 goto out_word4;
1177 case 2:
1178 result = FMT_16_16;
1179 goto out_word4;
1180 case 4:
1181 result = FMT_16_16_16_16;
1182 goto out_word4;
1183 }
1184 goto out_unknown;
1185 case 32:
1186 switch (desc->nr_channels) {
1187 case 1:
1188 result = FMT_32;
1189 goto out_word4;
1190 case 2:
1191 result = FMT_32_32;
1192 goto out_word4;
1193 case 4:
1194 result = FMT_32_32_32_32;
1195 goto out_word4;
1196 }
1197 }
1198 goto out_unknown;
1199
1200 case UTIL_FORMAT_TYPE_FLOAT:
1201 switch (desc->channel[i].size) {
1202 case 16:
1203 switch (desc->nr_channels) {
1204 case 1:
1205 result = FMT_16_FLOAT;
1206 goto out_word4;
1207 case 2:
1208 result = FMT_16_16_FLOAT;
1209 goto out_word4;
1210 case 4:
1211 result = FMT_16_16_16_16_FLOAT;
1212 goto out_word4;
1213 }
1214 goto out_unknown;
1215 case 32:
1216 switch (desc->nr_channels) {
1217 case 1:
1218 result = FMT_32_FLOAT;
1219 goto out_word4;
1220 case 2:
1221 result = FMT_32_32_FLOAT;
1222 goto out_word4;
1223 case 4:
1224 result = FMT_32_32_32_32_FLOAT;
1225 goto out_word4;
1226 }
1227 }
1228 goto out_unknown;
1229 }
1230
1231 out_word4:
1232
1233 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1234 return ~0;
1235 if (word4_p)
1236 *word4_p = word4;
1237 if (yuv_format_p)
1238 *yuv_format_p = yuv_format;
1239 return result;
1240 out_unknown:
1241 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1242 return ~0;
1243 }
1244
1245 static const struct u_resource_vtbl r600_texture_vtbl =
1246 {
1247 r600_texture_get_handle, /* get_handle */
1248 r600_texture_destroy, /* resource_destroy */
1249 r600_texture_transfer_map, /* transfer_map */
1250 NULL, /* transfer_flush_region */
1251 r600_texture_transfer_unmap, /* transfer_unmap */
1252 NULL /* transfer_inline_write */
1253 };