src/gallium/drivers/r600/r600_uvd.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2011 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * Authors:
  30  *      Christian König <christian.koenig@amd.com>
  31  *
  32  */
  33
  34 #include <sys/types.h>
  35 #include <assert.h>
  36 #include <errno.h>
  37 #include <unistd.h>
  38
  39 #include "pipe/p_video_codec.h"
  40
  41 #include "util/u_memory.h"
  42 #include "util/u_video.h"
  43
  44 #include "vl/vl_defines.h"
  45 #include "vl/vl_mpeg12_decoder.h"
  46
  47 #include "r600_pipe.h"
  48 #include "radeon/radeon_video.h"
  49 #include "radeon/radeon_uvd.h"
  50 #include "radeon/radeon_vce.h"
  51 #include "r600d.h"
  52
  53 #define R600_UVD_ENABLE_TILING 0
  54
  55 /**
  56  * creates an video buffer with an UVD compatible memory layout
  57  */
  58 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
  59                                                    const struct pipe_video_buffer *tmpl)
  60 {
  61         struct r600_context *ctx = (struct r600_context *)pipe;
  62         struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
  63         struct radeon_surf* surfaces[VL_NUM_COMPONENTS] = {};
  64         struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
  65         const enum pipe_format *resource_formats;
  66         struct pipe_video_buffer template;
  67         struct pipe_resource templ;
  68         unsigned i, array_size;
  69
  70         assert(pipe);
  71
  72         /* first create the needed resources as "normal" textures */
  73         resource_formats = vl_video_buffer_formats(pipe->screen, tmpl->buffer_format);
  74         if (!resource_formats)
  75                 return NULL;
  76
  77         array_size = tmpl->interlaced ? 2 : 1;
  78         template = *tmpl;
  79         template.width = align(tmpl->width, VL_MACROBLOCK_WIDTH);
  80         template.height = align(tmpl->height / array_size, VL_MACROBLOCK_HEIGHT);
  81
  82         vl_video_buffer_template(&templ, &template, resource_formats[0], 1, array_size, PIPE_USAGE_DEFAULT, 0);
  83         if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced || !R600_UVD_ENABLE_TILING)
  84                 templ.bind = PIPE_BIND_LINEAR;
  85         resources[0] = (struct r600_texture *)
  86                 pipe->screen->resource_create(pipe->screen, &templ);
  87         if (!resources[0])
  88                 goto error;
  89
  90         if (resource_formats[1] != PIPE_FORMAT_NONE) {
  91                 vl_video_buffer_template(&templ, &template, resource_formats[1], 1, array_size, PIPE_USAGE_DEFAULT, 1);
  92                 if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced || !R600_UVD_ENABLE_TILING)
  93                         templ.bind = PIPE_BIND_LINEAR;
  94                 resources[1] = (struct r600_texture *)
  95                         pipe->screen->resource_create(pipe->screen, &templ);
  96                 if (!resources[1])
  97                         goto error;
  98         }
  99
 100         if (resource_formats[2] != PIPE_FORMAT_NONE) {
 101                 vl_video_buffer_template(&templ, &template, resource_formats[2], 1, array_size, PIPE_USAGE_DEFAULT, 2);
 102                 if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced || !R600_UVD_ENABLE_TILING)
 103                         templ.bind = PIPE_BIND_LINEAR;
 104                 resources[2] = (struct r600_texture *)
 105                         pipe->screen->resource_create(pipe->screen, &templ);
 106                 if (!resources[2])
 107                         goto error;
 108         }
 109
 110         for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
 111                 if (!resources[i])
 112                         continue;
 113
 114                 pbs[i] = &resources[i]->resource.buf;
 115                 surfaces[i] = &resources[i]->surface;
 116         }
 117
 118         rvid_join_surfaces(&ctx->b, pbs, surfaces);
 119
 120         for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
 121                 if (!resources[i])
 122                         continue;
 123
 124                 /* reset the address */
 125                 resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address(
 126                         resources[i]->resource.buf);
 127         }
 128
 129         template.height *= array_size;
 130         return vl_video_buffer_create_ex2(pipe, &template, (struct pipe_resource **)resources);
 131
 132 error:
 133         for (i = 0; i < VL_NUM_COMPONENTS; ++i)
 134                 r600_texture_reference(&resources[i], NULL);
 135
 136         return NULL;
 137 }
 138
 139 /* hw encode the number of memory banks */
 140 static uint32_t eg_num_banks(uint32_t nbanks)
 141 {
 142         switch (nbanks) {
 143         case 2:
 144                 return 0;
 145         case 4:
 146                 return 1;
 147         case 8:
 148         default:
 149                 return 2;
 150         case 16:
 151                 return 3;
 152         }
 153 }
 154
 155 /* set the decoding target buffer offsets */
 156 static struct pb_buffer* r600_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
 157 {
 158         struct r600_screen *rscreen = (struct r600_screen*)buf->base.context->screen;
 159         struct r600_texture *luma = (struct r600_texture *)buf->resources[0];
 160         struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
 161
 162         msg->body.decode.dt_field_mode = buf->base.interlaced;
 163         msg->body.decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->b.info.r600_num_banks));
 164
 165         ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface, RUVD_SURFACE_TYPE_LEGACY);
 166
 167         return luma->resource.buf;
 168 }
 169
 170 /* get the radeon resources for VCE */
 171 static void r600_vce_get_buffer(struct pipe_resource *resource,
 172                                 struct pb_buffer **handle,
 173                                 struct radeon_surf **surface)
 174 {
 175         struct r600_texture *res = (struct r600_texture *)resource;
 176
 177         if (handle)
 178                 *handle = res->resource.buf;
 179
 180         if (surface)
 181                 *surface = &res->surface;
 182 }
 183
 184 /* create decoder */
 185 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
 186                                                  const struct pipe_video_codec *templat)
 187 {
 188         struct r600_context *ctx = (struct r600_context *)context;
 189
 190         if (templat->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
 191                 return rvce_create_encoder(context, templat, ctx->b.ws, r600_vce_get_buffer);
 192
 193         return ruvd_create_decoder(context, templat, r600_uvd_set_dtb);
 194 }