r600/uvd: stop advertising MPEG4 on UVD 2.x chips v2
[mesa.git] / src / gallium / drivers / r600 / r600_uvd.c
1 /**************************************************************************
2 *
3 * Copyright 2011 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * Authors:
30 * Christian König <christian.koenig@amd.com>
31 *
32 */
33
34 #include <sys/types.h>
35 #include <assert.h>
36 #include <errno.h>
37 #include <unistd.h>
38
39 #include "pipe/p_video_decoder.h"
40
41 #include "util/u_memory.h"
42 #include "util/u_video.h"
43
44 #include "vl/vl_defines.h"
45 #include "vl/vl_mpeg12_decoder.h"
46
47 #include "r600_pipe.h"
48 #include "radeon/radeon_uvd.h"
49 #include "r600d.h"
50
51 /**
52 * creates an video buffer with an UVD compatible memory layout
53 */
54 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
55 const struct pipe_video_buffer *tmpl)
56 {
57 struct r600_context *ctx = (struct r600_context *)pipe;
58 struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
59 struct radeon_surface* surfaces[VL_NUM_COMPONENTS] = {};
60 struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
61 const enum pipe_format *resource_formats;
62 struct pipe_video_buffer template;
63 struct pipe_resource templ;
64 unsigned i, depth;
65
66 assert(pipe);
67
68 /* first create the needed resources as "normal" textures */
69 resource_formats = vl_video_buffer_formats(pipe->screen, tmpl->buffer_format);
70 if (!resource_formats)
71 return NULL;
72
73 depth = tmpl->interlaced ? 2 : 1;
74 template = *tmpl;
75 template.width = align(tmpl->width, VL_MACROBLOCK_WIDTH);
76 template.height = align(tmpl->height / depth, VL_MACROBLOCK_HEIGHT);
77
78 vl_vide_buffer_template(&templ, &template, resource_formats[0], depth, PIPE_USAGE_STATIC, 0);
79 if (ctx->chip_class < EVERGREEN)
80 templ.flags = R600_RESOURCE_FLAG_TRANSFER;
81 resources[0] = (struct r600_texture *)
82 pipe->screen->resource_create(pipe->screen, &templ);
83 if (!resources[0])
84 goto error;
85
86 if (resource_formats[1] != PIPE_FORMAT_NONE) {
87 vl_vide_buffer_template(&templ, &template, resource_formats[1], depth, PIPE_USAGE_STATIC, 1);
88 if (ctx->chip_class < EVERGREEN)
89 templ.flags = R600_RESOURCE_FLAG_TRANSFER;
90 resources[1] = (struct r600_texture *)
91 pipe->screen->resource_create(pipe->screen, &templ);
92 if (!resources[1])
93 goto error;
94 }
95
96 if (resource_formats[2] != PIPE_FORMAT_NONE) {
97 vl_vide_buffer_template(&templ, &template, resource_formats[2], depth, PIPE_USAGE_STATIC, 2);
98 if (ctx->chip_class < EVERGREEN)
99 templ.flags = R600_RESOURCE_FLAG_TRANSFER;
100 resources[2] = (struct r600_texture *)
101 pipe->screen->resource_create(pipe->screen, &templ);
102 if (!resources[2])
103 goto error;
104 }
105
106 for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
107 if (!resources[i])
108 continue;
109
110 pbs[i] = &resources[i]->resource.buf;
111 surfaces[i] = &resources[i]->surface;
112 }
113
114 ruvd_join_surfaces(ctx->ws, templ.bind, pbs, surfaces);
115
116 for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
117 if (!resources[i])
118 continue;
119
120 /* recreate the CS handle */
121 resources[i]->resource.cs_buf = ctx->ws->buffer_get_cs_handle(
122 resources[i]->resource.buf);
123 }
124
125 template.height *= depth;
126 return vl_video_buffer_create_ex2(pipe, &template, (struct pipe_resource **)resources);
127
128 error:
129 for (i = 0; i < VL_NUM_COMPONENTS; ++i)
130 pipe_resource_reference((struct pipe_resource **)&resources[i], NULL);
131
132 return NULL;
133 }
134
135 /* hw encode the number of memory banks */
136 static uint32_t eg_num_banks(uint32_t nbanks)
137 {
138 switch (nbanks) {
139 case 2:
140 return 0;
141 case 4:
142 return 1;
143 case 8:
144 default:
145 return 2;
146 case 16:
147 return 3;
148 }
149 }
150
151 /* set the decoding target buffer offsets */
152 static struct radeon_winsys_cs_handle* r600_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
153 {
154 struct r600_screen *rscreen = (struct r600_screen*)buf->base.context->screen;
155 struct r600_texture *luma = (struct r600_texture *)buf->resources[0];
156 struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
157
158 msg->body.decode.dt_field_mode = buf->base.interlaced;
159 msg->body.decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->tiling_info.num_banks));
160
161 ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface);
162
163 return luma->resource.cs_buf;
164 }
165
166 /* create decoder */
167 struct pipe_video_decoder *r600_uvd_create_decoder(struct pipe_context *context,
168 enum pipe_video_profile profile,
169 enum pipe_video_entrypoint entrypoint,
170 enum pipe_video_chroma_format chroma_format,
171 unsigned width, unsigned height,
172 unsigned max_references, bool expect_chunked_decode)
173 {
174 struct r600_context *ctx = (struct r600_context *)context;
175
176 return ruvd_create_decoder(context, profile, entrypoint, chroma_format,
177 width, height, max_references, expect_chunked_decode,
178 ctx->ws, r600_uvd_set_dtb);
179 }
180
181 int r600_uvd_get_video_param(struct pipe_screen *screen,
182 enum pipe_video_profile profile,
183 enum pipe_video_cap param)
184 {
185 struct r600_screen *rscreen = (struct r600_screen *)screen;
186
187 /* No support for MPEG4 on UVD 2.x */
188 if (param == PIPE_VIDEO_CAP_SUPPORTED && rscreen->family < CHIP_CEDAR &&
189 u_reduce_video_profile(profile) == PIPE_VIDEO_CODEC_MPEG4)
190 return false;
191
192 return ruvd_get_video_param(screen, profile, param);
193 }