src/gallium/drivers/r600/r600_viewport.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "r600_cs.h"
  25 #include "util/u_viewport.h"
  26 #include "tgsi/tgsi_scan.h"
  27
  28 #define GET_MAX_SCISSOR(rctx) (rctx->chip_class >= EVERGREEN ? 16384 : 8192)
  29
  30 static void r600_set_scissor_states(struct pipe_context *ctx,
  31                                     unsigned start_slot,
  32                                     unsigned num_scissors,
  33                                     const struct pipe_scissor_state *state)
  34 {
  35         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
  36         int i;
  37
  38         for (i = 0; i < num_scissors; i++)
  39                 rctx->scissors.states[start_slot + i] = state[i];
  40
  41         if (!rctx->scissor_enabled)
  42                 return;
  43
  44         rctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
  45         rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
  46 }
  47
  48 /* Since the guard band disables clipping, we have to clip per-pixel
  49  * using a scissor.
  50  */
  51 static void r600_get_scissor_from_viewport(struct r600_common_context *rctx,
  52                                            const struct pipe_viewport_state *vp,
  53                                            struct r600_signed_scissor *scissor)
  54 {
  55         float tmp, minx, miny, maxx, maxy;
  56
  57         /* Convert (-1, -1) and (1, 1) from clip space into window space. */
  58         minx = -vp->scale[0] + vp->translate[0];
  59         miny = -vp->scale[1] + vp->translate[1];
  60         maxx = vp->scale[0] + vp->translate[0];
  61         maxy = vp->scale[1] + vp->translate[1];
  62
  63         /* r600_draw_rectangle sets this. Disable the scissor. */
  64         if (minx == -1 && miny == -1 && maxx == 1 && maxy == 1) {
  65                 scissor->minx = scissor->miny = 0;
  66                 scissor->maxx = scissor->maxy = GET_MAX_SCISSOR(rctx);
  67                 return;
  68         }
  69
  70         /* Handle inverted viewports. */
  71         if (minx > maxx) {
  72                 tmp = minx;
  73                 minx = maxx;
  74                 maxx = tmp;
  75         }
  76         if (miny > maxy) {
  77                 tmp = miny;
  78                 miny = maxy;
  79                 maxy = tmp;
  80         }
  81
  82         /* Convert to integer and round up the max bounds. */
  83         scissor->minx = minx;
  84         scissor->miny = miny;
  85         scissor->maxx = ceilf(maxx);
  86         scissor->maxy = ceilf(maxy);
  87 }
  88
  89 static void r600_clamp_scissor(struct r600_common_context *rctx,
  90                                struct pipe_scissor_state *out,
  91                                struct r600_signed_scissor *scissor)
  92 {
  93         unsigned max_scissor = GET_MAX_SCISSOR(rctx);
  94         out->minx = CLAMP(scissor->minx, 0, max_scissor);
  95         out->miny = CLAMP(scissor->miny, 0, max_scissor);
  96         out->maxx = CLAMP(scissor->maxx, 0, max_scissor);
  97         out->maxy = CLAMP(scissor->maxy, 0, max_scissor);
  98 }
  99
 100 static void r600_clip_scissor(struct pipe_scissor_state *out,
 101                               struct pipe_scissor_state *clip)
 102 {
 103         out->minx = MAX2(out->minx, clip->minx);
 104         out->miny = MAX2(out->miny, clip->miny);
 105         out->maxx = MIN2(out->maxx, clip->maxx);
 106         out->maxy = MIN2(out->maxy, clip->maxy);
 107 }
 108
 109 static void r600_scissor_make_union(struct r600_signed_scissor *out,
 110                                     struct r600_signed_scissor *in)
 111 {
 112         out->minx = MIN2(out->minx, in->minx);
 113         out->miny = MIN2(out->miny, in->miny);
 114         out->maxx = MAX2(out->maxx, in->maxx);
 115         out->maxy = MAX2(out->maxy, in->maxy);
 116 }
 117
 118 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 119                                             struct pipe_scissor_state *scissor)
 120 {
 121         if (rctx->chip_class == EVERGREEN || rctx->chip_class == CAYMAN) {
 122                 if (scissor->maxx == 0)
 123                         scissor->minx = 1;
 124                 if (scissor->maxy == 0)
 125                         scissor->miny = 1;
 126
 127                 if (rctx->chip_class == CAYMAN &&
 128                     scissor->maxx == 1 && scissor->maxy == 1)
 129                         scissor->maxx = 2;
 130         }
 131 }
 132
 133 static void r600_emit_one_scissor(struct r600_common_context *rctx,
 134                                   struct radeon_winsys_cs *cs,
 135                                   struct r600_signed_scissor *vp_scissor,
 136                                   struct pipe_scissor_state *scissor)
 137 {
 138         struct pipe_scissor_state final;
 139
 140         if (rctx->vs_disables_clipping_viewport) {
 141                 final.minx = final.miny = 0;
 142                 final.maxx = final.maxy = GET_MAX_SCISSOR(rctx);
 143         } else {
 144                 r600_clamp_scissor(rctx, &final, vp_scissor);
 145         }
 146
 147         if (scissor)
 148                 r600_clip_scissor(&final, scissor);
 149
 150         evergreen_apply_scissor_bug_workaround(rctx, &final);
 151
 152         radeon_emit(cs, S_028250_TL_X(final.minx) |
 153                         S_028250_TL_Y(final.miny) |
 154                         S_028250_WINDOW_OFFSET_DISABLE(1));
 155         radeon_emit(cs, S_028254_BR_X(final.maxx) |
 156                         S_028254_BR_Y(final.maxy));
 157 }
 158
 159 /* the range is [-MAX, MAX] */
 160 #define GET_MAX_VIEWPORT_RANGE(rctx) (rctx->chip_class >= EVERGREEN ? 32768 : 16384)
 161
 162 static void r600_emit_guardband(struct r600_common_context *rctx,
 163                                 struct r600_signed_scissor *vp_as_scissor)
 164 {
 165         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 166         struct pipe_viewport_state vp;
 167         float left, top, right, bottom, max_range, guardband_x, guardband_y;
 168
 169         /* Reconstruct the viewport transformation from the scissor. */
 170         vp.translate[0] = (vp_as_scissor->minx + vp_as_scissor->maxx) / 2.0;
 171         vp.translate[1] = (vp_as_scissor->miny + vp_as_scissor->maxy) / 2.0;
 172         vp.scale[0] = vp_as_scissor->maxx - vp.translate[0];
 173         vp.scale[1] = vp_as_scissor->maxy - vp.translate[1];
 174
 175         /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
 176         if (vp_as_scissor->minx == vp_as_scissor->maxx)
 177                 vp.scale[0] = 0.5;
 178         if (vp_as_scissor->miny == vp_as_scissor->maxy)
 179                 vp.scale[1] = 0.5;
 180
 181         /* Find the biggest guard band that is inside the supported viewport
 182          * range. The guard band is specified as a horizontal and vertical
 183          * distance from (0,0) in clip space.
 184          *
 185          * This is done by applying the inverse viewport transformation
 186          * on the viewport limits to get those limits in clip space.
 187          *
 188          * Use a limit one pixel smaller to allow for some precision error.
 189          */
 190         max_range = GET_MAX_VIEWPORT_RANGE(rctx) - 1;
 191         left   = (-max_range - vp.translate[0]) / vp.scale[0];
 192         right  = ( max_range - vp.translate[0]) / vp.scale[0];
 193         top    = (-max_range - vp.translate[1]) / vp.scale[1];
 194         bottom = ( max_range - vp.translate[1]) / vp.scale[1];
 195
 196         assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
 197
 198         guardband_x = MIN2(-left, right);
 199         guardband_y = MIN2(-top, bottom);
 200
 201         /* If any of the GB registers is updated, all of them must be updated. */
 202         if (rctx->chip_class >= CAYMAN)
 203                 radeon_set_context_reg_seq(cs, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
 204         else
 205                 radeon_set_context_reg_seq(cs, R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
 206
 207         radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
 208         radeon_emit(cs, fui(1.0));         /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
 209         radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
 210         radeon_emit(cs, fui(1.0));         /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
 211 }
 212
 213 static void r600_emit_scissors(struct r600_common_context *rctx, struct r600_atom *atom)
 214 {
 215         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 216         struct pipe_scissor_state *states = rctx->scissors.states;
 217         unsigned mask = rctx->scissors.dirty_mask;
 218         bool scissor_enabled = rctx->scissor_enabled;
 219         struct r600_signed_scissor max_vp_scissor;
 220         int i;
 221
 222         /* The simple case: Only 1 viewport is active. */
 223         if (!rctx->vs_writes_viewport_index) {
 224                 struct r600_signed_scissor *vp = &rctx->viewports.as_scissor[0];
 225
 226                 if (!(mask & 1))
 227                         return;
 228
 229                 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
 230                 r600_emit_one_scissor(rctx, cs, vp, scissor_enabled ? &states[0] : NULL);
 231                 r600_emit_guardband(rctx, vp);
 232                 rctx->scissors.dirty_mask &= ~1; /* clear one bit */
 233                 return;
 234         }
 235
 236         /* Shaders can draw to any viewport. Make a union of all viewports. */
 237         max_vp_scissor = rctx->viewports.as_scissor[0];
 238         for (i = 1; i < R600_MAX_VIEWPORTS; i++)
 239                 r600_scissor_make_union(&max_vp_scissor,
 240                                       &rctx->viewports.as_scissor[i]);
 241
 242         while (mask) {
 243                 int start, count, i;
 244
 245                 u_bit_scan_consecutive_range(&mask, &start, &count);
 246
 247                 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
 248                                                start * 4 * 2, count * 2);
 249                 for (i = start; i < start+count; i++) {
 250                         r600_emit_one_scissor(rctx, cs, &rctx->viewports.as_scissor[i],
 251                                               scissor_enabled ? &states[i] : NULL);
 252                 }
 253         }
 254         r600_emit_guardband(rctx, &max_vp_scissor);
 255         rctx->scissors.dirty_mask = 0;
 256 }
 257
 258 static void r600_set_viewport_states(struct pipe_context *ctx,
 259                                      unsigned start_slot,
 260                                      unsigned num_viewports,
 261                                      const struct pipe_viewport_state *state)
 262 {
 263         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 264         unsigned mask;
 265         int i;
 266
 267         for (i = 0; i < num_viewports; i++) {
 268                 unsigned index = start_slot + i;
 269
 270                 rctx->viewports.states[index] = state[i];
 271                 r600_get_scissor_from_viewport(rctx, &state[i],
 272                                                &rctx->viewports.as_scissor[index]);
 273         }
 274
 275         mask = ((1 << num_viewports) - 1) << start_slot;
 276         rctx->viewports.dirty_mask |= mask;
 277         rctx->viewports.depth_range_dirty_mask |= mask;
 278         rctx->scissors.dirty_mask |= mask;
 279         rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
 280         rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
 281 }
 282
 283 static void r600_emit_one_viewport(struct r600_common_context *rctx,
 284                                    struct pipe_viewport_state *state)
 285 {
 286         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 287
 288         radeon_emit(cs, fui(state->scale[0]));
 289         radeon_emit(cs, fui(state->translate[0]));
 290         radeon_emit(cs, fui(state->scale[1]));
 291         radeon_emit(cs, fui(state->translate[1]));
 292         radeon_emit(cs, fui(state->scale[2]));
 293         radeon_emit(cs, fui(state->translate[2]));
 294 }
 295
 296 static void r600_emit_viewports(struct r600_common_context *rctx)
 297 {
 298         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 299         struct pipe_viewport_state *states = rctx->viewports.states;
 300         unsigned mask = rctx->viewports.dirty_mask;
 301
 302         /* The simple case: Only 1 viewport is active. */
 303         if (!rctx->vs_writes_viewport_index) {
 304                 if (!(mask & 1))
 305                         return;
 306
 307                 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
 308                 r600_emit_one_viewport(rctx, &states[0]);
 309                 rctx->viewports.dirty_mask &= ~1; /* clear one bit */
 310                 return;
 311         }
 312
 313         while (mask) {
 314                 int start, count, i;
 315
 316                 u_bit_scan_consecutive_range(&mask, &start, &count);
 317
 318                 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
 319                                                start * 4 * 6, count * 6);
 320                 for (i = start; i < start+count; i++)
 321                         r600_emit_one_viewport(rctx, &states[i]);
 322         }
 323         rctx->viewports.dirty_mask = 0;
 324 }
 325
 326 static void r600_emit_depth_ranges(struct r600_common_context *rctx)
 327 {
 328         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 329         struct pipe_viewport_state *states = rctx->viewports.states;
 330         unsigned mask = rctx->viewports.depth_range_dirty_mask;
 331         float zmin, zmax;
 332
 333         /* The simple case: Only 1 viewport is active. */
 334         if (!rctx->vs_writes_viewport_index) {
 335                 if (!(mask & 1))
 336                         return;
 337
 338                 util_viewport_zmin_zmax(&states[0], rctx->clip_halfz, &zmin, &zmax);
 339
 340                 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
 341                 radeon_emit(cs, fui(zmin));
 342                 radeon_emit(cs, fui(zmax));
 343                 rctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
 344                 return;
 345         }
 346
 347         while (mask) {
 348                 int start, count, i;
 349
 350                 u_bit_scan_consecutive_range(&mask, &start, &count);
 351
 352                 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
 353                                            start * 4 * 2, count * 2);
 354                 for (i = start; i < start+count; i++) {
 355                         util_viewport_zmin_zmax(&states[i], rctx->clip_halfz, &zmin, &zmax);
 356                         radeon_emit(cs, fui(zmin));
 357                         radeon_emit(cs, fui(zmax));
 358                 }
 359         }
 360         rctx->viewports.depth_range_dirty_mask = 0;
 361 }
 362
 363 static void r600_emit_viewport_states(struct r600_common_context *rctx,
 364                                       struct r600_atom *atom)
 365 {
 366         r600_emit_viewports(rctx);
 367         r600_emit_depth_ranges(rctx);
 368 }
 369
 370 /* Set viewport dependencies on pipe_rasterizer_state. */
 371 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
 372                                  bool scissor_enable, bool clip_halfz)
 373 {
 374         if (rctx->scissor_enabled != scissor_enable) {
 375                 rctx->scissor_enabled = scissor_enable;
 376                 rctx->scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
 377                 rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
 378         }
 379         if (rctx->clip_halfz != clip_halfz) {
 380                 rctx->clip_halfz = clip_halfz;
 381                 rctx->viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
 382                 rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
 383         }
 384 }
 385
 386 /**
 387  * Normally, we only emit 1 viewport and 1 scissor if no shader is using
 388  * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
 389  * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
 390  * called to emit the rest.
 391  */
 392 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 393                                           struct tgsi_shader_info *info)
 394 {
 395         bool vs_window_space;
 396
 397         if (!info)
 398                 return;
 399
 400         /* When the VS disables clipping and viewport transformation. */
 401         vs_window_space =
 402                 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
 403
 404         if (rctx->vs_disables_clipping_viewport != vs_window_space) {
 405                 rctx->vs_disables_clipping_viewport = vs_window_space;
 406                 rctx->scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
 407                 rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
 408         }
 409
 410         /* Viewport index handling. */
 411         rctx->vs_writes_viewport_index = info->writes_viewport_index;
 412         if (!rctx->vs_writes_viewport_index)
 413                 return;
 414
 415         if (rctx->scissors.dirty_mask)
 416             rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
 417
 418         if (rctx->viewports.dirty_mask ||
 419             rctx->viewports.depth_range_dirty_mask)
 420             rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
 421 }
 422
 423 void r600_init_viewport_functions(struct r600_common_context *rctx)
 424 {
 425         rctx->scissors.atom.emit = r600_emit_scissors;
 426         rctx->viewports.atom.emit = r600_emit_viewport_states;
 427
 428         rctx->scissors.atom.num_dw = (2 + 16 * 2) + 6;
 429         rctx->viewports.atom.num_dw = 2 + 16 * 6;
 430
 431         rctx->b.set_scissor_states = r600_set_scissor_states;
 432         rctx->b.set_viewport_states = r600_set_viewport_states;
 433 }