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3f1ca95f699b9c082c3834c27e1a8bebe79f7e5a
[mesa.git] / src / gallium / drivers / r600 / radeon.h
1 /*
2 * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software Foundation,
15 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
16 */
17 #ifndef RADEON_H
18 #define RADEON_H
19
20 #define RADEON_CTX_MAX_PM4 (64 * 1024 / 4)
21
22 #include <stdint.h>
23
24 typedef uint64_t u64;
25 typedef uint32_t u32;
26 typedef uint16_t u16;
27 typedef uint8_t u8;
28
29 struct radeon;
30
31 enum radeon_family {
32 CHIP_UNKNOWN,
33 CHIP_R100,
34 CHIP_RV100,
35 CHIP_RS100,
36 CHIP_RV200,
37 CHIP_RS200,
38 CHIP_R200,
39 CHIP_RV250,
40 CHIP_RS300,
41 CHIP_RV280,
42 CHIP_R300,
43 CHIP_R350,
44 CHIP_RV350,
45 CHIP_RV380,
46 CHIP_R420,
47 CHIP_R423,
48 CHIP_RV410,
49 CHIP_RS400,
50 CHIP_RS480,
51 CHIP_RS600,
52 CHIP_RS690,
53 CHIP_RS740,
54 CHIP_RV515,
55 CHIP_R520,
56 CHIP_RV530,
57 CHIP_RV560,
58 CHIP_RV570,
59 CHIP_R580,
60 CHIP_R600,
61 CHIP_RV610,
62 CHIP_RV630,
63 CHIP_RV670,
64 CHIP_RV620,
65 CHIP_RV635,
66 CHIP_RS780,
67 CHIP_RS880,
68 CHIP_RV770,
69 CHIP_RV730,
70 CHIP_RV710,
71 CHIP_RV740,
72 CHIP_CEDAR,
73 CHIP_REDWOOD,
74 CHIP_JUNIPER,
75 CHIP_CYPRESS,
76 CHIP_HEMLOCK,
77 CHIP_LAST,
78 };
79
80 enum radeon_family radeon_get_family(struct radeon *rw);
81
82 /*
83 * radeon object functions
84 */
85 struct radeon_bo {
86 unsigned refcount;
87 unsigned handle;
88 unsigned size;
89 unsigned alignment;
90 unsigned map_count;
91 void *data;
92 };
93 struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
94 unsigned size, unsigned alignment, void *ptr);
95 int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
96 void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
97 struct radeon_bo *radeon_bo_incref(struct radeon *radeon, struct radeon_bo *bo);
98 struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo);
99 int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
100
101 struct radeon_stype_info;
102 /*
103 * states functions
104 */
105 struct radeon_state {
106 struct radeon *radeon;
107 unsigned refcount;
108 struct radeon_stype_info *stype;
109 unsigned id;
110 unsigned shader_index;
111 unsigned nstates;
112 u32 states[64];
113 unsigned npm4;
114 unsigned cpm4;
115 u32 pm4_crc;
116 u32 pm4[128];
117 unsigned nbo;
118 struct radeon_bo *bo[4];
119 unsigned nreloc;
120 unsigned reloc_pm4_id[8];
121 unsigned reloc_bo_id[8];
122 u32 placement[8];
123 unsigned bo_dirty[4];
124 };
125
126 struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id);
127 struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 type, u32 id, u32 shader_class);
128 struct radeon_state *radeon_state_incref(struct radeon_state *state);
129 struct radeon_state *radeon_state_decref(struct radeon_state *state);
130 int radeon_state_pm4(struct radeon_state *state);
131 int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type);
132
133 /*
134 * draw functions
135 */
136 struct radeon_draw {
137 unsigned refcount;
138 struct radeon *radeon;
139 unsigned nstate;
140 struct radeon_state **state;
141 unsigned cpm4;
142 };
143
144 struct radeon_draw *radeon_draw(struct radeon *radeon);
145 struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw);
146 struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw);
147 struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw);
148 int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state);
149 int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state);
150 int radeon_draw_check(struct radeon_draw *draw);
151
152 struct radeon_ctx *radeon_ctx(struct radeon *radeon);
153 struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
154 struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
155 int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
156 int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
157 int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
158 int radeon_ctx_pm4(struct radeon_ctx *ctx);
159 int radeon_ctx_submit(struct radeon_ctx *ctx);
160 void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
161
162 /*
163 * radeon context functions
164 */
165 #pragma pack(1)
166 struct radeon_cs_reloc {
167 uint32_t handle;
168 uint32_t read_domain;
169 uint32_t write_domain;
170 uint32_t flags;
171 };
172 #pragma pack()
173
174 struct radeon_ctx {
175 int refcount;
176 struct radeon *radeon;
177 u32 *pm4;
178 u32 cpm4;
179 u32 draw_cpm4;
180 unsigned id;
181 unsigned next_id;
182 unsigned nreloc;
183 struct radeon_cs_reloc *reloc;
184 unsigned nbo;
185 struct radeon_bo **bo;
186 unsigned ndraw;
187 struct radeon_draw *cdraw;
188 struct radeon_draw **draw;
189 unsigned nstate;
190 struct radeon_state **state;
191 };
192
193 /*
194 * R600/R700
195 */
196
197 enum r600_stype {
198 R600_STATE_CONFIG,
199 R600_STATE_CB_CNTL,
200 R600_STATE_RASTERIZER,
201 R600_STATE_VIEWPORT,
202 R600_STATE_SCISSOR,
203 R600_STATE_BLEND,
204 R600_STATE_DSA,
205 R600_STATE_SHADER, /* has PS,VS,GS,FS variants */
206 R600_STATE_CONSTANT, /* has PS,VS,GS,FS variants */
207 R600_STATE_RESOURCE, /* has PS,VS,GS,FS variants */
208 R600_STATE_SAMPLER, /* has PS,VS,GS,FS variants */
209 R600_STATE_SAMPLER_BORDER, /* has PS,VS,GS,FS variants */
210 R600_STATE_CB0,
211 R600_STATE_CB1,
212 R600_STATE_CB2,
213 R600_STATE_CB3,
214 R600_STATE_CB4,
215 R600_STATE_CB5,
216 R600_STATE_CB6,
217 R600_STATE_CB7,
218 R600_STATE_DB,
219 R600_STATE_QUERY_BEGIN,
220 R600_STATE_QUERY_END,
221 R600_STATE_UCP,
222 R600_STATE_VGT,
223 R600_STATE_DRAW,
224 };
225
226 enum {
227 R600_SHADER_PS = 1,
228 R600_SHADER_VS,
229 R600_SHADER_GS,
230 R600_SHADER_FS,
231 R600_SHADER_MAX = R600_SHADER_FS,
232 };
233
234 /* R600_CONFIG */
235 #define R600_CONFIG__SQ_CONFIG 0
236 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1 1
237 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2 2
238 #define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT 3
239 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1 4
240 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2 5
241 #define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 6
242 #define R600_CONFIG__TA_CNTL_AUX 7
243 #define R600_CONFIG__VC_ENHANCE 8
244 #define R600_CONFIG__DB_DEBUG 9
245 #define R600_CONFIG__DB_WATERMARKS 10
246 #define R600_CONFIG__SX_MISC 11
247 #define R600_CONFIG__SPI_THREAD_GROUPING 12
248 #define R600_CONFIG__CB_SHADER_CONTROL 13
249 #define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 14
250 #define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 15
251 #define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 16
252 #define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 17
253 #define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 18
254 #define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 19
255 #define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 20
256 #define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 21
257 #define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 22
258 #define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 23
259 #define R600_CONFIG__VGT_HOS_CNTL 24
260 #define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 25
261 #define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 26
262 #define R600_CONFIG__VGT_HOS_REUSE_DEPTH 27
263 #define R600_CONFIG__VGT_GROUP_PRIM_TYPE 28
264 #define R600_CONFIG__VGT_GROUP_FIRST_DECR 29
265 #define R600_CONFIG__VGT_GROUP_DECR 30
266 #define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 31
267 #define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 32
268 #define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 33
269 #define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 34
270 #define R600_CONFIG__VGT_GS_MODE 35
271 #define R600_CONFIG__PA_SC_MODE_CNTL 36
272 #define R600_CONFIG__VGT_STRMOUT_EN 37
273 #define R600_CONFIG__VGT_REUSE_OFF 38
274 #define R600_CONFIG__VGT_VTX_CNT_EN 39
275 #define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 40
276 #define R600_CONFIG_SIZE 41
277 #define R600_CONFIG_PM4 128
278 /* R600_CB_CNTL */
279 #define R600_CB_CNTL__CB_CLEAR_RED 0
280 #define R600_CB_CNTL__CB_CLEAR_GREEN 1
281 #define R600_CB_CNTL__CB_CLEAR_BLUE 2
282 #define R600_CB_CNTL__CB_CLEAR_ALPHA 3
283 #define R600_CB_CNTL__CB_SHADER_MASK 4
284 #define R600_CB_CNTL__CB_TARGET_MASK 5
285 #define R600_CB_CNTL__CB_FOG_RED 6
286 #define R600_CB_CNTL__CB_FOG_GREEN 7
287 #define R600_CB_CNTL__CB_FOG_BLUE 8
288 #define R600_CB_CNTL__CB_COLOR_CONTROL 9
289 #define R600_CB_CNTL__PA_SC_AA_CONFIG 10
290 #define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 11
291 #define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 12
292 #define R600_CB_CNTL__CB_CLRCMP_CONTROL 13
293 #define R600_CB_CNTL__CB_CLRCMP_SRC 14
294 #define R600_CB_CNTL__CB_CLRCMP_DST 15
295 #define R600_CB_CNTL__CB_CLRCMP_MSK 16
296 #define R600_CB_CNTL__PA_SC_AA_MASK 17
297 #define R600_CB_CNTL_SIZE 18
298 #define R600_CB_CNTL_PM4 128
299 /* R600_RASTERIZER */
300 #define R600_RASTERIZER__SPI_INTERP_CONTROL_0 0
301 #define R600_RASTERIZER__PA_CL_CLIP_CNTL 1
302 #define R600_RASTERIZER__PA_SU_SC_MODE_CNTL 2
303 #define R600_RASTERIZER__PA_CL_VS_OUT_CNTL 3
304 #define R600_RASTERIZER__PA_CL_NANINF_CNTL 4
305 #define R600_RASTERIZER__PA_SU_POINT_SIZE 5
306 #define R600_RASTERIZER__PA_SU_POINT_MINMAX 6
307 #define R600_RASTERIZER__PA_SU_LINE_CNTL 7
308 #define R600_RASTERIZER__PA_SC_LINE_STIPPLE 8
309 #define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL 9
310 #define R600_RASTERIZER__PA_SC_LINE_CNTL 10
311 #define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11
312 #define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12
313 #define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13
314 #define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14
315 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15
316 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16
317 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17
318 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18
319 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19
320 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20
321 #define R600_RASTERIZER_SIZE 21
322 #define R600_RASTERIZER_PM4 128
323 /* R600_VIEWPORT */
324 #define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0 0
325 #define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0 1
326 #define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0 2
327 #define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0 3
328 #define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4
329 #define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5
330 #define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6
331 #define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7
332 #define R600_VIEWPORT__PA_CL_VTE_CNTL 8
333 #define R600_VIEWPORT_SIZE 9
334 #define R600_VIEWPORT_PM4 128
335 /* R600_SCISSOR */
336 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0
337 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1
338 #define R600_SCISSOR__PA_SC_WINDOW_OFFSET 2
339 #define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3
340 #define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4
341 #define R600_SCISSOR__PA_SC_CLIPRECT_RULE 5
342 #define R600_SCISSOR__PA_SC_CLIPRECT_0_TL 6
343 #define R600_SCISSOR__PA_SC_CLIPRECT_0_BR 7
344 #define R600_SCISSOR__PA_SC_CLIPRECT_1_TL 8
345 #define R600_SCISSOR__PA_SC_CLIPRECT_1_BR 9
346 #define R600_SCISSOR__PA_SC_CLIPRECT_2_TL 10
347 #define R600_SCISSOR__PA_SC_CLIPRECT_2_BR 11
348 #define R600_SCISSOR__PA_SC_CLIPRECT_3_TL 12
349 #define R600_SCISSOR__PA_SC_CLIPRECT_3_BR 13
350 #define R600_SCISSOR__PA_SC_EDGERULE 14
351 #define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15
352 #define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16
353 #define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17
354 #define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18
355 #define R600_SCISSOR_SIZE 19
356 #define R600_SCISSOR_PM4 128
357 /* R600_BLEND */
358 #define R600_BLEND__CB_BLEND_RED 0
359 #define R600_BLEND__CB_BLEND_GREEN 1
360 #define R600_BLEND__CB_BLEND_BLUE 2
361 #define R600_BLEND__CB_BLEND_ALPHA 3
362 #define R600_BLEND__CB_BLEND0_CONTROL 4
363 #define R600_BLEND__CB_BLEND1_CONTROL 5
364 #define R600_BLEND__CB_BLEND2_CONTROL 6
365 #define R600_BLEND__CB_BLEND3_CONTROL 7
366 #define R600_BLEND__CB_BLEND4_CONTROL 8
367 #define R600_BLEND__CB_BLEND5_CONTROL 9
368 #define R600_BLEND__CB_BLEND6_CONTROL 10
369 #define R600_BLEND__CB_BLEND7_CONTROL 11
370 #define R600_BLEND__CB_BLEND_CONTROL 12
371 #define R600_BLEND_SIZE 13
372 #define R600_BLEND_PM4 128
373 /* R600_DSA */
374 #define R600_DSA__DB_STENCIL_CLEAR 0
375 #define R600_DSA__DB_DEPTH_CLEAR 1
376 #define R600_DSA__SX_ALPHA_TEST_CONTROL 2
377 #define R600_DSA__DB_STENCILREFMASK 3
378 #define R600_DSA__DB_STENCILREFMASK_BF 4
379 #define R600_DSA__SX_ALPHA_REF 5
380 #define R600_DSA__SPI_FOG_FUNC_SCALE 6
381 #define R600_DSA__SPI_FOG_FUNC_BIAS 7
382 #define R600_DSA__SPI_FOG_CNTL 8
383 #define R600_DSA__DB_DEPTH_CONTROL 9
384 #define R600_DSA__DB_SHADER_CONTROL 10
385 #define R600_DSA__DB_RENDER_CONTROL 11
386 #define R600_DSA__DB_RENDER_OVERRIDE 12
387 #define R600_DSA__DB_SRESULTS_COMPARE_STATE1 13
388 #define R600_DSA__DB_PRELOAD_CONTROL 14
389 #define R600_DSA__DB_ALPHA_TO_MASK 15
390 #define R600_DSA_SIZE 16
391 #define R600_DSA_PM4 128
392 /* R600_VS_SHADER */
393 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_0 0
394 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_1 1
395 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_2 2
396 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_3 3
397 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_4 4
398 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_5 5
399 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_6 6
400 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_7 7
401 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_8 8
402 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_9 9
403 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_10 10
404 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_11 11
405 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_12 12
406 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_13 13
407 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_14 14
408 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_15 15
409 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_16 16
410 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_17 17
411 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_18 18
412 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_19 19
413 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_20 20
414 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_21 21
415 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_22 22
416 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_23 23
417 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_24 24
418 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_25 25
419 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_26 26
420 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_27 27
421 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_28 28
422 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_29 29
423 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_30 30
424 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_31 31
425 #define R600_VS_SHADER__SPI_VS_OUT_ID_0 32
426 #define R600_VS_SHADER__SPI_VS_OUT_ID_1 33
427 #define R600_VS_SHADER__SPI_VS_OUT_ID_2 34
428 #define R600_VS_SHADER__SPI_VS_OUT_ID_3 35
429 #define R600_VS_SHADER__SPI_VS_OUT_ID_4 36
430 #define R600_VS_SHADER__SPI_VS_OUT_ID_5 37
431 #define R600_VS_SHADER__SPI_VS_OUT_ID_6 38
432 #define R600_VS_SHADER__SPI_VS_OUT_ID_7 39
433 #define R600_VS_SHADER__SPI_VS_OUT_ID_8 40
434 #define R600_VS_SHADER__SPI_VS_OUT_ID_9 41
435 #define R600_VS_SHADER__SPI_VS_OUT_CONFIG 42
436 #define R600_VS_SHADER__SQ_PGM_START_VS 43
437 #define R600_VS_SHADER__SQ_PGM_RESOURCES_VS 44
438 #define R600_VS_SHADER__SQ_PGM_START_FS 45
439 #define R600_VS_SHADER__SQ_PGM_RESOURCES_FS 46
440 #define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS 47
441 #define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS 48
442 #define R600_VS_SHADER_SIZE 49
443 #define R600_VS_SHADER_PM4 128
444 /* R600_PS_SHADER */
445 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 0
446 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1 1
447 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_2 2
448 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_3 3
449 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_4 4
450 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_5 5
451 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_6 6
452 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_7 7
453 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_8 8
454 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_9 9
455 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_10 10
456 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_11 11
457 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_12 12
458 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_13 13
459 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_14 14
460 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_15 15
461 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_16 16
462 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_17 17
463 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_18 18
464 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_19 19
465 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_20 20
466 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_21 21
467 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_22 22
468 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_23 23
469 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_24 24
470 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_25 25
471 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_26 26
472 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_27 27
473 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_28 28
474 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29 29
475 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30 30
476 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31 31
477 #define R600_PS_SHADER__SPI_PS_IN_CONTROL_0 32
478 #define R600_PS_SHADER__SPI_PS_IN_CONTROL_1 33
479 #define R600_PS_SHADER__SPI_INPUT_Z 34
480 #define R600_PS_SHADER__SQ_PGM_START_PS 35
481 #define R600_PS_SHADER__SQ_PGM_RESOURCES_PS 36
482 #define R600_PS_SHADER__SQ_PGM_EXPORTS_PS 37
483 #define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS 38
484 #define R600_PS_SHADER_SIZE 39
485 #define R600_PS_SHADER_PM4 128
486 /* R600_PS_CONSTANT */
487 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0 0
488 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0 1
489 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0 2
490 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0 3
491 #define R600_PS_CONSTANT_SIZE 4
492 #define R600_PS_CONSTANT_PM4 128
493 /* R600_VS_CONSTANT */
494 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256 0
495 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256 1
496 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256 2
497 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256 3
498 #define R600_VS_CONSTANT_SIZE 4
499 #define R600_VS_CONSTANT_PM4 128
500 /* R600_PS_RESOURCE */
501 #define R600_PS_RESOURCE__RESOURCE0_WORD0 0
502 #define R600_PS_RESOURCE__RESOURCE0_WORD1 1
503 #define R600_PS_RESOURCE__RESOURCE0_WORD2 2
504 #define R600_PS_RESOURCE__RESOURCE0_WORD3 3
505 #define R600_PS_RESOURCE__RESOURCE0_WORD4 4
506 #define R600_PS_RESOURCE__RESOURCE0_WORD5 5
507 #define R600_PS_RESOURCE__RESOURCE0_WORD6 6
508 #define R600_PS_RESOURCE_SIZE 7
509 #define R600_PS_RESOURCE_PM4 128
510 /* R600_VS_RESOURCE */
511 #define R600_VS_RESOURCE__RESOURCE160_WORD0 0
512 #define R600_VS_RESOURCE__RESOURCE160_WORD1 1
513 #define R600_VS_RESOURCE__RESOURCE160_WORD2 2
514 #define R600_VS_RESOURCE__RESOURCE160_WORD3 3
515 #define R600_VS_RESOURCE__RESOURCE160_WORD4 4
516 #define R600_VS_RESOURCE__RESOURCE160_WORD5 5
517 #define R600_VS_RESOURCE__RESOURCE160_WORD6 6
518 #define R600_VS_RESOURCE_SIZE 7
519 #define R600_VS_RESOURCE_PM4 128
520 /* R600_FS_RESOURCE */
521 #define R600_FS_RESOURCE__RESOURCE320_WORD0 0
522 #define R600_FS_RESOURCE__RESOURCE320_WORD1 1
523 #define R600_FS_RESOURCE__RESOURCE320_WORD2 2
524 #define R600_FS_RESOURCE__RESOURCE320_WORD3 3
525 #define R600_FS_RESOURCE__RESOURCE320_WORD4 4
526 #define R600_FS_RESOURCE__RESOURCE320_WORD5 5
527 #define R600_FS_RESOURCE__RESOURCE320_WORD6 6
528 #define R600_FS_RESOURCE_SIZE 7
529 #define R600_FS_RESOURCE_PM4 128
530 /* R600_GS_RESOURCE */
531 #define R600_GS_RESOURCE__RESOURCE336_WORD0 0
532 #define R600_GS_RESOURCE__RESOURCE336_WORD1 1
533 #define R600_GS_RESOURCE__RESOURCE336_WORD2 2
534 #define R600_GS_RESOURCE__RESOURCE336_WORD3 3
535 #define R600_GS_RESOURCE__RESOURCE336_WORD4 4
536 #define R600_GS_RESOURCE__RESOURCE336_WORD5 5
537 #define R600_GS_RESOURCE__RESOURCE336_WORD6 6
538 #define R600_GS_RESOURCE_SIZE 7
539 #define R600_GS_RESOURCE_PM4 128
540 /* R600_PS_SAMPLER */
541 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0
542 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1
543 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2
544 #define R600_PS_SAMPLER_SIZE 3
545 #define R600_PS_SAMPLER_PM4 128
546 /* R600_VS_SAMPLER */
547 #define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0
548 #define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1
549 #define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2
550 #define R600_VS_SAMPLER_SIZE 3
551 #define R600_VS_SAMPLER_PM4 128
552 /* R600_GS_SAMPLER */
553 #define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0
554 #define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1
555 #define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2
556 #define R600_GS_SAMPLER_SIZE 3
557 #define R600_GS_SAMPLER_PM4 128
558 /* R600_PS_SAMPLER_BORDER */
559 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0
560 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1
561 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2
562 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3
563 #define R600_PS_SAMPLER_BORDER_SIZE 4
564 #define R600_PS_SAMPLER_BORDER_PM4 128
565 /* R600_VS_SAMPLER_BORDER */
566 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0
567 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1
568 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2
569 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3
570 #define R600_VS_SAMPLER_BORDER_SIZE 4
571 #define R600_VS_SAMPLER_BORDER_PM4 128
572 /* R600_GS_SAMPLER_BORDER */
573 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0
574 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1
575 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2
576 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3
577 #define R600_GS_SAMPLER_BORDER_SIZE 4
578 #define R600_GS_SAMPLER_BORDER_PM4 128
579 /* R600_CB0 */
580 #define R600_CB0__CB_COLOR0_BASE 0
581 #define R600_CB0__CB_COLOR0_INFO 1
582 #define R600_CB0__CB_COLOR0_SIZE 2
583 #define R600_CB0__CB_COLOR0_VIEW 3
584 #define R600_CB0__CB_COLOR0_FRAG 4
585 #define R600_CB0__CB_COLOR0_TILE 5
586 #define R600_CB0__CB_COLOR0_MASK 6
587 #define R600_CB0_SIZE 7
588 #define R600_CB0_PM4 128
589 /* R600_DB */
590 #define R600_DB__DB_DEPTH_BASE 0
591 #define R600_DB__DB_DEPTH_SIZE 1
592 #define R600_DB__DB_DEPTH_VIEW 2
593 #define R600_DB__DB_DEPTH_INFO 3
594 #define R600_DB__DB_HTILE_SURFACE 4
595 #define R600_DB__DB_PREFETCH_LIMIT 5
596 #define R600_DB_SIZE 6
597 #define R600_DB_PM4 128
598 /* R600_VGT */
599 #define R600_VGT__VGT_PRIMITIVE_TYPE 0
600 #define R600_VGT__VGT_MAX_VTX_INDX 1
601 #define R600_VGT__VGT_MIN_VTX_INDX 2
602 #define R600_VGT__VGT_INDX_OFFSET 3
603 #define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX 4
604 #define R600_VGT__VGT_DMA_INDEX_TYPE 5
605 #define R600_VGT__VGT_PRIMITIVEID_EN 6
606 #define R600_VGT__VGT_DMA_NUM_INSTANCES 7
607 #define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN 8
608 #define R600_VGT__VGT_INSTANCE_STEP_RATE_0 9
609 #define R600_VGT__VGT_INSTANCE_STEP_RATE_1 10
610 #define R600_VGT_SIZE 11
611 #define R600_VGT_PM4 128
612 /* R600_DRAW */
613 #define R600_DRAW__VGT_NUM_INDICES 0
614 #define R600_DRAW__VGT_DMA_BASE_HI 1
615 #define R600_DRAW__VGT_DMA_BASE 2
616 #define R600_DRAW__VGT_DRAW_INITIATOR 3
617 #define R600_DRAW_SIZE 4
618 #define R600_DRAW_PM4 128
619 /* R600_CLIP */
620 #define R600_CLIP__PA_CL_UCP_X_0 0
621 #define R600_CLIP__PA_CL_UCP_Y_0 1
622 #define R600_CLIP__PA_CL_UCP_Z_0 2
623 #define R600_CLIP__PA_CL_UCP_W_0 3
624 #define R600_CLIP__PA_CL_UCP_X_1 4
625 #define R600_CLIP__PA_CL_UCP_Y_1 5
626 #define R600_CLIP__PA_CL_UCP_Z_1 6
627 #define R600_CLIP__PA_CL_UCP_W_1 7
628 #define R600_CLIP__PA_CL_UCP_X_2 8
629 #define R600_CLIP__PA_CL_UCP_Y_2 9
630 #define R600_CLIP__PA_CL_UCP_Z_2 10
631 #define R600_CLIP__PA_CL_UCP_W_2 11
632 #define R600_CLIP__PA_CL_UCP_X_3 12
633 #define R600_CLIP__PA_CL_UCP_Y_3 13
634 #define R600_CLIP__PA_CL_UCP_Z_3 14
635 #define R600_CLIP__PA_CL_UCP_W_3 15
636 #define R600_CLIP__PA_CL_UCP_X_4 16
637 #define R600_CLIP__PA_CL_UCP_Y_4 17
638 #define R600_CLIP__PA_CL_UCP_Z_4 18
639 #define R600_CLIP__PA_CL_UCP_W_4 19
640 #define R600_CLIP__PA_CL_UCP_X_5 20
641 #define R600_CLIP__PA_CL_UCP_Y_5 21
642 #define R600_CLIP__PA_CL_UCP_Z_5 22
643 #define R600_CLIP__PA_CL_UCP_W_5 23
644 #define R600_CLIP_SIZE 24
645 #define R600_CLIP_PM4 128
646 /* R600 QUERY BEGIN/END */
647 #define R600_QUERY__OFFSET 0
648 #define R600_QUERY_SIZE 1
649 #define R600_QUERY_PM4 128
650
651 #endif