src/gallium/drivers/r600/radeon.h

   1 /*
   2  * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * This file is free software; you can redistribute it and/or modify
   5  * it under the terms of version 2 of the GNU General Public License
   6  * as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software Foundation,
  15  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  16  */
  17 #ifndef RADEON_H
  18 #define RADEON_H
  19
  20 #define RADEON_CTX_MAX_PM4      (64 * 1024 / 4)
  21
  22 #include <stdint.h>
  23
  24 typedef uint64_t                u64;
  25 typedef uint32_t                u32;
  26 typedef uint16_t                u16;
  27 typedef uint8_t                 u8;
  28
  29 struct radeon;
  30
  31 enum radeon_family {
  32         CHIP_UNKNOWN,
  33         CHIP_R100,
  34         CHIP_RV100,
  35         CHIP_RS100,
  36         CHIP_RV200,
  37         CHIP_RS200,
  38         CHIP_R200,
  39         CHIP_RV250,
  40         CHIP_RS300,
  41         CHIP_RV280,
  42         CHIP_R300,
  43         CHIP_R350,
  44         CHIP_RV350,
  45         CHIP_RV380,
  46         CHIP_R420,
  47         CHIP_R423,
  48         CHIP_RV410,
  49         CHIP_RS400,
  50         CHIP_RS480,
  51         CHIP_RS600,
  52         CHIP_RS690,
  53         CHIP_RS740,
  54         CHIP_RV515,
  55         CHIP_R520,
  56         CHIP_RV530,
  57         CHIP_RV560,
  58         CHIP_RV570,
  59         CHIP_R580,
  60         CHIP_R600,
  61         CHIP_RV610,
  62         CHIP_RV630,
  63         CHIP_RV670,
  64         CHIP_RV620,
  65         CHIP_RV635,
  66         CHIP_RS780,
  67         CHIP_RS880,
  68         CHIP_RV770,
  69         CHIP_RV730,
  70         CHIP_RV710,
  71         CHIP_RV740,
  72         CHIP_CEDAR,
  73         CHIP_REDWOOD,
  74         CHIP_JUNIPER,
  75         CHIP_CYPRESS,
  76         CHIP_HEMLOCK,
  77         CHIP_LAST,
  78 };
  79
  80 enum {
  81         R600_SHADER_PS = 1,
  82         R600_SHADER_VS,
  83         R600_SHADER_GS,
  84         R600_SHADER_FS,
  85         R600_SHADER_MAX = R600_SHADER_FS,
  86 };
  87
  88 enum radeon_family radeon_get_family(struct radeon *rw);
  89
  90 /*
  91  * radeon object functions
  92  */
  93 struct radeon_bo {
  94         unsigned                        refcount;
  95         unsigned                        handle;
  96         unsigned                        size;
  97         unsigned                        alignment;
  98         unsigned                        map_count;
  99         void                            *data;
 100 };
 101 struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
 102                         unsigned size, unsigned alignment, void *ptr);
 103 int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
 104 void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
 105 struct radeon_bo *radeon_bo_incref(struct radeon *radeon, struct radeon_bo *bo);
 106 struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo);
 107 int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
 108
 109 struct radeon_stype_info;
 110 /*
 111  * states functions
 112  */
 113 struct radeon_state {
 114         struct radeon                   *radeon;
 115         unsigned                        refcount;
 116         struct radeon_stype_info        *stype;
 117         unsigned                        state_id;
 118         unsigned                        id;
 119         unsigned                        shader_index;
 120         unsigned                        nstates;
 121         u32                             states[64];
 122         unsigned                        npm4;
 123         unsigned                        cpm4;
 124         u32                             pm4_crc;
 125         u32                             pm4[128];
 126         unsigned                        nbo;
 127         struct radeon_bo                *bo[4];
 128         unsigned                        nreloc;
 129         unsigned                        reloc_pm4_id[8];
 130         unsigned                        reloc_bo_id[8];
 131         u32                             placement[8];
 132         unsigned                        bo_dirty[4];
 133 };
 134
 135 int radeon_state_init(struct radeon_state *rstate, struct radeon *radeon, u32 type, u32 id, u32 shader_class);
 136 void radeon_state_fini(struct radeon_state *state);
 137 int radeon_state_pm4(struct radeon_state *state);
 138 int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type);
 139
 140 /*
 141  * draw functions
 142  */
 143 struct radeon_draw {
 144         struct radeon                   *radeon;
 145         struct radeon_state             **state;
 146 };
 147
 148 int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon);
 149 void radeon_draw_bind(struct radeon_draw *draw, struct radeon_state *state);
 150 void radeon_draw_unbind(struct radeon_draw *draw, struct radeon_state *state);
 151
 152 /*
 153  * radeon context functions
 154  */
 155 #pragma pack(1)
 156 struct radeon_cs_reloc {
 157         uint32_t        handle;
 158         uint32_t        read_domain;
 159         uint32_t        write_domain;
 160         uint32_t        flags;
 161 };
 162 #pragma pack()
 163
 164 struct radeon_ctx {
 165         struct radeon                   *radeon;
 166         u32                             *pm4;
 167         int                             cdwords;
 168         int                             ndwords;
 169         unsigned                        nreloc;
 170         struct radeon_cs_reloc          *reloc;
 171         unsigned                        nbo;
 172         struct radeon_bo                **bo;
 173 };
 174
 175 int radeon_ctx_init(struct radeon_ctx *ctx, struct radeon *radeon);
 176 void radeon_ctx_fini(struct radeon_ctx *ctx);
 177 void radeon_ctx_clear(struct radeon_ctx *ctx);
 178 int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
 179 int radeon_ctx_submit(struct radeon_ctx *ctx);
 180 void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
 181 int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
 182
 183 /*
 184  * R600/R700
 185  */
 186
 187 enum r600_stype {
 188         R600_STATE_CONFIG,
 189         R600_STATE_CB_CNTL,
 190         R600_STATE_RASTERIZER,
 191         R600_STATE_VIEWPORT,
 192         R600_STATE_SCISSOR,
 193         R600_STATE_BLEND,
 194         R600_STATE_DSA,
 195         R600_STATE_SHADER,          /* has PS,VS,GS,FS variants */
 196         R600_STATE_CONSTANT,        /* has PS,VS,GS,FS variants */
 197         R600_STATE_CBUF,        /* has PS,VS,GS,FS variants */
 198         R600_STATE_RESOURCE,        /* has PS,VS,GS,FS variants */
 199         R600_STATE_SAMPLER,         /* has PS,VS,GS,FS variants */
 200         R600_STATE_SAMPLER_BORDER,  /* has PS,VS,GS,FS variants */
 201         R600_STATE_CB0,
 202         R600_STATE_CB1,
 203         R600_STATE_CB2,
 204         R600_STATE_CB3,
 205         R600_STATE_CB4,
 206         R600_STATE_CB5,
 207         R600_STATE_CB6,
 208         R600_STATE_CB7,
 209         R600_STATE_DB,
 210         R600_STATE_QUERY_BEGIN,
 211         R600_STATE_QUERY_END,
 212         R600_STATE_UCP,
 213         R600_STATE_VGT,
 214         R600_STATE_DRAW,
 215         R600_STATE_CB_FLUSH,
 216         R600_STATE_DB_FLUSH,
 217 };
 218
 219 #include "r600_states_inc.h"
 220
 221 /* R600 QUERY BEGIN/END */
 222 #define R600_QUERY__OFFSET                      0
 223 #define R600_QUERY_SIZE                         1
 224 #define R600_QUERY_PM4                          128
 225
 226 #endif