709ef8a85aeebf15eab814dc0c46c08f20f7b924
2 * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software Foundation,
15 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20 #define RADEON_CTX_MAX_PM4 (64 * 1024 / 4)
80 enum radeon_family
radeon_get_family(struct radeon
*rw
);
83 * radeon object functions
93 struct radeon_bo
*radeon_bo(struct radeon
*radeon
, unsigned handle
,
94 unsigned size
, unsigned alignment
, void *ptr
);
95 int radeon_bo_map(struct radeon
*radeon
, struct radeon_bo
*bo
);
96 void radeon_bo_unmap(struct radeon
*radeon
, struct radeon_bo
*bo
);
97 struct radeon_bo
*radeon_bo_incref(struct radeon
*radeon
, struct radeon_bo
*bo
);
98 struct radeon_bo
*radeon_bo_decref(struct radeon
*radeon
, struct radeon_bo
*bo
);
99 int radeon_bo_wait(struct radeon
*radeon
, struct radeon_bo
*bo
);
104 struct radeon_state
{
105 struct radeon
*radeon
;
118 struct radeon_bo
*bo
[4];
120 unsigned reloc_pm4_id
[8];
121 unsigned reloc_bo_id
[8];
123 unsigned bo_dirty
[4];
126 int radeon_state_init(struct radeon_state
*state
, struct radeon
*radeon
, u32 type
, u32 id
);
127 int radeon_state_pm4(struct radeon_state
*state
);
133 struct radeon
*radeon
;
135 struct radeon_state state
[1273];
139 int radeon_draw_init(struct radeon_draw
*draw
, struct radeon
*radeon
);
140 int radeon_draw_set(struct radeon_draw
*draw
, struct radeon_state
*state
);
141 int radeon_draw_check(struct radeon_draw
*draw
);
147 struct radeon_cs_reloc
{
149 uint32_t read_domain
;
150 uint32_t write_domain
;
156 struct radeon
*radeon
;
162 struct radeon_cs_reloc reloc
[2048];
164 struct radeon_bo
*bo
[2048];
166 struct radeon_draw draw
[128];
169 int radeon_ctx_init(struct radeon_ctx
*ctx
, struct radeon
*radeon
);
170 int radeon_ctx_set_draw(struct radeon_ctx
*ctx
, struct radeon_draw
*draw
);
171 int radeon_ctx_pm4(struct radeon_ctx
*ctx
);
172 int radeon_ctx_submit(struct radeon_ctx
*ctx
);
173 void radeon_ctx_dump_bof(struct radeon_ctx
*ctx
, const char *file
);
179 #define R600_NSTATE 1273
180 #define R600_NTYPE 25
182 #define R600_CONFIG 0
183 #define R600_CONFIG_TYPE 0
184 #define R600_CB_CNTL 1
185 #define R600_CB_CNTL_TYPE 1
186 #define R600_RASTERIZER 2
187 #define R600_RASTERIZER_TYPE 2
188 #define R600_VIEWPORT 3
189 #define R600_VIEWPORT_TYPE 3
190 #define R600_SCISSOR 4
191 #define R600_SCISSOR_TYPE 4
193 #define R600_BLEND_TYPE 5
195 #define R600_DSA_TYPE 6
196 #define R600_VS_SHADER 7
197 #define R600_VS_SHADER_TYPE 7
198 #define R600_PS_SHADER 8
199 #define R600_PS_SHADER_TYPE 8
200 #define R600_PS_CONSTANT 9
201 #define R600_PS_CONSTANT_TYPE 9
202 #define R600_VS_CONSTANT 265
203 #define R600_VS_CONSTANT_TYPE 10
204 #define R600_PS_RESOURCE 521
205 #define R600_PS_RESOURCE_TYPE 11
206 #define R600_VS_RESOURCE 681
207 #define R600_VS_RESOURCE_TYPE 12
208 #define R600_FS_RESOURCE 841
209 #define R600_FS_RESOURCE_TYPE 13
210 #define R600_GS_RESOURCE 1001
211 #define R600_GS_RESOURCE_TYPE 14
212 #define R600_PS_SAMPLER 1161
213 #define R600_PS_SAMPLER_TYPE 15
214 #define R600_VS_SAMPLER 1179
215 #define R600_VS_SAMPLER_TYPE 16
216 #define R600_GS_SAMPLER 1197
217 #define R600_GS_SAMPLER_TYPE 17
218 #define R600_PS_SAMPLER_BORDER 1215
219 #define R600_PS_SAMPLER_BORDER_TYPE 18
220 #define R600_VS_SAMPLER_BORDER 1233
221 #define R600_VS_SAMPLER_BORDER_TYPE 19
222 #define R600_GS_SAMPLER_BORDER 1251
223 #define R600_GS_SAMPLER_BORDER_TYPE 20
224 #define R600_CB0 1269
225 #define R600_CB0_TYPE 21
227 #define R600_DB_TYPE 22
228 #define R600_VGT 1271
229 #define R600_VGT_TYPE 23
230 #define R600_DRAW 1272
231 #define R600_DRAW_TYPE 24
233 #define R600_CONFIG__SQ_CONFIG 0
234 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1 1
235 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2 2
236 #define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT 3
237 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1 4
238 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2 5
239 #define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 6
240 #define R600_CONFIG__TA_CNTL_AUX 7
241 #define R600_CONFIG__VC_ENHANCE 8
242 #define R600_CONFIG__DB_DEBUG 9
243 #define R600_CONFIG__DB_WATERMARKS 10
244 #define R600_CONFIG__SX_MISC 11
245 #define R600_CONFIG__SPI_THREAD_GROUPING 12
246 #define R600_CONFIG__CB_SHADER_CONTROL 13
247 #define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 14
248 #define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 15
249 #define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 16
250 #define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 17
251 #define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 18
252 #define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 19
253 #define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 20
254 #define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 21
255 #define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 22
256 #define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 23
257 #define R600_CONFIG__VGT_HOS_CNTL 24
258 #define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 25
259 #define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 26
260 #define R600_CONFIG__VGT_HOS_REUSE_DEPTH 27
261 #define R600_CONFIG__VGT_GROUP_PRIM_TYPE 28
262 #define R600_CONFIG__VGT_GROUP_FIRST_DECR 29
263 #define R600_CONFIG__VGT_GROUP_DECR 30
264 #define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 31
265 #define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 32
266 #define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 33
267 #define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 34
268 #define R600_CONFIG__VGT_GS_MODE 35
269 #define R600_CONFIG__PA_SC_MODE_CNTL 36
270 #define R600_CONFIG__VGT_STRMOUT_EN 37
271 #define R600_CONFIG__VGT_REUSE_OFF 38
272 #define R600_CONFIG__VGT_VTX_CNT_EN 39
273 #define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 40
274 #define R600_CONFIG_SIZE 41
275 #define R600_CONFIG_PM4 128
277 #define R600_CB_CNTL__CB_CLEAR_RED 0
278 #define R600_CB_CNTL__CB_CLEAR_GREEN 1
279 #define R600_CB_CNTL__CB_CLEAR_BLUE 2
280 #define R600_CB_CNTL__CB_CLEAR_ALPHA 3
281 #define R600_CB_CNTL__CB_SHADER_MASK 4
282 #define R600_CB_CNTL__CB_TARGET_MASK 5
283 #define R600_CB_CNTL__CB_FOG_RED 6
284 #define R600_CB_CNTL__CB_FOG_GREEN 7
285 #define R600_CB_CNTL__CB_FOG_BLUE 8
286 #define R600_CB_CNTL__CB_COLOR_CONTROL 9
287 #define R600_CB_CNTL__PA_SC_AA_CONFIG 10
288 #define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 11
289 #define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 12
290 #define R600_CB_CNTL__CB_CLRCMP_CONTROL 13
291 #define R600_CB_CNTL__CB_CLRCMP_SRC 14
292 #define R600_CB_CNTL__CB_CLRCMP_DST 15
293 #define R600_CB_CNTL__CB_CLRCMP_MSK 16
294 #define R600_CB_CNTL__PA_SC_AA_MASK 17
295 #define R600_CB_CNTL_SIZE 18
296 #define R600_CB_CNTL_PM4 128
297 /* R600_RASTERIZER */
298 #define R600_RASTERIZER__SPI_INTERP_CONTROL_0 0
299 #define R600_RASTERIZER__PA_CL_CLIP_CNTL 1
300 #define R600_RASTERIZER__PA_SU_SC_MODE_CNTL 2
301 #define R600_RASTERIZER__PA_CL_VS_OUT_CNTL 3
302 #define R600_RASTERIZER__PA_CL_NANINF_CNTL 4
303 #define R600_RASTERIZER__PA_SU_POINT_SIZE 5
304 #define R600_RASTERIZER__PA_SU_POINT_MINMAX 6
305 #define R600_RASTERIZER__PA_SU_LINE_CNTL 7
306 #define R600_RASTERIZER__PA_SC_LINE_STIPPLE 8
307 #define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL 9
308 #define R600_RASTERIZER__PA_SC_LINE_CNTL 10
309 #define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11
310 #define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12
311 #define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13
312 #define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14
313 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15
314 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16
315 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17
316 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18
317 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19
318 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20
319 #define R600_RASTERIZER_SIZE 21
320 #define R600_RASTERIZER_PM4 128
322 #define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0 0
323 #define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0 1
324 #define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0 2
325 #define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0 3
326 #define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4
327 #define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5
328 #define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6
329 #define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7
330 #define R600_VIEWPORT__PA_CL_VTE_CNTL 8
331 #define R600_VIEWPORT_SIZE 9
332 #define R600_VIEWPORT_PM4 128
334 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0
335 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1
336 #define R600_SCISSOR__PA_SC_WINDOW_OFFSET 2
337 #define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3
338 #define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4
339 #define R600_SCISSOR__PA_SC_CLIPRECT_RULE 5
340 #define R600_SCISSOR__PA_SC_CLIPRECT_0_TL 6
341 #define R600_SCISSOR__PA_SC_CLIPRECT_0_BR 7
342 #define R600_SCISSOR__PA_SC_CLIPRECT_1_TL 8
343 #define R600_SCISSOR__PA_SC_CLIPRECT_1_BR 9
344 #define R600_SCISSOR__PA_SC_CLIPRECT_2_TL 10
345 #define R600_SCISSOR__PA_SC_CLIPRECT_2_BR 11
346 #define R600_SCISSOR__PA_SC_CLIPRECT_3_TL 12
347 #define R600_SCISSOR__PA_SC_CLIPRECT_3_BR 13
348 #define R600_SCISSOR__PA_SC_EDGERULE 14
349 #define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15
350 #define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16
351 #define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17
352 #define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18
353 #define R600_SCISSOR_SIZE 19
354 #define R600_SCISSOR_PM4 128
356 #define R600_BLEND__CB_BLEND_RED 0
357 #define R600_BLEND__CB_BLEND_GREEN 1
358 #define R600_BLEND__CB_BLEND_BLUE 2
359 #define R600_BLEND__CB_BLEND_ALPHA 3
360 #define R600_BLEND__CB_BLEND0_CONTROL 4
361 #define R600_BLEND__CB_BLEND1_CONTROL 5
362 #define R600_BLEND__CB_BLEND2_CONTROL 6
363 #define R600_BLEND__CB_BLEND3_CONTROL 7
364 #define R600_BLEND__CB_BLEND4_CONTROL 8
365 #define R600_BLEND__CB_BLEND5_CONTROL 9
366 #define R600_BLEND__CB_BLEND6_CONTROL 10
367 #define R600_BLEND__CB_BLEND7_CONTROL 11
368 #define R600_BLEND__CB_BLEND_CONTROL 12
369 #define R600_BLEND_SIZE 13
370 #define R600_BLEND_PM4 128
372 #define R600_DSA__DB_STENCIL_CLEAR 0
373 #define R600_DSA__DB_DEPTH_CLEAR 1
374 #define R600_DSA__SX_ALPHA_TEST_CONTROL 2
375 #define R600_DSA__DB_STENCILREFMASK 3
376 #define R600_DSA__DB_STENCILREFMASK_BF 4
377 #define R600_DSA__SX_ALPHA_REF 5
378 #define R600_DSA__SPI_FOG_FUNC_SCALE 6
379 #define R600_DSA__SPI_FOG_FUNC_BIAS 7
380 #define R600_DSA__SPI_FOG_CNTL 8
381 #define R600_DSA__DB_DEPTH_CONTROL 9
382 #define R600_DSA__DB_SHADER_CONTROL 10
383 #define R600_DSA__DB_RENDER_CONTROL 11
384 #define R600_DSA__DB_RENDER_OVERRIDE 12
385 #define R600_DSA__DB_SRESULTS_COMPARE_STATE1 13
386 #define R600_DSA__DB_PRELOAD_CONTROL 14
387 #define R600_DSA__DB_ALPHA_TO_MASK 15
388 #define R600_DSA_SIZE 16
389 #define R600_DSA_PM4 128
391 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_0 0
392 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_1 1
393 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_2 2
394 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_3 3
395 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_4 4
396 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_5 5
397 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_6 6
398 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_7 7
399 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_8 8
400 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_9 9
401 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_10 10
402 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_11 11
403 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_12 12
404 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_13 13
405 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_14 14
406 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_15 15
407 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_16 16
408 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_17 17
409 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_18 18
410 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_19 19
411 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_20 20
412 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_21 21
413 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_22 22
414 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_23 23
415 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_24 24
416 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_25 25
417 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_26 26
418 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_27 27
419 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_28 28
420 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_29 29
421 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_30 30
422 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_31 31
423 #define R600_VS_SHADER__SPI_VS_OUT_ID_0 32
424 #define R600_VS_SHADER__SPI_VS_OUT_ID_1 33
425 #define R600_VS_SHADER__SPI_VS_OUT_ID_2 34
426 #define R600_VS_SHADER__SPI_VS_OUT_ID_3 35
427 #define R600_VS_SHADER__SPI_VS_OUT_ID_4 36
428 #define R600_VS_SHADER__SPI_VS_OUT_ID_5 37
429 #define R600_VS_SHADER__SPI_VS_OUT_ID_6 38
430 #define R600_VS_SHADER__SPI_VS_OUT_ID_7 39
431 #define R600_VS_SHADER__SPI_VS_OUT_ID_8 40
432 #define R600_VS_SHADER__SPI_VS_OUT_ID_9 41
433 #define R600_VS_SHADER__SPI_VS_OUT_CONFIG 42
434 #define R600_VS_SHADER__SQ_PGM_START_VS 43
435 #define R600_VS_SHADER__SQ_PGM_RESOURCES_VS 44
436 #define R600_VS_SHADER__SQ_PGM_START_FS 45
437 #define R600_VS_SHADER__SQ_PGM_RESOURCES_FS 46
438 #define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS 47
439 #define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS 48
440 #define R600_VS_SHADER_SIZE 49
441 #define R600_VS_SHADER_PM4 128
443 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 0
444 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1 1
445 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_2 2
446 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_3 3
447 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_4 4
448 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_5 5
449 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_6 6
450 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_7 7
451 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_8 8
452 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_9 9
453 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_10 10
454 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_11 11
455 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_12 12
456 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_13 13
457 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_14 14
458 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_15 15
459 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_16 16
460 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_17 17
461 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_18 18
462 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_19 19
463 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_20 20
464 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_21 21
465 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_22 22
466 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_23 23
467 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_24 24
468 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_25 25
469 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_26 26
470 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_27 27
471 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_28 28
472 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29 29
473 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30 30
474 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31 31
475 #define R600_PS_SHADER__SPI_PS_IN_CONTROL_0 32
476 #define R600_PS_SHADER__SPI_PS_IN_CONTROL_1 33
477 #define R600_PS_SHADER__SPI_INPUT_Z 34
478 #define R600_PS_SHADER__SQ_PGM_START_PS 35
479 #define R600_PS_SHADER__SQ_PGM_RESOURCES_PS 36
480 #define R600_PS_SHADER__SQ_PGM_EXPORTS_PS 37
481 #define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS 38
482 #define R600_PS_SHADER_SIZE 39
483 #define R600_PS_SHADER_PM4 128
484 /* R600_PS_CONSTANT */
485 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0 0
486 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0 1
487 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0 2
488 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0 3
489 #define R600_PS_CONSTANT_SIZE 4
490 #define R600_PS_CONSTANT_PM4 128
491 /* R600_VS_CONSTANT */
492 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256 0
493 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256 1
494 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256 2
495 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256 3
496 #define R600_VS_CONSTANT_SIZE 4
497 #define R600_VS_CONSTANT_PM4 128
498 /* R600_PS_RESOURCE */
499 #define R600_PS_RESOURCE__RESOURCE0_WORD0 0
500 #define R600_PS_RESOURCE__RESOURCE0_WORD1 1
501 #define R600_PS_RESOURCE__RESOURCE0_WORD2 2
502 #define R600_PS_RESOURCE__RESOURCE0_WORD3 3
503 #define R600_PS_RESOURCE__RESOURCE0_WORD4 4
504 #define R600_PS_RESOURCE__RESOURCE0_WORD5 5
505 #define R600_PS_RESOURCE__RESOURCE0_WORD6 6
506 #define R600_PS_RESOURCE_SIZE 7
507 #define R600_PS_RESOURCE_PM4 128
508 /* R600_VS_RESOURCE */
509 #define R600_VS_RESOURCE__RESOURCE160_WORD0 0
510 #define R600_VS_RESOURCE__RESOURCE160_WORD1 1
511 #define R600_VS_RESOURCE__RESOURCE160_WORD2 2
512 #define R600_VS_RESOURCE__RESOURCE160_WORD3 3
513 #define R600_VS_RESOURCE__RESOURCE160_WORD4 4
514 #define R600_VS_RESOURCE__RESOURCE160_WORD5 5
515 #define R600_VS_RESOURCE__RESOURCE160_WORD6 6
516 #define R600_VS_RESOURCE_SIZE 7
517 #define R600_VS_RESOURCE_PM4 128
518 /* R600_FS_RESOURCE */
519 #define R600_FS_RESOURCE__RESOURCE320_WORD0 0
520 #define R600_FS_RESOURCE__RESOURCE320_WORD1 1
521 #define R600_FS_RESOURCE__RESOURCE320_WORD2 2
522 #define R600_FS_RESOURCE__RESOURCE320_WORD3 3
523 #define R600_FS_RESOURCE__RESOURCE320_WORD4 4
524 #define R600_FS_RESOURCE__RESOURCE320_WORD5 5
525 #define R600_FS_RESOURCE__RESOURCE320_WORD6 6
526 #define R600_FS_RESOURCE_SIZE 7
527 #define R600_FS_RESOURCE_PM4 128
528 /* R600_GS_RESOURCE */
529 #define R600_GS_RESOURCE__RESOURCE336_WORD0 0
530 #define R600_GS_RESOURCE__RESOURCE336_WORD1 1
531 #define R600_GS_RESOURCE__RESOURCE336_WORD2 2
532 #define R600_GS_RESOURCE__RESOURCE336_WORD3 3
533 #define R600_GS_RESOURCE__RESOURCE336_WORD4 4
534 #define R600_GS_RESOURCE__RESOURCE336_WORD5 5
535 #define R600_GS_RESOURCE__RESOURCE336_WORD6 6
536 #define R600_GS_RESOURCE_SIZE 7
537 #define R600_GS_RESOURCE_PM4 128
538 /* R600_PS_SAMPLER */
539 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0
540 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1
541 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2
542 #define R600_PS_SAMPLER_SIZE 3
543 #define R600_PS_SAMPLER_PM4 128
544 /* R600_VS_SAMPLER */
545 #define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0
546 #define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1
547 #define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2
548 #define R600_VS_SAMPLER_SIZE 3
549 #define R600_VS_SAMPLER_PM4 128
550 /* R600_GS_SAMPLER */
551 #define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0
552 #define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1
553 #define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2
554 #define R600_GS_SAMPLER_SIZE 3
555 #define R600_GS_SAMPLER_PM4 128
556 /* R600_PS_SAMPLER_BORDER */
557 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0
558 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1
559 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2
560 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3
561 #define R600_PS_SAMPLER_BORDER_SIZE 4
562 #define R600_PS_SAMPLER_BORDER_PM4 128
563 /* R600_VS_SAMPLER_BORDER */
564 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0
565 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1
566 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2
567 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3
568 #define R600_VS_SAMPLER_BORDER_SIZE 4
569 #define R600_VS_SAMPLER_BORDER_PM4 128
570 /* R600_GS_SAMPLER_BORDER */
571 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0
572 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1
573 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2
574 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3
575 #define R600_GS_SAMPLER_BORDER_SIZE 4
576 #define R600_GS_SAMPLER_BORDER_PM4 128
578 #define R600_CB0__CB_COLOR0_BASE 0
579 #define R600_CB0__CB_COLOR0_INFO 1
580 #define R600_CB0__CB_COLOR0_SIZE 2
581 #define R600_CB0__CB_COLOR0_VIEW 3
582 #define R600_CB0__CB_COLOR0_FRAG 4
583 #define R600_CB0__CB_COLOR0_TILE 5
584 #define R600_CB0__CB_COLOR0_MASK 6
585 #define R600_CB0_SIZE 7
586 #define R600_CB0_PM4 128
588 #define R600_DB__DB_DEPTH_BASE 0
589 #define R600_DB__DB_DEPTH_SIZE 1
590 #define R600_DB__DB_DEPTH_VIEW 2
591 #define R600_DB__DB_DEPTH_INFO 3
592 #define R600_DB__DB_HTILE_SURFACE 4
593 #define R600_DB__DB_PREFETCH_LIMIT 5
594 #define R600_DB_SIZE 6
595 #define R600_DB_PM4 128
597 #define R600_VGT__VGT_PRIMITIVE_TYPE 0
598 #define R600_VGT__VGT_MAX_VTX_INDX 1
599 #define R600_VGT__VGT_MIN_VTX_INDX 2
600 #define R600_VGT__VGT_INDX_OFFSET 3
601 #define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX 4
602 #define R600_VGT__VGT_DMA_INDEX_TYPE 5
603 #define R600_VGT__VGT_PRIMITIVEID_EN 6
604 #define R600_VGT__VGT_DMA_NUM_INSTANCES 7
605 #define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN 8
606 #define R600_VGT__VGT_INSTANCE_STEP_RATE_0 9
607 #define R600_VGT__VGT_INSTANCE_STEP_RATE_1 10
608 #define R600_VGT_SIZE 11
609 #define R600_VGT_PM4 128
611 #define R600_DRAW__VGT_NUM_INDICES 0
612 #define R600_DRAW__VGT_DMA_BASE_HI 1
613 #define R600_DRAW__VGT_DMA_BASE 2
614 #define R600_DRAW__VGT_DRAW_INITIATOR 3
615 #define R600_DRAW_SIZE 4
616 #define R600_DRAW_PM4 128