src/gallium/drivers/r600/radeon.h

   1 /*
   2  * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * This file is free software; you can redistribute it and/or modify
   5  * it under the terms of version 2 of the GNU General Public License
   6  * as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software Foundation,
  15  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  16  */
  17 #ifndef RADEON_H
  18 #define RADEON_H
  19
  20 #define RADEON_CTX_MAX_PM4      (64 * 1024 / 4)
  21
  22 #include <stdint.h>
  23
  24 typedef uint64_t                u64;
  25 typedef uint32_t                u32;
  26 typedef uint16_t                u16;
  27 typedef uint8_t                 u8;
  28
  29 struct radeon;
  30
  31 enum radeon_family {
  32         CHIP_UNKNOWN,
  33         CHIP_R100,
  34         CHIP_RV100,
  35         CHIP_RS100,
  36         CHIP_RV200,
  37         CHIP_RS200,
  38         CHIP_R200,
  39         CHIP_RV250,
  40         CHIP_RS300,
  41         CHIP_RV280,
  42         CHIP_R300,
  43         CHIP_R350,
  44         CHIP_RV350,
  45         CHIP_RV380,
  46         CHIP_R420,
  47         CHIP_R423,
  48         CHIP_RV410,
  49         CHIP_RS400,
  50         CHIP_RS480,
  51         CHIP_RS600,
  52         CHIP_RS690,
  53         CHIP_RS740,
  54         CHIP_RV515,
  55         CHIP_R520,
  56         CHIP_RV530,
  57         CHIP_RV560,
  58         CHIP_RV570,
  59         CHIP_R580,
  60         CHIP_R600,
  61         CHIP_RV610,
  62         CHIP_RV630,
  63         CHIP_RV670,
  64         CHIP_RV620,
  65         CHIP_RV635,
  66         CHIP_RS780,
  67         CHIP_RS880,
  68         CHIP_RV770,
  69         CHIP_RV730,
  70         CHIP_RV710,
  71         CHIP_RV740,
  72         CHIP_CEDAR,
  73         CHIP_REDWOOD,
  74         CHIP_JUNIPER,
  75         CHIP_CYPRESS,
  76         CHIP_HEMLOCK,
  77         CHIP_LAST,
  78 };
  79
  80 enum radeon_family radeon_get_family(struct radeon *rw);
  81
  82 /*
  83  * radeon object functions
  84  */
  85 struct radeon_bo {
  86         unsigned                        refcount;
  87         unsigned                        handle;
  88         unsigned                        size;
  89         unsigned                        alignment;
  90         unsigned                        map_count;
  91         void                            *data;
  92 };
  93 struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
  94                         unsigned size, unsigned alignment, void *ptr);
  95 int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
  96 void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
  97 struct radeon_bo *radeon_bo_incref(struct radeon *radeon, struct radeon_bo *bo);
  98 struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo);
  99 int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
 100
 101 /*
 102  * states functions
 103  */
 104 struct radeon_state {
 105         struct radeon                   *radeon;
 106         unsigned                        refcount;
 107         unsigned                        type;
 108         unsigned                        id;
 109         unsigned                        nstates;
 110         u32                             *states;
 111         unsigned                        npm4;
 112         unsigned                        cpm4;
 113         u32                             pm4_crc;
 114         u32                             *pm4;
 115         u32                             nimmd;
 116         u32                             *immd;
 117         unsigned                        nbo;
 118         struct radeon_bo                *bo[4];
 119         unsigned                        nreloc;
 120         unsigned                        reloc_pm4_id[8];
 121         unsigned                        reloc_bo_id[8];
 122         u32                             placement[8];
 123         unsigned                        bo_dirty[4];
 124 };
 125
 126 struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id);
 127 struct radeon_state *radeon_state_incref(struct radeon_state *state);
 128 struct radeon_state *radeon_state_decref(struct radeon_state *state);
 129 int radeon_state_pm4(struct radeon_state *state);
 130
 131 /*
 132  * draw functions
 133  */
 134 struct radeon_draw {
 135         unsigned                        refcount;
 136         struct radeon                   *radeon;
 137         unsigned                        nstate;
 138         struct radeon_state             **state;
 139         unsigned                        cpm4;
 140 };
 141
 142 struct radeon_draw *radeon_draw(struct radeon *radeon);
 143 struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw);
 144 struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw);
 145 struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw);
 146 int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state);
 147 int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state);
 148 int radeon_draw_check(struct radeon_draw *draw);
 149
 150 struct radeon_ctx *radeon_ctx(struct radeon *radeon);
 151 struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
 152 struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
 153 int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
 154 int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
 155 int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
 156 int radeon_ctx_pm4(struct radeon_ctx *ctx);
 157 int radeon_ctx_submit(struct radeon_ctx *ctx);
 158 void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
 159
 160 /*
 161  * radeon context functions
 162  */
 163 #pragma pack(1)
 164 struct radeon_cs_reloc {
 165         uint32_t        handle;
 166         uint32_t        read_domain;
 167         uint32_t        write_domain;
 168         uint32_t        flags;
 169 };
 170 #pragma pack()
 171
 172 struct radeon_ctx {
 173         int                             refcount;
 174         struct radeon                   *radeon;
 175         u32                             *pm4;
 176         u32                             cpm4;
 177         u32                             draw_cpm4;
 178         unsigned                        id;
 179         unsigned                        next_id;
 180         unsigned                        nreloc;
 181         struct radeon_cs_reloc          *reloc;
 182         unsigned                        nbo;
 183         struct radeon_bo                **bo;
 184         unsigned                        ndraw;
 185         struct radeon_draw              *cdraw;
 186         struct radeon_draw              **draw;
 187         unsigned                        nstate;
 188         struct radeon_state             **state;
 189 };
 190
 191 /*
 192  * R600/R700
 193  */
 194
 195 #define R600_NSTATE                             1288
 196 #define R600_NTYPE                              35
 197
 198 #define R600_CONFIG                             0
 199 #define R600_CONFIG_TYPE                                0
 200 #define R600_CB_CNTL                            1
 201 #define R600_CB_CNTL_TYPE                               1
 202 #define R600_RASTERIZER                         2
 203 #define R600_RASTERIZER_TYPE                            2
 204 #define R600_VIEWPORT                           3
 205 #define R600_VIEWPORT_TYPE                              3
 206 #define R600_SCISSOR                            4
 207 #define R600_SCISSOR_TYPE                               4
 208 #define R600_BLEND                              5
 209 #define R600_BLEND_TYPE                         5
 210 #define R600_DSA                                6
 211 #define R600_DSA_TYPE                           6
 212 #define R600_VS_SHADER                          7
 213 #define R600_VS_SHADER_TYPE                             7
 214 #define R600_PS_SHADER                          8
 215 #define R600_PS_SHADER_TYPE                             8
 216 #define R600_PS_CONSTANT                                9
 217 #define R600_PS_CONSTANT_TYPE                           9
 218 #define R600_VS_CONSTANT                                265
 219 #define R600_VS_CONSTANT_TYPE                           10
 220 #define R600_PS_RESOURCE                                521
 221 #define R600_PS_RESOURCE_TYPE                           11
 222 #define R600_VS_RESOURCE                                681
 223 #define R600_VS_RESOURCE_TYPE                           12
 224 #define R600_FS_RESOURCE                                841
 225 #define R600_FS_RESOURCE_TYPE                           13
 226 #define R600_GS_RESOURCE                                1001
 227 #define R600_GS_RESOURCE_TYPE                           14
 228 #define R600_PS_SAMPLER                         1161
 229 #define R600_PS_SAMPLER_TYPE                            15
 230 #define R600_VS_SAMPLER                         1179
 231 #define R600_VS_SAMPLER_TYPE                            16
 232 #define R600_GS_SAMPLER                         1197
 233 #define R600_GS_SAMPLER_TYPE                            17
 234 #define R600_PS_SAMPLER_BORDER                          1215
 235 #define R600_PS_SAMPLER_BORDER_TYPE                             18
 236 #define R600_VS_SAMPLER_BORDER                          1233
 237 #define R600_VS_SAMPLER_BORDER_TYPE                             19
 238 #define R600_GS_SAMPLER_BORDER                          1251
 239 #define R600_GS_SAMPLER_BORDER_TYPE                             20
 240 #define R600_CB0                                1269
 241 #define R600_CB0_TYPE                           21
 242 #define R600_CB1                                1270
 243 #define R600_CB1_TYPE                           22
 244 #define R600_CB2                                1271
 245 #define R600_CB2_TYPE                           23
 246 #define R600_CB3                                1272
 247 #define R600_CB3_TYPE                           24
 248 #define R600_CB4                                1273
 249 #define R600_CB4_TYPE                           25
 250 #define R600_CB5                                1274
 251 #define R600_CB5_TYPE                           26
 252 #define R600_CB6                                1275
 253 #define R600_CB6_TYPE                           27
 254 #define R600_CB7                                1276
 255 #define R600_CB7_TYPE                           28
 256 #define R600_QUERY_BEGIN                        1277
 257 #define R600_QUERY_BEGIN_TYPE                   29
 258 #define R600_QUERY_END                          1278
 259 #define R600_QUERY_END_TYPE                     30
 260 #define R600_DB                                 1279
 261 #define R600_DB_TYPE                            31
 262 #define R600_CLIP                               1280
 263 #define R600_CLIP_TYPE                          32
 264 #define R600_VGT                                1286
 265 #define R600_VGT_TYPE                           33
 266 #define R600_DRAW                               1287
 267 #define R600_DRAW_TYPE                          34
 268
 269 /* R600_CONFIG */
 270 #define R600_CONFIG__SQ_CONFIG                  0
 271 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1                     1
 272 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2                     2
 273 #define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT                    3
 274 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1                   4
 275 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2                   5
 276 #define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ                       6
 277 #define R600_CONFIG__TA_CNTL_AUX                        7
 278 #define R600_CONFIG__VC_ENHANCE                 8
 279 #define R600_CONFIG__DB_DEBUG                   9
 280 #define R600_CONFIG__DB_WATERMARKS                      10
 281 #define R600_CONFIG__SX_MISC                    11
 282 #define R600_CONFIG__SPI_THREAD_GROUPING                        12
 283 #define R600_CONFIG__CB_SHADER_CONTROL                  13
 284 #define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE                      14
 285 #define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE                      15
 286 #define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE                     16
 287 #define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE                     17
 288 #define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE                     18
 289 #define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE                     19
 290 #define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE                      20
 291 #define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE                     21
 292 #define R600_CONFIG__SQ_GS_VERT_ITEMSIZE                        22
 293 #define R600_CONFIG__VGT_OUTPUT_PATH_CNTL                       23
 294 #define R600_CONFIG__VGT_HOS_CNTL                       24
 295 #define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL                     25
 296 #define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL                     26
 297 #define R600_CONFIG__VGT_HOS_REUSE_DEPTH                        27
 298 #define R600_CONFIG__VGT_GROUP_PRIM_TYPE                        28
 299 #define R600_CONFIG__VGT_GROUP_FIRST_DECR                       29
 300 #define R600_CONFIG__VGT_GROUP_DECR                     30
 301 #define R600_CONFIG__VGT_GROUP_VECT_0_CNTL                      31
 302 #define R600_CONFIG__VGT_GROUP_VECT_1_CNTL                      32
 303 #define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL                  33
 304 #define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL                  34
 305 #define R600_CONFIG__VGT_GS_MODE                        35
 306 #define R600_CONFIG__PA_SC_MODE_CNTL                    36
 307 #define R600_CONFIG__VGT_STRMOUT_EN                     37
 308 #define R600_CONFIG__VGT_REUSE_OFF                      38
 309 #define R600_CONFIG__VGT_VTX_CNT_EN                     39
 310 #define R600_CONFIG__VGT_STRMOUT_BUFFER_EN                      40
 311 #define R600_CONFIG_SIZE                                41
 312 #define R600_CONFIG_PM4                         128
 313 /* R600_CB_CNTL */
 314 #define R600_CB_CNTL__CB_CLEAR_RED                      0
 315 #define R600_CB_CNTL__CB_CLEAR_GREEN                    1
 316 #define R600_CB_CNTL__CB_CLEAR_BLUE                     2
 317 #define R600_CB_CNTL__CB_CLEAR_ALPHA                    3
 318 #define R600_CB_CNTL__CB_SHADER_MASK                    4
 319 #define R600_CB_CNTL__CB_TARGET_MASK                    5
 320 #define R600_CB_CNTL__CB_FOG_RED                        6
 321 #define R600_CB_CNTL__CB_FOG_GREEN                      7
 322 #define R600_CB_CNTL__CB_FOG_BLUE                       8
 323 #define R600_CB_CNTL__CB_COLOR_CONTROL                  9
 324 #define R600_CB_CNTL__PA_SC_AA_CONFIG                   10
 325 #define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX                 11
 326 #define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX                  12
 327 #define R600_CB_CNTL__CB_CLRCMP_CONTROL                 13
 328 #define R600_CB_CNTL__CB_CLRCMP_SRC                     14
 329 #define R600_CB_CNTL__CB_CLRCMP_DST                     15
 330 #define R600_CB_CNTL__CB_CLRCMP_MSK                     16
 331 #define R600_CB_CNTL__PA_SC_AA_MASK                     17
 332 #define R600_CB_CNTL_SIZE                               18
 333 #define R600_CB_CNTL_PM4                                128
 334 /* R600_RASTERIZER */
 335 #define R600_RASTERIZER__SPI_INTERP_CONTROL_0                   0
 336 #define R600_RASTERIZER__PA_CL_CLIP_CNTL                        1
 337 #define R600_RASTERIZER__PA_SU_SC_MODE_CNTL                     2
 338 #define R600_RASTERIZER__PA_CL_VS_OUT_CNTL                      3
 339 #define R600_RASTERIZER__PA_CL_NANINF_CNTL                      4
 340 #define R600_RASTERIZER__PA_SU_POINT_SIZE                       5
 341 #define R600_RASTERIZER__PA_SU_POINT_MINMAX                     6
 342 #define R600_RASTERIZER__PA_SU_LINE_CNTL                        7
 343 #define R600_RASTERIZER__PA_SC_LINE_STIPPLE                     8
 344 #define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL                    9
 345 #define R600_RASTERIZER__PA_SC_LINE_CNTL                        10
 346 #define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ                 11
 347 #define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ                 12
 348 #define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ                 13
 349 #define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ                 14
 350 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL                  15
 351 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP                        16
 352 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE                  17
 353 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET                 18
 354 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE                   19
 355 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET                  20
 356 #define R600_RASTERIZER_SIZE                            21
 357 #define R600_RASTERIZER_PM4                             128
 358 /* R600_VIEWPORT */
 359 #define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0                       0
 360 #define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0                       1
 361 #define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0                     2
 362 #define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0                     3
 363 #define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0                     4
 364 #define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0                    5
 365 #define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0                    6
 366 #define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0                    7
 367 #define R600_VIEWPORT__PA_CL_VTE_CNTL                   8
 368 #define R600_VIEWPORT_SIZE                              9
 369 #define R600_VIEWPORT_PM4                               128
 370 /* R600_SCISSOR */
 371 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL                   0
 372 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR                   1
 373 #define R600_SCISSOR__PA_SC_WINDOW_OFFSET                       2
 374 #define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL                   3
 375 #define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR                   4
 376 #define R600_SCISSOR__PA_SC_CLIPRECT_RULE                       5
 377 #define R600_SCISSOR__PA_SC_CLIPRECT_0_TL                       6
 378 #define R600_SCISSOR__PA_SC_CLIPRECT_0_BR                       7
 379 #define R600_SCISSOR__PA_SC_CLIPRECT_1_TL                       8
 380 #define R600_SCISSOR__PA_SC_CLIPRECT_1_BR                       9
 381 #define R600_SCISSOR__PA_SC_CLIPRECT_2_TL                       10
 382 #define R600_SCISSOR__PA_SC_CLIPRECT_2_BR                       11
 383 #define R600_SCISSOR__PA_SC_CLIPRECT_3_TL                       12
 384 #define R600_SCISSOR__PA_SC_CLIPRECT_3_BR                       13
 385 #define R600_SCISSOR__PA_SC_EDGERULE                    14
 386 #define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL                  15
 387 #define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR                  16
 388 #define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL                  17
 389 #define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR                  18
 390 #define R600_SCISSOR_SIZE                               19
 391 #define R600_SCISSOR_PM4                                128
 392 /* R600_BLEND */
 393 #define R600_BLEND__CB_BLEND_RED                        0
 394 #define R600_BLEND__CB_BLEND_GREEN                      1
 395 #define R600_BLEND__CB_BLEND_BLUE                       2
 396 #define R600_BLEND__CB_BLEND_ALPHA                      3
 397 #define R600_BLEND__CB_BLEND0_CONTROL                   4
 398 #define R600_BLEND__CB_BLEND1_CONTROL                   5
 399 #define R600_BLEND__CB_BLEND2_CONTROL                   6
 400 #define R600_BLEND__CB_BLEND3_CONTROL                   7
 401 #define R600_BLEND__CB_BLEND4_CONTROL                   8
 402 #define R600_BLEND__CB_BLEND5_CONTROL                   9
 403 #define R600_BLEND__CB_BLEND6_CONTROL                   10
 404 #define R600_BLEND__CB_BLEND7_CONTROL                   11
 405 #define R600_BLEND__CB_BLEND_CONTROL                    12
 406 #define R600_BLEND_SIZE                         13
 407 #define R600_BLEND_PM4                          128
 408 /* R600_DSA */
 409 #define R600_DSA__DB_STENCIL_CLEAR                      0
 410 #define R600_DSA__DB_DEPTH_CLEAR                        1
 411 #define R600_DSA__SX_ALPHA_TEST_CONTROL                 2
 412 #define R600_DSA__DB_STENCILREFMASK                     3
 413 #define R600_DSA__DB_STENCILREFMASK_BF                  4
 414 #define R600_DSA__SX_ALPHA_REF                  5
 415 #define R600_DSA__SPI_FOG_FUNC_SCALE                    6
 416 #define R600_DSA__SPI_FOG_FUNC_BIAS                     7
 417 #define R600_DSA__SPI_FOG_CNTL                  8
 418 #define R600_DSA__DB_DEPTH_CONTROL                      9
 419 #define R600_DSA__DB_SHADER_CONTROL                     10
 420 #define R600_DSA__DB_RENDER_CONTROL                     11
 421 #define R600_DSA__DB_RENDER_OVERRIDE                    12
 422 #define R600_DSA__DB_SRESULTS_COMPARE_STATE1                    13
 423 #define R600_DSA__DB_PRELOAD_CONTROL                    14
 424 #define R600_DSA__DB_ALPHA_TO_MASK                      15
 425 #define R600_DSA_SIZE                           16
 426 #define R600_DSA_PM4                            128
 427 /* R600_VS_SHADER */
 428 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_0                       0
 429 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_1                       1
 430 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_2                       2
 431 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_3                       3
 432 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_4                       4
 433 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_5                       5
 434 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_6                       6
 435 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_7                       7
 436 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_8                       8
 437 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_9                       9
 438 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_10                      10
 439 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_11                      11
 440 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_12                      12
 441 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_13                      13
 442 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_14                      14
 443 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_15                      15
 444 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_16                      16
 445 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_17                      17
 446 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_18                      18
 447 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_19                      19
 448 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_20                      20
 449 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_21                      21
 450 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_22                      22
 451 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_23                      23
 452 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_24                      24
 453 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_25                      25
 454 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_26                      26
 455 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_27                      27
 456 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_28                      28
 457 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_29                      29
 458 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_30                      30
 459 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_31                      31
 460 #define R600_VS_SHADER__SPI_VS_OUT_ID_0                 32
 461 #define R600_VS_SHADER__SPI_VS_OUT_ID_1                 33
 462 #define R600_VS_SHADER__SPI_VS_OUT_ID_2                 34
 463 #define R600_VS_SHADER__SPI_VS_OUT_ID_3                 35
 464 #define R600_VS_SHADER__SPI_VS_OUT_ID_4                 36
 465 #define R600_VS_SHADER__SPI_VS_OUT_ID_5                 37
 466 #define R600_VS_SHADER__SPI_VS_OUT_ID_6                 38
 467 #define R600_VS_SHADER__SPI_VS_OUT_ID_7                 39
 468 #define R600_VS_SHADER__SPI_VS_OUT_ID_8                 40
 469 #define R600_VS_SHADER__SPI_VS_OUT_ID_9                 41
 470 #define R600_VS_SHADER__SPI_VS_OUT_CONFIG                       42
 471 #define R600_VS_SHADER__SQ_PGM_START_VS                 43
 472 #define R600_VS_SHADER__SQ_PGM_RESOURCES_VS                     44
 473 #define R600_VS_SHADER__SQ_PGM_START_FS                 45
 474 #define R600_VS_SHADER__SQ_PGM_RESOURCES_FS                     46
 475 #define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS                     47
 476 #define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS                     48
 477 #define R600_VS_SHADER_SIZE                             49
 478 #define R600_VS_SHADER_PM4                              128
 479 /* R600_PS_SHADER */
 480 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0                     0
 481 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1                     1
 482 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_2                     2
 483 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_3                     3
 484 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_4                     4
 485 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_5                     5
 486 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_6                     6
 487 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_7                     7
 488 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_8                     8
 489 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_9                     9
 490 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_10                    10
 491 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_11                    11
 492 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_12                    12
 493 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_13                    13
 494 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_14                    14
 495 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_15                    15
 496 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_16                    16
 497 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_17                    17
 498 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_18                    18
 499 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_19                    19
 500 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_20                    20
 501 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_21                    21
 502 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_22                    22
 503 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_23                    23
 504 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_24                    24
 505 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_25                    25
 506 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_26                    26
 507 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_27                    27
 508 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_28                    28
 509 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29                    29
 510 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30                    30
 511 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31                    31
 512 #define R600_PS_SHADER__SPI_PS_IN_CONTROL_0                     32
 513 #define R600_PS_SHADER__SPI_PS_IN_CONTROL_1                     33
 514 #define R600_PS_SHADER__SPI_INPUT_Z                     34
 515 #define R600_PS_SHADER__SQ_PGM_START_PS                 35
 516 #define R600_PS_SHADER__SQ_PGM_RESOURCES_PS                     36
 517 #define R600_PS_SHADER__SQ_PGM_EXPORTS_PS                       37
 518 #define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS                     38
 519 #define R600_PS_SHADER_SIZE                             39
 520 #define R600_PS_SHADER_PM4                              128
 521 /* R600_PS_CONSTANT */
 522 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0                    0
 523 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0                    1
 524 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0                    2
 525 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0                    3
 526 #define R600_PS_CONSTANT_SIZE                           4
 527 #define R600_PS_CONSTANT_PM4                            128
 528 /* R600_VS_CONSTANT */
 529 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256                  0
 530 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256                  1
 531 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256                  2
 532 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256                  3
 533 #define R600_VS_CONSTANT_SIZE                           4
 534 #define R600_VS_CONSTANT_PM4                            128
 535 /* R600_PS_RESOURCE */
 536 #define R600_PS_RESOURCE__RESOURCE0_WORD0                       0
 537 #define R600_PS_RESOURCE__RESOURCE0_WORD1                       1
 538 #define R600_PS_RESOURCE__RESOURCE0_WORD2                       2
 539 #define R600_PS_RESOURCE__RESOURCE0_WORD3                       3
 540 #define R600_PS_RESOURCE__RESOURCE0_WORD4                       4
 541 #define R600_PS_RESOURCE__RESOURCE0_WORD5                       5
 542 #define R600_PS_RESOURCE__RESOURCE0_WORD6                       6
 543 #define R600_PS_RESOURCE_SIZE                           7
 544 #define R600_PS_RESOURCE_PM4                            128
 545 /* R600_VS_RESOURCE */
 546 #define R600_VS_RESOURCE__RESOURCE160_WORD0                     0
 547 #define R600_VS_RESOURCE__RESOURCE160_WORD1                     1
 548 #define R600_VS_RESOURCE__RESOURCE160_WORD2                     2
 549 #define R600_VS_RESOURCE__RESOURCE160_WORD3                     3
 550 #define R600_VS_RESOURCE__RESOURCE160_WORD4                     4
 551 #define R600_VS_RESOURCE__RESOURCE160_WORD5                     5
 552 #define R600_VS_RESOURCE__RESOURCE160_WORD6                     6
 553 #define R600_VS_RESOURCE_SIZE                           7
 554 #define R600_VS_RESOURCE_PM4                            128
 555 /* R600_FS_RESOURCE */
 556 #define R600_FS_RESOURCE__RESOURCE320_WORD0                     0
 557 #define R600_FS_RESOURCE__RESOURCE320_WORD1                     1
 558 #define R600_FS_RESOURCE__RESOURCE320_WORD2                     2
 559 #define R600_FS_RESOURCE__RESOURCE320_WORD3                     3
 560 #define R600_FS_RESOURCE__RESOURCE320_WORD4                     4
 561 #define R600_FS_RESOURCE__RESOURCE320_WORD5                     5
 562 #define R600_FS_RESOURCE__RESOURCE320_WORD6                     6
 563 #define R600_FS_RESOURCE_SIZE                           7
 564 #define R600_FS_RESOURCE_PM4                            128
 565 /* R600_GS_RESOURCE */
 566 #define R600_GS_RESOURCE__RESOURCE336_WORD0                     0
 567 #define R600_GS_RESOURCE__RESOURCE336_WORD1                     1
 568 #define R600_GS_RESOURCE__RESOURCE336_WORD2                     2
 569 #define R600_GS_RESOURCE__RESOURCE336_WORD3                     3
 570 #define R600_GS_RESOURCE__RESOURCE336_WORD4                     4
 571 #define R600_GS_RESOURCE__RESOURCE336_WORD5                     5
 572 #define R600_GS_RESOURCE__RESOURCE336_WORD6                     6
 573 #define R600_GS_RESOURCE_SIZE                           7
 574 #define R600_GS_RESOURCE_PM4                            128
 575 /* R600_PS_SAMPLER */
 576 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0                 0
 577 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0                 1
 578 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0                 2
 579 #define R600_PS_SAMPLER_SIZE                            3
 580 #define R600_PS_SAMPLER_PM4                             128
 581 /* R600_VS_SAMPLER */
 582 #define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18                        0
 583 #define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18                        1
 584 #define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18                        2
 585 #define R600_VS_SAMPLER_SIZE                            3
 586 #define R600_VS_SAMPLER_PM4                             128
 587 /* R600_GS_SAMPLER */
 588 #define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36                        0
 589 #define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36                        1
 590 #define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36                        2
 591 #define R600_GS_SAMPLER_SIZE                            3
 592 #define R600_GS_SAMPLER_PM4                             128
 593 /* R600_PS_SAMPLER_BORDER */
 594 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED                       0
 595 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN                     1
 596 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE                      2
 597 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA                     3
 598 #define R600_PS_SAMPLER_BORDER_SIZE                             4
 599 #define R600_PS_SAMPLER_BORDER_PM4                              128
 600 /* R600_VS_SAMPLER_BORDER */
 601 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED                       0
 602 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN                     1
 603 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE                      2
 604 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA                     3
 605 #define R600_VS_SAMPLER_BORDER_SIZE                             4
 606 #define R600_VS_SAMPLER_BORDER_PM4                              128
 607 /* R600_GS_SAMPLER_BORDER */
 608 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED                       0
 609 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN                     1
 610 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE                      2
 611 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA                     3
 612 #define R600_GS_SAMPLER_BORDER_SIZE                             4
 613 #define R600_GS_SAMPLER_BORDER_PM4                              128
 614 /* R600_CB0 */
 615 #define R600_CB0__CB_COLOR0_BASE                        0
 616 #define R600_CB0__CB_COLOR0_INFO                        1
 617 #define R600_CB0__CB_COLOR0_SIZE                        2
 618 #define R600_CB0__CB_COLOR0_VIEW                        3
 619 #define R600_CB0__CB_COLOR0_FRAG                        4
 620 #define R600_CB0__CB_COLOR0_TILE                        5
 621 #define R600_CB0__CB_COLOR0_MASK                        6
 622 #define R600_CB0_SIZE                           7
 623 #define R600_CB0_PM4                            128
 624 /* R600_DB */
 625 #define R600_DB__DB_DEPTH_BASE                  0
 626 #define R600_DB__DB_DEPTH_SIZE                  1
 627 #define R600_DB__DB_DEPTH_VIEW                  2
 628 #define R600_DB__DB_DEPTH_INFO                  3
 629 #define R600_DB__DB_HTILE_SURFACE                       4
 630 #define R600_DB__DB_PREFETCH_LIMIT                      5
 631 #define R600_DB_SIZE                            6
 632 #define R600_DB_PM4                             128
 633 /* R600_VGT */
 634 #define R600_VGT__VGT_PRIMITIVE_TYPE                    0
 635 #define R600_VGT__VGT_MAX_VTX_INDX                      1
 636 #define R600_VGT__VGT_MIN_VTX_INDX                      2
 637 #define R600_VGT__VGT_INDX_OFFSET                       3
 638 #define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX                  4
 639 #define R600_VGT__VGT_DMA_INDEX_TYPE                    5
 640 #define R600_VGT__VGT_PRIMITIVEID_EN                    6
 641 #define R600_VGT__VGT_DMA_NUM_INSTANCES                 7
 642 #define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN                    8
 643 #define R600_VGT__VGT_INSTANCE_STEP_RATE_0                      9
 644 #define R600_VGT__VGT_INSTANCE_STEP_RATE_1                      10
 645 #define R600_VGT_SIZE                           11
 646 #define R600_VGT_PM4                            128
 647 /* R600_DRAW */
 648 #define R600_DRAW__VGT_NUM_INDICES                      0
 649 #define R600_DRAW__VGT_DMA_BASE_HI                      1
 650 #define R600_DRAW__VGT_DMA_BASE                 2
 651 #define R600_DRAW__VGT_DRAW_INITIATOR                   3
 652 #define R600_DRAW_SIZE                          4
 653 #define R600_DRAW_PM4                           128
 654 /* R600_CLIP */
 655 #define R600_CLIP__PA_CL_UCP_X_0  0
 656 #define R600_CLIP__PA_CL_UCP_Y_0  1
 657 #define R600_CLIP__PA_CL_UCP_Z_0  2
 658 #define R600_CLIP__PA_CL_UCP_W_0  3
 659 #define R600_CLIP_SIZE  4
 660 #define R600_CLIP_PM4 128
 661 /* R600 QUERY BEGIN/END */
 662 #define R600_QUERY__OFFSET                      0
 663 #define R600_QUERY_SIZE                         1
 664 #define R600_QUERY_PM4                          128
 665
 666 #endif