r600g: move chip class to radeon common structure
[mesa.git] / src / gallium / drivers / r600 / radeon.h
1 /*
2 * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software Foundation,
15 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
16 */
17 #ifndef RADEON_H
18 #define RADEON_H
19
20 #define RADEON_CTX_MAX_PM4 (64 * 1024 / 4)
21
22 #include <stdint.h>
23
24 #include <pipe/p_compiler.h>
25
26 typedef uint64_t u64;
27 typedef uint32_t u32;
28 typedef uint16_t u16;
29 typedef uint8_t u8;
30
31 struct radeon;
32
33 enum radeon_family {
34 CHIP_UNKNOWN,
35 CHIP_R100,
36 CHIP_RV100,
37 CHIP_RS100,
38 CHIP_RV200,
39 CHIP_RS200,
40 CHIP_R200,
41 CHIP_RV250,
42 CHIP_RS300,
43 CHIP_RV280,
44 CHIP_R300,
45 CHIP_R350,
46 CHIP_RV350,
47 CHIP_RV380,
48 CHIP_R420,
49 CHIP_R423,
50 CHIP_RV410,
51 CHIP_RS400,
52 CHIP_RS480,
53 CHIP_RS600,
54 CHIP_RS690,
55 CHIP_RS740,
56 CHIP_RV515,
57 CHIP_R520,
58 CHIP_RV530,
59 CHIP_RV560,
60 CHIP_RV570,
61 CHIP_R580,
62 CHIP_R600,
63 CHIP_RV610,
64 CHIP_RV630,
65 CHIP_RV670,
66 CHIP_RV620,
67 CHIP_RV635,
68 CHIP_RS780,
69 CHIP_RS880,
70 CHIP_RV770,
71 CHIP_RV730,
72 CHIP_RV710,
73 CHIP_RV740,
74 CHIP_CEDAR,
75 CHIP_REDWOOD,
76 CHIP_JUNIPER,
77 CHIP_CYPRESS,
78 CHIP_HEMLOCK,
79 CHIP_LAST,
80 };
81
82 enum chip_class {
83 R600,
84 R700,
85 EVERGREEN,
86 };
87
88 enum {
89 R600_SHADER_PS = 1,
90 R600_SHADER_VS,
91 R600_SHADER_GS,
92 R600_SHADER_FS,
93 R600_SHADER_MAX = R600_SHADER_FS,
94 };
95
96 enum radeon_family radeon_get_family(struct radeon *rw);
97 enum chip_class radeon_get_family_class(struct radeon *radeon);
98 void radeon_set_mem_constant(struct radeon *radeon, boolean state);
99
100 /* lowlevel WS bo */
101 struct radeon_ws_bo;
102 struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
103 unsigned size, unsigned alignment, unsigned usage);
104 struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
105 unsigned handle);
106 void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo, unsigned usage, void *ctx);
107 void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo);
108 void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
109 struct radeon_ws_bo *src);
110
111 struct radeon_stype_info;
112
113 /* currently limited to max buffers in a cb flush */
114 #define RADEON_STATE_MAX_BO 8
115 /*
116 * states functions
117 */
118 struct radeon_state {
119 struct radeon *radeon;
120 unsigned refcount;
121 struct radeon_stype_info *stype;
122 unsigned state_id;
123 unsigned id;
124 unsigned shader_index;
125 unsigned nstates;
126 u32 states[64];
127 unsigned npm4;
128 unsigned cpm4;
129 u32 pm4_crc;
130 u32 pm4[128];
131 unsigned nbo;
132 struct radeon_ws_bo *bo[RADEON_STATE_MAX_BO];
133 unsigned nreloc;
134 unsigned reloc_pm4_id[8];
135 unsigned reloc_bo_id[8];
136 u32 placement[8];
137 unsigned bo_dirty[4];
138 };
139
140 int radeon_state_init(struct radeon_state *rstate, struct radeon *radeon, u32 type, u32 id, u32 shader_class);
141 void radeon_state_fini(struct radeon_state *state);
142 int radeon_state_pm4(struct radeon_state *state);
143 int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type);
144
145 /*
146 * draw functions
147 */
148 struct radeon_draw {
149 struct radeon *radeon;
150 struct radeon_state **state;
151 };
152
153 int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon);
154 void radeon_draw_bind(struct radeon_draw *draw, struct radeon_state *state);
155 void radeon_draw_unbind(struct radeon_draw *draw, struct radeon_state *state);
156
157 /*
158 * radeon context functions
159 */
160 #pragma pack(1)
161 struct radeon_cs_reloc {
162 uint32_t handle;
163 uint32_t read_domain;
164 uint32_t write_domain;
165 uint32_t flags;
166 };
167 #pragma pack()
168
169 struct radeon_ctx;
170
171 struct radeon_ctx *radeon_ctx_init(struct radeon *radeon);
172 void radeon_ctx_fini(struct radeon_ctx *ctx);
173 void radeon_ctx_clear(struct radeon_ctx *ctx);
174 int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
175 int radeon_ctx_submit(struct radeon_ctx *ctx);
176 void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
177 int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
178
179 /*
180 * R600/R700
181 */
182
183 enum r600_stype {
184 R600_STATE_CONFIG,
185 R600_STATE_CB_CNTL,
186 R600_STATE_RASTERIZER,
187 R600_STATE_VIEWPORT,
188 R600_STATE_SCISSOR,
189 R600_STATE_BLEND,
190 R600_STATE_DSA,
191 R600_STATE_SHADER, /* has PS,VS,GS,FS variants */
192 R600_STATE_CONSTANT, /* has PS,VS,GS,FS variants */
193 R600_STATE_CBUF, /* has PS,VS,GS,FS variants */
194 R600_STATE_RESOURCE, /* has PS,VS,GS,FS variants */
195 R600_STATE_SAMPLER, /* has PS,VS,GS,FS variants */
196 R600_STATE_SAMPLER_BORDER, /* has PS,VS,GS,FS variants */
197 R600_STATE_CB0,
198 R600_STATE_CB1,
199 R600_STATE_CB2,
200 R600_STATE_CB3,
201 R600_STATE_CB4,
202 R600_STATE_CB5,
203 R600_STATE_CB6,
204 R600_STATE_CB7,
205 R600_STATE_DB,
206 R600_STATE_QUERY_BEGIN,
207 R600_STATE_QUERY_END,
208 R600_STATE_UCP,
209 R600_STATE_VGT,
210 R600_STATE_DRAW,
211 R600_STATE_CB_FLUSH,
212 R600_STATE_DB_FLUSH,
213 R600_STATE_MAX,
214 };
215
216 #include "r600_states_inc.h"
217 #include "eg_states_inc.h"
218
219 /* R600 QUERY BEGIN/END */
220 #define R600_QUERY__OFFSET 0
221 #define R600_QUERY_SIZE 1
222 #define R600_QUERY_PM4 128
223
224 void r600_flush_ctx(void *data);
225 #endif