v3d: Add support for handling OOM signals from the simulator.
[mesa.git] / src / gallium / drivers / r600 / radeon_vce.c
1 /**************************************************************************
2 *
3 * Copyright 2013 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * Authors:
30 * Christian König <christian.koenig@amd.com>
31 *
32 */
33
34 #include <stdio.h>
35
36 #include "pipe/p_video_codec.h"
37
38 #include "util/u_video.h"
39 #include "util/u_memory.h"
40
41 #include "vl/vl_video_buffer.h"
42
43 #include "r600_pipe_common.h"
44 #include "radeon_video.h"
45 #include "radeon_vce.h"
46
47 #define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
48 #define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
49 #define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8))
50 #define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8))
51 #define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8))
52 #define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8))
53 #define FW_52_4_3 ((52 << 24) | (4 << 16) | (3 << 8))
54 #define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8))
55 #define FW_53 (53 << 24)
56
57 /**
58 * flush commands to the hardware
59 */
60 static void flush(struct rvce_encoder *enc)
61 {
62 enc->ws->cs_flush(enc->cs, PIPE_FLUSH_ASYNC, NULL);
63 enc->task_info_idx = 0;
64 enc->bs_idx = 0;
65 }
66
67 #if 0
68 static void dump_feedback(struct rvce_encoder *enc, struct rvid_buffer *fb)
69 {
70 uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE);
71 unsigned i = 0;
72 fprintf(stderr, "\n");
73 fprintf(stderr, "encStatus:\t\t\t%08x\n", ptr[i++]);
74 fprintf(stderr, "encHasBitstream:\t\t%08x\n", ptr[i++]);
75 fprintf(stderr, "encHasAudioBitstream:\t\t%08x\n", ptr[i++]);
76 fprintf(stderr, "encBitstreamOffset:\t\t%08x\n", ptr[i++]);
77 fprintf(stderr, "encBitstreamSize:\t\t%08x\n", ptr[i++]);
78 fprintf(stderr, "encAudioBitstreamOffset:\t%08x\n", ptr[i++]);
79 fprintf(stderr, "encAudioBitstreamSize:\t\t%08x\n", ptr[i++]);
80 fprintf(stderr, "encExtrabytes:\t\t\t%08x\n", ptr[i++]);
81 fprintf(stderr, "encAudioExtrabytes:\t\t%08x\n", ptr[i++]);
82 fprintf(stderr, "videoTimeStamp:\t\t\t%08x\n", ptr[i++]);
83 fprintf(stderr, "audioTimeStamp:\t\t\t%08x\n", ptr[i++]);
84 fprintf(stderr, "videoOutputType:\t\t%08x\n", ptr[i++]);
85 fprintf(stderr, "attributeFlags:\t\t\t%08x\n", ptr[i++]);
86 fprintf(stderr, "seiPrivatePackageOffset:\t%08x\n", ptr[i++]);
87 fprintf(stderr, "seiPrivatePackageSize:\t\t%08x\n", ptr[i++]);
88 fprintf(stderr, "\n");
89 enc->ws->buffer_unmap(fb->res->buf);
90 }
91 #endif
92
93 /**
94 * reset the CPB handling
95 */
96 static void reset_cpb(struct rvce_encoder *enc)
97 {
98 unsigned i;
99
100 LIST_INITHEAD(&enc->cpb_slots);
101 for (i = 0; i < enc->cpb_num; ++i) {
102 struct rvce_cpb_slot *slot = &enc->cpb_array[i];
103 slot->index = i;
104 slot->picture_type = PIPE_H264_ENC_PICTURE_TYPE_SKIP;
105 slot->frame_num = 0;
106 slot->pic_order_cnt = 0;
107 LIST_ADDTAIL(&slot->list, &enc->cpb_slots);
108 }
109 }
110
111 /**
112 * sort l0 and l1 to the top of the list
113 */
114 static void sort_cpb(struct rvce_encoder *enc)
115 {
116 struct rvce_cpb_slot *i, *l0 = NULL, *l1 = NULL;
117
118 LIST_FOR_EACH_ENTRY(i, &enc->cpb_slots, list) {
119 if (i->frame_num == enc->pic.ref_idx_l0)
120 l0 = i;
121
122 if (i->frame_num == enc->pic.ref_idx_l1)
123 l1 = i;
124
125 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P && l0)
126 break;
127
128 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B &&
129 l0 && l1)
130 break;
131 }
132
133 if (l1) {
134 LIST_DEL(&l1->list);
135 LIST_ADD(&l1->list, &enc->cpb_slots);
136 }
137
138 if (l0) {
139 LIST_DEL(&l0->list);
140 LIST_ADD(&l0->list, &enc->cpb_slots);
141 }
142 }
143
144 /**
145 * get number of cpbs based on dpb
146 */
147 static unsigned get_cpb_num(struct rvce_encoder *enc)
148 {
149 unsigned w = align(enc->base.width, 16) / 16;
150 unsigned h = align(enc->base.height, 16) / 16;
151 unsigned dpb;
152
153 switch (enc->base.level) {
154 case 10:
155 dpb = 396;
156 break;
157 case 11:
158 dpb = 900;
159 break;
160 case 12:
161 case 13:
162 case 20:
163 dpb = 2376;
164 break;
165 case 21:
166 dpb = 4752;
167 break;
168 case 22:
169 case 30:
170 dpb = 8100;
171 break;
172 case 31:
173 dpb = 18000;
174 break;
175 case 32:
176 dpb = 20480;
177 break;
178 case 40:
179 case 41:
180 dpb = 32768;
181 break;
182 case 42:
183 dpb = 34816;
184 break;
185 case 50:
186 dpb = 110400;
187 break;
188 default:
189 case 51:
190 case 52:
191 dpb = 184320;
192 break;
193 }
194
195 return MIN2(dpb / (w * h), 16);
196 }
197
198 /**
199 * Get the slot for the currently encoded frame
200 */
201 struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc)
202 {
203 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.prev, list);
204 }
205
206 /**
207 * Get the slot for L0
208 */
209 struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc)
210 {
211 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next, list);
212 }
213
214 /**
215 * Get the slot for L1
216 */
217 struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc)
218 {
219 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next, list);
220 }
221
222 /**
223 * Calculate the offsets into the CPB
224 */
225 void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
226 signed *luma_offset, signed *chroma_offset)
227 {
228 unsigned pitch, vpitch, fsize;
229
230 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128);
231 vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16);
232 fsize = pitch * (vpitch + vpitch / 2);
233
234 *luma_offset = slot->index * fsize;
235 *chroma_offset = *luma_offset + pitch * vpitch;
236 }
237
238 /**
239 * destroy this video encoder
240 */
241 static void rvce_destroy(struct pipe_video_codec *encoder)
242 {
243 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
244 if (enc->stream_handle) {
245 struct rvid_buffer fb;
246 rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
247 enc->fb = &fb;
248 enc->session(enc);
249 enc->feedback(enc);
250 enc->destroy(enc);
251 flush(enc);
252 rvid_destroy_buffer(&fb);
253 }
254 rvid_destroy_buffer(&enc->cpb);
255 enc->ws->cs_destroy(enc->cs);
256 FREE(enc->cpb_array);
257 FREE(enc);
258 }
259
260 static void rvce_begin_frame(struct pipe_video_codec *encoder,
261 struct pipe_video_buffer *source,
262 struct pipe_picture_desc *picture)
263 {
264 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
265 struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
266 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
267
268 bool need_rate_control =
269 enc->pic.rate_ctrl.rate_ctrl_method != pic->rate_ctrl.rate_ctrl_method ||
270 enc->pic.quant_i_frames != pic->quant_i_frames ||
271 enc->pic.quant_p_frames != pic->quant_p_frames ||
272 enc->pic.quant_b_frames != pic->quant_b_frames;
273
274 enc->pic = *pic;
275 get_pic_param(enc, pic);
276
277 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
278 enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
279
280 if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
281 reset_cpb(enc);
282 else if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_P ||
283 pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)
284 sort_cpb(enc);
285
286 if (!enc->stream_handle) {
287 struct rvid_buffer fb;
288 enc->stream_handle = rvid_alloc_stream_handle();
289 rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
290 enc->fb = &fb;
291 enc->session(enc);
292 enc->create(enc);
293 enc->config(enc);
294 enc->feedback(enc);
295 flush(enc);
296 //dump_feedback(enc, &fb);
297 rvid_destroy_buffer(&fb);
298 need_rate_control = false;
299 }
300
301 if (need_rate_control) {
302 enc->session(enc);
303 enc->config(enc);
304 flush(enc);
305 }
306 }
307
308 static void rvce_encode_bitstream(struct pipe_video_codec *encoder,
309 struct pipe_video_buffer *source,
310 struct pipe_resource *destination,
311 void **fb)
312 {
313 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
314 enc->get_buffer(destination, &enc->bs_handle, NULL);
315 enc->bs_size = destination->width0;
316
317 *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
318 if (!rvid_create_buffer(enc->screen, enc->fb, 512, PIPE_USAGE_STAGING)) {
319 RVID_ERR("Can't create feedback buffer.\n");
320 return;
321 }
322 if (!radeon_emitted(enc->cs, 0))
323 enc->session(enc);
324 enc->encode(enc);
325 enc->feedback(enc);
326 }
327
328 static void rvce_end_frame(struct pipe_video_codec *encoder,
329 struct pipe_video_buffer *source,
330 struct pipe_picture_desc *picture)
331 {
332 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
333 struct rvce_cpb_slot *slot = LIST_ENTRY(
334 struct rvce_cpb_slot, enc->cpb_slots.prev, list);
335
336 if (!enc->dual_inst || enc->bs_idx > 1)
337 flush(enc);
338
339 /* update the CPB backtrack with the just encoded frame */
340 slot->picture_type = enc->pic.picture_type;
341 slot->frame_num = enc->pic.frame_num;
342 slot->pic_order_cnt = enc->pic.pic_order_cnt;
343 if (!enc->pic.not_referenced) {
344 LIST_DEL(&slot->list);
345 LIST_ADD(&slot->list, &enc->cpb_slots);
346 }
347 }
348
349 static void rvce_get_feedback(struct pipe_video_codec *encoder,
350 void *feedback, unsigned *size)
351 {
352 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
353 struct rvid_buffer *fb = feedback;
354
355 if (size) {
356 uint32_t *ptr = enc->ws->buffer_map(
357 fb->res->buf, enc->cs,
358 PIPE_TRANSFER_READ_WRITE | RADEON_TRANSFER_TEMPORARY);
359
360 if (ptr[1]) {
361 *size = ptr[4] - ptr[9];
362 } else {
363 *size = 0;
364 }
365
366 enc->ws->buffer_unmap(fb->res->buf);
367 }
368 //dump_feedback(enc, fb);
369 rvid_destroy_buffer(fb);
370 FREE(fb);
371 }
372
373 /**
374 * flush any outstanding command buffers to the hardware
375 */
376 static void rvce_flush(struct pipe_video_codec *encoder)
377 {
378 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
379
380 flush(enc);
381 }
382
383 static void rvce_cs_flush(void *ctx, unsigned flags,
384 struct pipe_fence_handle **fence)
385 {
386 // just ignored
387 }
388
389 struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
390 const struct pipe_video_codec *templ,
391 struct radeon_winsys* ws,
392 rvce_get_buffer get_buffer)
393 {
394 struct r600_common_screen *rscreen = (struct r600_common_screen *)context->screen;
395 struct r600_common_context *rctx = (struct r600_common_context*)context;
396 struct rvce_encoder *enc;
397 struct pipe_video_buffer *tmp_buf, templat = {};
398 struct radeon_surf *tmp_surf;
399 unsigned cpb_size;
400
401 if (!rscreen->info.vce_fw_version) {
402 RVID_ERR("Kernel doesn't supports VCE!\n");
403 return NULL;
404
405 } else if (!rvce_is_fw_version_supported(rscreen)) {
406 RVID_ERR("Unsupported VCE fw version loaded!\n");
407 return NULL;
408 }
409
410 enc = CALLOC_STRUCT(rvce_encoder);
411 if (!enc)
412 return NULL;
413
414 if (rscreen->info.drm_major == 3)
415 enc->use_vm = true;
416 if ((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42) ||
417 rscreen->info.drm_major == 3)
418 enc->use_vui = true;
419
420 enc->base = *templ;
421 enc->base.context = context;
422
423 enc->base.destroy = rvce_destroy;
424 enc->base.begin_frame = rvce_begin_frame;
425 enc->base.encode_bitstream = rvce_encode_bitstream;
426 enc->base.end_frame = rvce_end_frame;
427 enc->base.flush = rvce_flush;
428 enc->base.get_feedback = rvce_get_feedback;
429 enc->get_buffer = get_buffer;
430
431 enc->screen = context->screen;
432 enc->ws = ws;
433 enc->cs = ws->cs_create(rctx->ctx, RING_VCE, rvce_cs_flush, enc, false);
434 if (!enc->cs) {
435 RVID_ERR("Can't get command submission context.\n");
436 goto error;
437 }
438
439 templat.buffer_format = PIPE_FORMAT_NV12;
440 templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
441 templat.width = enc->base.width;
442 templat.height = enc->base.height;
443 templat.interlaced = false;
444 if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
445 RVID_ERR("Can't create video buffer.\n");
446 goto error;
447 }
448
449 enc->cpb_num = get_cpb_num(enc);
450 if (!enc->cpb_num)
451 goto error;
452
453 get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
454
455 cpb_size = align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
456 align(tmp_surf->u.legacy.level[0].nblk_y, 32);
457
458 cpb_size = cpb_size * 3 / 2;
459 cpb_size = cpb_size * enc->cpb_num;
460 if (enc->dual_pipe)
461 cpb_size += RVCE_MAX_AUX_BUFFER_NUM *
462 RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
463 tmp_buf->destroy(tmp_buf);
464 if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
465 RVID_ERR("Can't create CPB buffer.\n");
466 goto error;
467 }
468
469 enc->cpb_array = CALLOC(enc->cpb_num, sizeof(struct rvce_cpb_slot));
470 if (!enc->cpb_array)
471 goto error;
472
473 reset_cpb(enc);
474
475 goto error;
476
477 return &enc->base;
478
479 error:
480 if (enc->cs)
481 enc->ws->cs_destroy(enc->cs);
482
483 rvid_destroy_buffer(&enc->cpb);
484
485 FREE(enc->cpb_array);
486 FREE(enc);
487 return NULL;
488 }
489
490 /**
491 * check if kernel has the right fw version loaded
492 */
493 bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen)
494 {
495 switch (rscreen->info.vce_fw_version) {
496 case FW_40_2_2:
497 case FW_50_0_1:
498 case FW_50_1_2:
499 case FW_50_10_2:
500 case FW_50_17_3:
501 case FW_52_0_3:
502 case FW_52_4_3:
503 case FW_52_8_3:
504 return true;
505 default:
506 if ((rscreen->info.vce_fw_version & (0xff << 24)) == FW_53)
507 return true;
508 else
509 return false;
510 }
511 }
512
513 /**
514 * Add the buffer as relocation to the current command submission
515 */
516 void rvce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
517 enum radeon_bo_usage usage, enum radeon_bo_domain domain,
518 signed offset)
519 {
520 int reloc_idx;
521
522 reloc_idx = enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
523 domain, 0);
524 if (enc->use_vm) {
525 uint64_t addr;
526 addr = enc->ws->buffer_get_virtual_address(buf);
527 addr = addr + offset;
528 RVCE_CS(addr >> 32);
529 RVCE_CS(addr);
530 } else {
531 offset += enc->ws->buffer_get_reloc_offset(buf);
532 RVCE_CS(reloc_idx * 4);
533 RVCE_CS(offset);
534 }
535 }