1 /**************************************************************************
3 * Copyright 2013 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 * Christian König <christian.koenig@amd.com>
36 #include "util/u_memory.h"
37 #include "util/u_video.h"
39 #include "vl/vl_defines.h"
40 #include "vl/vl_video_buffer.h"
42 #include "r600_pipe_common.h"
43 #include "radeon_video.h"
44 #include "radeon_vce.h"
46 #define UVD_FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
48 /* generate an stream handle */
49 unsigned rvid_alloc_stream_handle()
51 static unsigned counter
= 0;
52 unsigned stream_handle
= 0;
53 unsigned pid
= getpid();
56 for (i
= 0; i
< 32; ++i
)
57 stream_handle
|= ((pid
>> i
) & 1) << (31 - i
);
59 stream_handle
^= ++counter
;
63 /* create a buffer in the winsys */
64 bool rvid_create_buffer(struct pipe_screen
*screen
, struct rvid_buffer
*buffer
,
65 unsigned size
, unsigned usage
)
67 memset(buffer
, 0, sizeof(*buffer
));
68 buffer
->usage
= usage
;
70 /* Hardware buffer placement restrictions require the kernel to be
71 * able to move buffers around individually, so request a
72 * non-sub-allocated buffer.
74 buffer
->res
= (struct r600_resource
*)
75 pipe_buffer_create(screen
, PIPE_BIND_SHARED
,
78 return buffer
->res
!= NULL
;
81 /* destroy a buffer */
82 void rvid_destroy_buffer(struct rvid_buffer
*buffer
)
84 r600_resource_reference(&buffer
->res
, NULL
);
87 /* reallocate a buffer, preserving its content */
88 bool rvid_resize_buffer(struct pipe_screen
*screen
, struct radeon_cmdbuf
*cs
,
89 struct rvid_buffer
*new_buf
, unsigned new_size
)
91 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
92 struct radeon_winsys
* ws
= rscreen
->ws
;
93 unsigned bytes
= MIN2(new_buf
->res
->buf
->size
, new_size
);
94 struct rvid_buffer old_buf
= *new_buf
;
95 void *src
= NULL
, *dst
= NULL
;
97 if (!rvid_create_buffer(screen
, new_buf
, new_size
, new_buf
->usage
))
100 src
= ws
->buffer_map(old_buf
.res
->buf
, cs
,
101 PIPE_TRANSFER_READ
| RADEON_TRANSFER_TEMPORARY
);
105 dst
= ws
->buffer_map(new_buf
->res
->buf
, cs
,
106 PIPE_TRANSFER_WRITE
| RADEON_TRANSFER_TEMPORARY
);
110 memcpy(dst
, src
, bytes
);
111 if (new_size
> bytes
) {
114 memset(dst
, 0, new_size
);
116 ws
->buffer_unmap(new_buf
->res
->buf
);
117 ws
->buffer_unmap(old_buf
.res
->buf
);
118 rvid_destroy_buffer(&old_buf
);
123 ws
->buffer_unmap(old_buf
.res
->buf
);
124 rvid_destroy_buffer(new_buf
);
129 /* clear the buffer with zeros */
130 void rvid_clear_buffer(struct pipe_context
*context
, struct rvid_buffer
* buffer
)
132 struct r600_common_context
*rctx
= (struct r600_common_context
*)context
;
134 rctx
->dma_clear_buffer(context
, &buffer
->res
->b
.b
, 0,
135 buffer
->res
->buf
->size
, 0);
136 context
->flush(context
, NULL
, 0);
140 * join surfaces into the same buffer with identical tiling params
141 * sumup their sizes and replace the backend buffers with a single bo
143 void rvid_join_surfaces(struct r600_common_context
*rctx
,
144 struct pb_buffer
** buffers
[VL_NUM_COMPONENTS
],
145 struct radeon_surf
*surfaces
[VL_NUM_COMPONENTS
])
147 struct radeon_winsys
* ws
;
148 unsigned best_tiling
, best_wh
, off
;
149 unsigned size
, alignment
;
150 struct pb_buffer
*pb
;
155 for (i
= 0, best_tiling
= 0, best_wh
= ~0; i
< VL_NUM_COMPONENTS
; ++i
) {
161 /* choose the smallest bank w/h for now */
162 wh
= surfaces
[i
]->u
.legacy
.bankw
* surfaces
[i
]->u
.legacy
.bankh
;
169 for (i
= 0, off
= 0; i
< VL_NUM_COMPONENTS
; ++i
) {
173 /* adjust the texture layer offsets */
174 off
= align(off
, surfaces
[i
]->surf_alignment
);
176 /* copy the tiling parameters */
177 surfaces
[i
]->u
.legacy
.bankw
= surfaces
[best_tiling
]->u
.legacy
.bankw
;
178 surfaces
[i
]->u
.legacy
.bankh
= surfaces
[best_tiling
]->u
.legacy
.bankh
;
179 surfaces
[i
]->u
.legacy
.mtilea
= surfaces
[best_tiling
]->u
.legacy
.mtilea
;
180 surfaces
[i
]->u
.legacy
.tile_split
= surfaces
[best_tiling
]->u
.legacy
.tile_split
;
182 for (j
= 0; j
< ARRAY_SIZE(surfaces
[i
]->u
.legacy
.level
); ++j
)
183 surfaces
[i
]->u
.legacy
.level
[j
].offset
+= off
;
185 off
+= surfaces
[i
]->surf_size
;
188 for (i
= 0, size
= 0, alignment
= 0; i
< VL_NUM_COMPONENTS
; ++i
) {
189 if (!buffers
[i
] || !*buffers
[i
])
192 size
= align(size
, (*buffers
[i
])->alignment
);
193 size
+= (*buffers
[i
])->size
;
194 alignment
= MAX2(alignment
, (*buffers
[i
])->alignment
* 1);
200 /* TODO: 2D tiling workaround */
203 pb
= ws
->buffer_create(ws
, size
, alignment
, RADEON_DOMAIN_VRAM
,
208 for (i
= 0; i
< VL_NUM_COMPONENTS
; ++i
) {
209 if (!buffers
[i
] || !*buffers
[i
])
212 pb_reference(buffers
[i
], pb
);
215 pb_reference(&pb
, NULL
);
218 int rvid_get_video_param(struct pipe_screen
*screen
,
219 enum pipe_video_profile profile
,
220 enum pipe_video_entrypoint entrypoint
,
221 enum pipe_video_cap param
)
223 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
224 enum pipe_video_format codec
= u_reduce_video_profile(profile
);
225 struct radeon_info info
;
227 rscreen
->ws
->query_info(rscreen
->ws
, &info
);
229 if (entrypoint
== PIPE_VIDEO_ENTRYPOINT_ENCODE
) {
231 case PIPE_VIDEO_CAP_SUPPORTED
:
232 return codec
== PIPE_VIDEO_FORMAT_MPEG4_AVC
&&
233 rvce_is_fw_version_supported(rscreen
);
234 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
236 case PIPE_VIDEO_CAP_MAX_WIDTH
:
238 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
240 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
241 return PIPE_FORMAT_NV12
;
242 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
244 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
246 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
248 case PIPE_VIDEO_CAP_STACKED_FRAMES
:
256 case PIPE_VIDEO_CAP_SUPPORTED
:
258 case PIPE_VIDEO_FORMAT_MPEG12
:
259 return profile
!= PIPE_VIDEO_PROFILE_MPEG1
;
260 case PIPE_VIDEO_FORMAT_MPEG4
:
261 /* no support for MPEG4 on older hw */
262 return rscreen
->family
>= CHIP_PALM
;
263 case PIPE_VIDEO_FORMAT_MPEG4_AVC
:
265 case PIPE_VIDEO_FORMAT_VC1
:
267 case PIPE_VIDEO_FORMAT_HEVC
:
269 case PIPE_VIDEO_FORMAT_JPEG
:
274 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
276 case PIPE_VIDEO_CAP_MAX_WIDTH
:
278 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
280 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
281 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
282 return PIPE_FORMAT_P016
;
284 return PIPE_FORMAT_NV12
;
286 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
287 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
288 if (rscreen
->family
< CHIP_PALM
) {
289 /* MPEG2 only with shaders and no support for
290 interlacing on R6xx style UVD */
291 return codec
!= PIPE_VIDEO_FORMAT_MPEG12
&&
292 rscreen
->family
> CHIP_RV770
;
294 enum pipe_video_format format
= u_reduce_video_profile(profile
);
296 if (format
== PIPE_VIDEO_FORMAT_HEVC
)
297 return false; //The firmware doesn't support interlaced HEVC.
298 else if (format
== PIPE_VIDEO_FORMAT_JPEG
)
302 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
304 case PIPE_VIDEO_CAP_MAX_LEVEL
:
306 case PIPE_VIDEO_PROFILE_MPEG1
:
308 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE
:
309 case PIPE_VIDEO_PROFILE_MPEG2_MAIN
:
311 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE
:
313 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE
:
315 case PIPE_VIDEO_PROFILE_VC1_SIMPLE
:
317 case PIPE_VIDEO_PROFILE_VC1_MAIN
:
319 case PIPE_VIDEO_PROFILE_VC1_ADVANCED
:
321 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE
:
322 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN
:
323 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH
:
325 case PIPE_VIDEO_PROFILE_HEVC_MAIN
:
326 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10
:
336 boolean
rvid_is_format_supported(struct pipe_screen
*screen
,
337 enum pipe_format format
,
338 enum pipe_video_profile profile
,
339 enum pipe_video_entrypoint entrypoint
)
341 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
342 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
343 return (format
== PIPE_FORMAT_NV12
) ||
344 (format
== PIPE_FORMAT_P016
);
346 /* we can only handle this one with UVD */
347 if (profile
!= PIPE_VIDEO_PROFILE_UNKNOWN
)
348 return format
== PIPE_FORMAT_NV12
;
350 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);